JPH0748105B2 - Photo mask - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask, and more particularly to a mask alignment mark and a chip shift confirmation mark of the photomask.

2. Description of the Related Art In recent years, the density of the entire mask pattern layout formed by a plurality of photomasks used in semiconductor integrated circuits (ICs) has been increasing. In this mask pattern layout, the scribe lane for finally cutting the semiconductor wafer and the scribe lane surrounded by this scribe lane
Components such as transistors, aluminum wiring, bonding pads, etc. are provided in the circuit portion of the IC, and mask alignment marks 20 as shown in FIG. 6 are provided in the circuit portion of the IC. Note that, hereinafter, the mask alignment mark formed on the photomask will be referred to as a mask alignment mark, and the shape of the mask alignment mark formed on the semiconductor wafer by the mask alignment mark will be referred to as a mask alignment mark pattern.

At the time of forming an IC, a plurality of photomasks for forming components such as transistors are formed on a semiconductor wafer, and a mask alignment mark having two consecutive process numbers in the order of the process used is formed on each photomask. . For example, for the photomask of the first step, the step number "1" shown in FIG. 6 is used.
And “2” mask alignment marks are provided, and the photomasks of the second process are provided with mask alignment marks of process numbers “2” and “3”. The mask alignment mark of the process number of is provided.

Next, a method of forming a semiconductor integrated circuit (IC) using the photomask having the mask alignment mark formed therein will be described. First, the first diffusion layer of the component is formed on the semiconductor wafer using the photomask of the first step, and then the second diffusion layer of the component is formed on the first diffusion layer of the component using the photomask of the second step. In the case of, the "2" pattern of the mask alignment mark patterns of "1" and "2" formed on the semiconductor wafer formed by the photomask of the first step is provided on the photomask of the second step. The "2" mark of the "2" and "3" mask alignment marks is overlaid and the second component
After forming a diffusion layer, the mask alignment mark "3" provided on the photomask of the third step is replaced with the pattern of "3" on the semiconductor wafer formed by the photomask of the second step. The IC is formed by stacking them on top.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, when the mask mark is laid out in the circuit portion of the IC as in the above-described conventional case, it becomes impossible to form a circuit correspondingly, and this mask alignment mark has a very wasteful area when forming a circuit. Become. Therefore, the conventional mask pattern layout has a problem that the chip size is enlarged by the amount corresponding to the mask alignment mark, the density is not increased, and the chip cost is also increased.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a photomask having a mask alignment mark, which can achieve high density and can reduce chip cost.

Means for Solving the Problems In order to solve the above problems, the photomask of the present invention is provided with a photomask in which the whole process of the photomask is divided into four regions separated by scribe lines in the intersections of the scribe lanes of the plurality of masks. The mask alignment marks of the number of steps obtained by dividing the number into four are divided and arranged, and further, the chip shift confirmation marks are arranged on the intersections of the scribe lines.

Operation According to the above configuration, the mask alignment mark having the number of steps obtained by dividing the total number of steps of the photomask into four is divided into each of four areas partitioned by the scribe line in the intersection of the scribe lanes of the plurality of masks. By arranging,
Since the mask alignment mark is not provided in the circuit portion of the IC, the mask pattern layout is advanced and the chip area is reduced, so that the chip cost can be reduced. Further, by disposing the chip shift confirmation mark on the intersection of the scribe lines, it is possible to reduce the chip shift and the mask shift during mask alignment.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of corner portions of four chips formed by a photomask according to an embodiment of the present invention. In FIG. 1, 11 is a semiconductor substrate (Si wafer), and the hatched portions 12 of the semiconductor substrate 11 show the circuit portions of four chips, respectively. Also, 13 is a chip scribe lane, and a scribe line 14 of the center line in the intersection of the four chip scribe lanes 13 (indicated by a solid line in the drawing, but this line is not The mask alignment mark of the number of steps (two steps in FIG. 1) obtained by dividing the total number of steps (8 steps in FIG. 1) of the photomask into four areas is divided into four areas each divided by The pattern 15 is divided and arranged, and the chip misalignment confirmation mark pattern 16 is arranged on the intersection of the scribe lines 14.

FIG. 2 is an enlarged view of the chip corner portion of FIG. 1, and in the mask alignment mark pattern 15, process numbers for using the photomask in the order of processes are provided.

FIG. 3 shows a pattern 16 of chip misalignment confirmation marks formed on the semiconductor substrate 11 by the photomask of the first step and the photomask of the second step. Scribe line
At the chip corner of each chip partitioned by 14, the pattern 16a of the chip misalignment confirmation mark of the first layer formed by the first step photomask shown in FIG.
The second layer chip misalignment confirmation mark pattern 16 formed so as to surround the first layer chip misalignment confirmation mark pattern 16a by the second step photomask shown in FIG.
Provide b. Then, in each layer of these patterns, one point, which cannot be confirmed by negative / positive, is formed in the first layer and the second layer in order of being displaced in the clockwise direction.

Next, the operation of forming an IC on the semiconductor substrate 11 will be described.

Once the total number of photomask forming steps for the IC has been determined,
The number of mask alignment marks 15 provided at the intersections of the scribe lanes 13 is determined, and as shown in FIGS. 1 and 2, the scribe lines 14 within the intersections of the scribe lanes 13 are determined.
The arrangement of all the mask alignment marks 15 is determined when they are located in the four areas partitioned by. According to the above arrangement, the photomask 11 'in the first step has mask alignment marks 15' of the step numbers "1" and "2" of the photomask 11 'according to the above arrangement, for example, as shown in FIG. Scribe lane 1
It is provided at the intersection of 3 '. Photomask 1 for the second step
For example, as shown in FIG. 5B, mask alignment marks 15 'of process numbers "2" and "3" are provided at 1 "at the intersection of the scribe lane 13' of the photomask 11".
Further, the chip mask confirmation mark 16a 'is provided at the intersection of the scribe lines 14' in the photomask 11 'in the first step of FIG. 5 (a) with one of the four regions missing. Next photomask of the second step of FIG. 5 (b)
A chip misalignment confirmation mark 16b 'is provided on the 11 "in a state in which the chip misalignment confirmation mark 16a' of the photomask 11 'in the first step is cut off by one region in the clockwise direction. A chip shift confirmation mark 16b 'is provided so as to surround the chip shift confirmation mark 16a'.

With the above photomask structure, first, the first diffusion layer of the IC component is formed on the semiconductor substrate 11 by the photomask in the first step, and the process numbers "1" and " A 2 "mask alignment mark pattern 15 is formed, and a chip misalignment confirmation mark pattern 16a of the first layer is formed at the intersection of the scribe lines 14.
Then, in the next second step, the photomask is used as a semiconductor substrate.
When aligning with 11, the mask alignment mark pattern 15 and the chip misalignment confirmation mark pattern 16a of the process number “2” formed on the semiconductor substrate 11 and the mask alignment mark of the process number “2” of the photomask of the second process Fix 15 'and chip misalignment confirmation mark 16b' so that they coincide with each other and overlap. Since the mask alignment mark pattern 15 is formed at the intersection of the scribe lanes 13 of all the chips, the mask alignment can be performed over two chips, so that two-point alignment can be performed and the mask alignment accuracy is improved. be able to. Then, when aligning the mask alignment mark of the photomask of the next process with the mask alignment pattern of the previous process in order, the pattern 15 of the mask alignment mark and the pattern 16 of the chip misalignment confirmation mark of the same number in the process number match. Fix them so that they overlap.

In this manner, the mask alignment mark 15 'and the chip misalignment confirmation mark 16' for each layer, that is, for each process, are divided and arranged at the four corners of the intersection of the scribe lanes on the photomask, so that the chip on which the IC is formed is formed. A pattern 15 of mask alignment marks and a pattern 16 of chip misalignment confirmation marks are present on all corners of the mask.

According to the above configuration, by dividing the mask alignment mark and the chip misalignment confirmation mark in the scribe lane, it is not necessary to consider the layout of the mask alignment mark in the circuit portion of the IC during mask layout,
The mask design time can also be shortened. In addition, by arranging in the corner portion of the chip, the amount of variation between the photomasks is reduced and the accuracy is improved, and since the mask alignment mark is not formed in the circuit portion as in the conventional case, the mask pattern layout is made higher in density. It is possible to reduce the chip size.

EFFECTS OF THE INVENTION As described above, according to the present invention, the mask alignment mark is divided and arranged at the intersection of the scribe lanes, and the chip displacement confirmation mark is provided at the intersection of the scribe lines, so that the chip displacement and the photomask displacement can be prevented. Further, since the mask alignment mark is divided and arranged in the scribe lane and is not provided in the circuit portion as in the conventional case, the mask pattern layout can be made high in density and the chip size can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view of four corner portions of a chip showing the arrangement of a mask alignment mark pattern and a chip misalignment confirmation mark pattern by a photomask according to an embodiment of the present invention,
FIG. 2 is an enlarged view of a corner portion of the chip of FIG. 1, FIG. 3 is a plan view of a semiconductor substrate showing an arrangement of chip misalignment confirmation marks of a photomask according to one embodiment of the present invention, and FIG. 4 (a).
5B is an explanatory diagram of a chip misalignment confirmation mark in a photomask, FIGS. 5A and 5B are explanatory diagrams of a mask alignment mark in each photomask, and FIG. 6 is a mask alignment mark in a conventional photomask. FIG. 11 ... semiconductor substrate, 12 ... circuit part, 13 ... scribe lane,
14 ... Scribe line, 15 ... Mask alignment mark pattern, 16, 16a, 16b ... Chip misalignment confirmation mark pattern,
11 '... Photomask, 13' ... Photomask scribe lane, 14 '... Photomask scribe line, 15'
… Mask alignment marks on photomask, 16a ′, 16b ′…
A mark for checking misalignment of chips on the photomask.

Claims (2)

[Claims] 1. A mask alignment mark having a number of steps obtained by dividing the total number of steps of a photomask into four is divided and arranged in each of four areas partitioned by a scribe line in an intersection of scribe lanes of a plurality of masks. Photo mask. 2. The photomask according to claim 1, wherein a chip shift confirmation mark is arranged on the intersection of the scribe lines.