JPH0748302B2 - Memory device - Google Patents

Description

The present invention relates to a memory device suitable for use in storing image data or program data in an image processing device or the like.

"Prior Art" A memory device has been developed in which data can be rewritten pixel by pixel or bit by bit at a high speed, and a storage area can be selectively used for an image data area and a program area at a high speed (Japanese Patent Application No. Sho-sho). 61-1959
No. 04).

This memory device has a normal mode and a mask mode. In the normal mode, the same access as that of a normal memory is possible, and in the mask mode, bit-wise masking and logical operation are possible.

[Problems to be Solved by the Invention] By the way, when the image memory of the 16-bit data bus is composed of a plurality of chips, a mask process may be necessary even when writing in the normal mode. This point will be described below.

FIG. 19 is a diagram showing a general connection relationship when connecting two 8-bit memories per word to a 16-bit data bus. In the figure, BUS indicates each bit position of the 16-bit data bus, and ME2 and ME3 each indicate a memory in which one word has 8 bits. Each of the memories ME2 and ME3 has a serial register and has a multi-port configuration.

Further, as shown in the drawing, even bits of the data bus are sequentially connected to the 0th to 7th bits of the memory ME2,
The odd bits of the data bus are sequentially connected to the 0th to 7th bits of the memory ME3. In this way, the even and odd bits of the data bus are distributed to the memories ME2 and ME3 in order to facilitate high-speed display of images.

That is, at the time of display, as shown in FIG.
The image data of the corresponding line from 2 and 3 are transferred to the serial registers SR1 and SR2, respectively, and the serial register SR
1, SR2 to dot clock 1/2 clock frequency φ ₁
Is serially converted by and output. These serial data are supplied to a selector SE4, dot clock phi ₂ by the selector SE4 selects alternately the outputs of the serial register SR1, SR2 by the dot clock phi ₂
The serial data based on is output. Further, since even bits and odd bits of the data bus are separately stored in the memories ME2 and ME3, the data combined by the selector SE4 is data having consecutive bit numbers.

With this configuration, the serial register SR
The clock supplied to 1 and SR2 can be half of the dot clock, enabling high-speed display.

However, for the sake of high-speed display, if the memories ME2, 3 and the data bus are connected as described above, the memories ME2, 3
When using as a program or data area, if it is necessary to rewrite only the upper or lower 8 bits, the mask processing becomes necessary. For example, when only the lower 8 bits are rewritten, as shown by the hatched lines in FIG.
It is necessary to write to the portion 2 and mask processing is required.

In addition to the above case, when the bit numbers are discontinuously arranged in one memory chip, the mask processing may be necessary in the normal mode.

However, the memory device described above has no mask function in the normal mode, which is inconvenient when rewriting data of one word or less. That is, according to the mask mode, it is possible to rewrite any bit because masking can be performed in bit units, but it is necessary to switch to the mask mode, and it is necessary to perform processing such as masking in advance for planes that will not be accessed. This is because these processes take time.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory device that can be accessed in bit units even in the normal mode.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a first mode in which an access is performed as a simple memory element and a second mode in which logical operation and masking can be performed on data. In addition, the memory device having the selecting means for selecting the first and second modes has the masking means for masking the data in the first mode.

[Operation] Since the mask function can be activated in the first mode in which access is performed as the simple memory, even if the mask processing is necessary when the memory is used as the program area, the mode is switched to the second mode. Without
Mask processing can be performed.

[Examples] Examples of the present invention will be described below with reference to the drawings.

In the embodiment, the case of displaying 16 colors is taken as an example, and 4 bits are required as a color code. Therefore, as shown in FIG.
Requires 0 to FM3. In this case, each frame memory FM0
Data surrounded by a broken line at the same bit position of FM3 (the direction of this broken line is hereinafter referred to as pixel direction) corresponds to one dot on the display surface. Then, when displaying an image, data is sequentially read out for each pixel of each of the frame memories FM0 to FM3 in accordance with the scanning of the display surface, thereby enabling multicolor display. In practice, as the frame memories FM0 to FM3, a method in which dual port memories are provided in parallel on four sides and pixel data is synchronously read from the serial data output end of each chip is generally adopted. In the case shown in FIG. 18, the access direction when accessing in word units is hereinafter referred to as the word direction (indicated by a chain line arrow in the figure).

§ Overall configuration of the embodiment Fig. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. In the figure, M _{0 to} M ₇ are 1-bit × 64K (or 128K) memories, respectively, which are connected in parallel to form 8-bit × 64K (or 128K) memory block MB0. BTI _{0 to} BTI ₇ are memory M ₀
A bit interface that controls for each bit to exchange data between the ~M ₇ and the data bus IO ₀ ~IO _7, PXI-
Reference numeral 0 is a pixel interface circuit that exchanges 1-bit data in the pixel direction (hereinafter referred to as pixel data) with the data bus IOp-0, and also reads chip select data or plane mask data described later. is there. This pixel interface circuit PXI-0 has bit interfaces BTI _{0 to} BTI.
Either through the TI ₇ are adapted to perform either of the memory M ₀ ~M ₇ exchanging pixel data, and a control signal based on the chip select data and plane mask data bit interface BTI ₀ ~BTI ₇ and timing command control circuit TCC.

The timing command control circuit TCC includes address data supplied externally via the address buses A0 to A7, an output enable signal (control signal) OE,
This is a circuit for performing access control of the memory block MB0 and timing control of each part of the circuit based on the write enable signal WE, the row address / strobe signal RAS, the column address / strobe signal CAS, and the like. The timing command control circuit TCC controls the write enable signals of the memories M _{0 to} M ₇ according to the value of bit mask data (described later) supplied from the bit interfaces BTI _{0 to} BTI ₇ . . Further, the timing command control circuit TCC decodes the command data supplied from the address buses A0 to A7,
Each part of the circuit is appropriately controlled based on the result of this decoding.

The memory device # 0M is configured by the above-described components. Further, this embodiment comprises a total of four parts, that is, the memory device # 0M and the memory devices # 1M to # 3M having the same structure as the memory device # 0M. In this case, the memory blocks in each of the memory devices # 1M to # 3M are MB1 to MB3, the pixel interfaces are PXI-1 to PXI-3, and the data buses connected to the pixel interfaces are IOp-1 to IOp. It is expressed as -3 to distinguish.

FIG. 2 shows a connection state of the memory devices # 0M to # 3M. As shown in FIG. 2, the data buses IO _{0 to} IO _{7 of the} memory devices # 0M to # 3M are commonly connected for each bit. ,Also,
Data bus IOp-0 to IOp-3 of each memory device # 0M to # 3M
However, each has individual wiring.

§ Configuration of each part of the embodiment Hereinafter, the configuration of each part of the circuit described above will be described in more detail.

(I) Outline of Operation Mode for Understanding Configuration First, in order to facilitate the understanding of the configuration of each part of the circuit, the operation mode in this embodiment will be briefly described.

(A) Normal mode In this mode, in principle, any one of the memory devices # 0M to # 3M is selected, and 8 is selected for the selected memory device.
This is a mode for performing data access in bit units (it is possible to access any two or more memory devices as described later). Data in this mode is input / output via the data buses IO _{0 to} IO ₇ . That is, for any of the memory devices # 0M to # 3M, the normal 8
It is a mode in which bit parallel access is performed,
In this mode, the memory is used as a simple memory element.
Then, at the time of writing data, it is possible to enable masking for any bit.

(B) Mask mode This mask mode is a mode in which any one or more bits of input / output data can be masked and any one or more of the memory devices # 0M to # 3M can be masked. is there. In addition, this mode is further divided into a word access mode and a pixel access mode. In the word access mode, data is input / output in the word direction via the data buses IO _{0 to} IO ₇ , and in the pixel access mode. Inputs / outputs data in the pixel direction via the data buses IOp-0 to IOp-3. In the mask mode, it is possible not to mask any bit or any memory device.

The word access mode is the memory block shown in Figure 18.
In the mode to access the data in the word direction of MB0 to MB3 (see the alternate long and short dash line), when performing bit masking, do the following. For example, if you want to access only b _5, b ₇ bits shown in FIG. 18, it accesses the wd ₀ (8 bits) to access the memory block MB0 in the word direction, of the 8-bit data, b ₅ , b ₇ are masked to prohibit access, and b ₅ and b ₇ are accessed.

The pixel access mode is, for example, a mode in which the memory blocks MB0 to MB3 shown in FIG. 18 are accessed in the direction of the Vixel (see the broken line), and when the bit mask is performed, the following is performed. For example, pb ₁ , shown in FIG.
When accessing only the pb ₂ bits, the pixel pc ₀ is accessed and the memory blocks MB0 and MB3 are masked to access the pb ₁ and pb ₂ bits.

The above is the outline of the operation mode in this embodiment.

(II) Configuration of Each Part Next, the configuration of each part of the circuit shown in FIG. 1 will be described.
Since the memory devices # 0M to # 3M have the same configuration, the following description of the configuration will be given by taking the memory device # 0M as an example.

[Timing command control circuit TCC] This timing command control circuit TCC is
As shown in FIG. 1, the timing control circuit TC
And a command / control circuit CC, each of which is shown in FIGS. 3 and 4.

In FIG. 3, Ta to Te are control signal input terminals, and the row address strobe signal RAS is applied to the terminal Ta.
A chip select signal CSW that specifies whether to select the memory device # 0M is input to the terminal Tb, a column address strobe signal CAS is input to the terminal Tc, a write enable signal WE is input to the terminal Td, and a terminal Te is input to the terminal Te. Output enable signal
Each OE is supplied. DL is a delay that delays the row address strobe signal RAS to create a signal RASD, and OR1 ORs the row address strobe signal RAS and the signal RASD to obtain the row address
This is an OR gate that creates a signal RASW in which the pulse width of the strobe signal RAS is lengthened. LFF1 is the chip select signal CS
Latch type flip-flop (hereinafter referred to as L-type flip-flop) that captures the value of W at the rising edge of signal RSAW, AN1 is an AND gate that detects that normal mode is specified, and outputs normal mode enable signal NME, AN2 is a mask An AND gate that detects that a mode is designated and outputs a mask mode enable signal MME, and an AN3 that outputs a command enable signal MCE when a command write cycle to be described later is designated. LFF2, LFF3, LFF4 are L-type flip-flops that take in the values of the enable signals NME, MME, MCE at the rising edge of the signal RASW, and output signals NMA, MKA, MCC from their output ends. Further, AN4 to AN9 are AND gates that create the illustrated signals based on the above signals and control signals supplied from other circuits.

INV10 is an inverter that inverts the signal WPB (see FIG. 4), and AN40 is an AND gate that takes the logical product of the output signal of the inverter INV10 and the signal NMA. OR30 to OR37 are the output signal of the AND gate AN40 and the bit mask signal BM _{0, respectively.}
It is an OR gate that takes the logical sum of ~ BM ₇ . The bit mask signals BM _{0 to} BM ₇ are signals output from the bit interfaces BTI _{0 to} BTI ₇ shown in FIG.

AN10~AN17 takes a logical product of the signal WEP supplied from the bit mask signal BM ₀ to Bm ₇ AND gate AN8 each supplied via the OR gate OR30～RO37, memory M ₀ ~M ₇
It is an AND gate for generating write enable signals WEP _{0 to} WEP ₇ (see FIG. 5). In the above configuration, L
Each of the type flip-flops LFF1 to LFF4 latches data when a "1" level signal is supplied to the latch terminal L which has a negative logic.

Next, referring to FIG. 4, the command / control circuit CC
Will be described. Tad0 to Tad7 shown in the figure are address data input terminals, and the address data input terminals Tad0 to Tad7 are connected to the input terminals of the command register 1, respectively. The command in this embodiment is specified by an 8-bit command code, and this command code is supplied via the address bus. Command register 1 is a row address
The command code is latched at the rising edge of the strobe signal RAS and output as command data MC0 to MC7. Then, the command register 1 transfers the data MC0, which is the least significant bit of the command data, to the data terminal DT of the decoding circuit 3 and the input end of the decoder 2,
The data MC1 to MC3 are supplied to the 0th to 2nd bit input terminals of the decoding circuit 3, and the data MC4 to MC6 are supplied to the 4th 0th to 2nd bit input terminals of the main command decoder. In this case, the upper 4 bits of the command data become the main command data and the lower 4 bits become the sub-command data. However, the most significant bit MC7 of the command data is a don't care bit as can be seen from the figure. The following table shows the relationship between command data MC0 to MC7 values (hexadecimal display) and command names.

It should be noted that in Table 1, only commands relevant to the present invention are described, and the functions of the described commands will be described later.

The decoding circuit 3 uses signals PAM, CME, PME, BCE, LSE, FSB, DBT
It has 0th to 7th D-type flip-flops for respectively outputting ROE and ROE, and one of the D-type flip-flops is selected by the 3-bit data supplied to the input terminal. . That is, the D-type flip-flop having the number corresponding to the 3-bit address data supplied to the input terminal is selected. Then, the data supplied to the data terminal DT is supplied to the input terminal of one of the D type flip-flops selected at that time, and the output signal of the AND gate AN21.
When the MDS rises, it is taken in by the D type flip-flop. That is, the signals PAM, CME, PME, BCE, LSE, depending on the value of the command data MC1 ~ MC3
One of FSB, DBT, and ROE is selected, and the value of the selected signal is rewritten with the value (“1” / “0”) of the command data MC0. Further, a reset signal is supplied from the power-on reset circuit 5 to the clear terminal CL of the decoding circuit 3, and as a result, when the power is turned on, the above-mentioned 0th
All of the seventh D-type flip-flops are designed to be cleared.

The main command decoder 4 outputs a "1" signal from the output end having the number corresponding to the 3-bit data supplied to the input end. This main command decoder 4
Although eight kinds of control signals are output, only the signals RGA and WPB related to the present invention are shown in this figure. Also, the main command decoder 4
Is enabled when the signal MCST is supplied from the AND gate AN20.

The decoder 2 outputs the signal from the timing control circuit TC.
When WEW is supplied and the signal RGA is supplied from the main command decoder 4, the signal is enabled, and if the data MC0 is "0", the signal RPW is output. If the data MC0 is "1", the signal WPW is output. Is output.

Memory blocks MB0] FIG. 5 is a block diagram showing the structure of a memory block MB0, each memory M ₀ ~M ₇ in the memory block MB0 is on the address bus A0~A7 at the rise of the row address strobe RAS Capture the output row address,
When the column address strobe CAS rises, the column address on the address buses A0 to A7 is fetched and the access address is determined. Then, in the read cycle, the output is performed when the signal OEW (output enable signal) rises after the access address is determined, and in the write cycle, the signals in which the signals WEP ₀ to WEP ₇ are at the high level when the access address is determined or thereafter. The data is written to.

[Bit Interface BTIi] FIG. 6 shows the bit interface BTIi (where i =
It is 0-7, and the same shall apply hereinafter), and TIOi (i = 0 to 7) in the figure is a data input / output terminal. The data input from the data input / output terminal TIOi is transferred through the buffer BFF1 to the 0th, 2nd,
Third bit input terminal and L type flip-flop LFF6
It is designed to be supplied to the input terminal of. Selector 10
Is the 0th and the 0th when the signal PAM is "1" and the signal NMA is other than "0".
2, Select the 3rd bit input terminal and output the data supplied to the terminal TIOi. Select the 1st bit input terminal only when the signal PAM is "1" and the signal NMA is "0" to select the pixel interface. It outputs the signal DIP supplied from PXI-0 (see FIG. 7). The output signal WDTi of the selector 10 is supplied to the input terminal of the D type flip-flop DFF7, and the D type flip-flop DFF7 takes in the signal WDTi when the signal WEW supplied from the timing control circuit TC rises. Output signal SR of this D type flip-flop DFF7
Ci is supplied to the corresponding memory Mi via the buffer BFF3 and the data bus DTi sequentially (see FIG. 1). The buffer BFF3 is enabled when the signal WEP supplied from the timing control circuit TC is "1".

The L-type flip-flop LFF6 takes in data when the signal RASW supplied from the timing control circuit TC rises, and its output signal
FBMi is supplied to the first bit input terminal of the selector 11. In the selector 11, a positive voltage is applied to the 0th bit input terminal via a pull-up resistor, and the signal BCE supplied from the command control circuit CC is "0".
When it is, the 0th bit input terminal is selected, and when the signal BCE is "1", the 1st bit input terminal is selected.
The output signal of the selector 11 is supplied to the timing control circuit TC as the bit mask data BMi.

BFF2 is a buffer whose input end is connected to the data bus DTi and whose output end is an output data buffer.
It is connected to 12 data input terminals and the input terminal of buffer BFF5 with open drain output. The output data buffer 12 receives the signal OE supplied from the AND gate AN25.
When i is "1", the data supplied to the input terminal is output to the data input / output terminal TIOi. BFF6 is an open-drain buffer whose input terminal is grounded. The buffers BFF6 and BFF5 are enabled when the signal OEPi supplied from the AND gate AN26 is "1", and each of them is in the enable state. Output signal DOi, -OEPi
To the pixel interface PXI-0.

AND gates AN27 and AN28 have signals MKA, BMi, and RPM, respectively.
The AND gate AN26 is a gate that creates the signal RWX and the signal RPX based on P and PAM, and creates the signal OEPi by taking the logical product of the signal RPX and the signal OEW. Also, OR Gate OR10
Is a gate that takes the logical sum of the signal RWX and the signal NCS, and the AND gate AN25 takes the logical product of the output of the OR gate OR10 and the signal OEW to create the signal OEi.

[Pixel Interface] FIG. 7 is a block diagram showing the configuration of the pixel interface PXI-0. In this figure, TIOp-0 is a pixel data input / output terminal, and the data input from this pixel data input / output terminal TIOp-0 is stored in the buffer BF.
After becoming data DIP via F10, L-type flip-flop LFF10, D-type flip-flop DFF11, DFF12
Of the bit interfaces BTI _{0 to} BTI ₇ (see FIG. 6). The L type flip-flop LFF10 is a timing control circuit TC
When the signal RASW supplied from (Fig. 3) rises, the data supplied to the input terminal is taken in, and the D type flip-flops DFF11 and DFF12 receive the signals WPW and RPW supplied from the command control circuit CC, respectively. It is designed to take in the data supplied to the input terminal when it starts up. L type flip-flop LFF10, D
Output signals FCS, FWP of type flip-flops DFF11, 12
The FRP is supplied to the first bit input ends of the selectors 15, 16 and 17, respectively, and the positive voltage is applied to the 0th bit input ends of the selectors 15, 16 and 17 via pull-up resistors. The selector 15 selects the 0th bit input end when the signal BCE supplied from the command control circuit CC is "0", and selects the 1st bit input end when the signal BCE is "1". Further, the selectors 16 and 17 are respectively the 0th when the signal PME supplied from the command / control circuit CC is "0".
The bit input terminal is selected, and when the signal PME is "1", the first bit input terminal is selected. In this case, it is actually selector 1
Although 6 and 17 are one selector, they are displayed as two selectors for convenience of explanation.

A pixel output data buffer 18 outputs the signal supplied to the data terminal D to the pixel data input / output terminal TIOp-0 when a "1" signal is supplied to the enable terminal E. In this case, a positive voltage is applied to the data terminal D through the pull-up resistor, and the data DO _{0 is} transmitted from the bit interfaces BTI _{0 to} BTI _7.
~ DO ₇ is now available. Further, the enable terminal E of the pixel output data buffer 18
Signal from bit interfaces BTI _{0 to} BTI ₇ -OE
P ₆ to -OEP ₇ are supplied via the inverter INV5, and a positive voltage is applied to the input terminal of the inverter INV5 via a pull-up resistor.

The above is the configuration of each part of the circuit in this embodiment.

§ Operation of the embodiment Next, the operation of this embodiment with the above configuration will be described.

In this embodiment, as described above, in the memory read / write cycle, there are two operation modes, that is, the normal mode and the mask mode. On the other hand, on the other hand, there is a command write cycle for writing a command, which is completely different from the above cycle. Therefore, in the following description, the read cycle and the write cycle will be described in this order, and the normal mode, the mask mode, and the command write cycle will be properly described in each cycle.

(I) Read cycle (a) Normal mode As shown in FIG. 8 (a), when the row address strobe signal RAS rises at time t ₁ , the level of the column address strobe signal CAS is "0". Further, when the write enable signal WE and the output enable signal OE are at "0" level as shown in P ₁ and P ₂ in the same figure, the normal mode is selected. That is, if the above conditions are satisfied, the AND gate shown in FIG.
The output signal NME of AN1 becomes "1" and the normal mode is selected. Then, this signal NME is taken into the L type flip-flop LF2 at the rise of the row address strobe signal RAS, that is, at the rise of the signal RASW, and thereafter, the output signal NMA of the L type flip-flop LFF2.
Keeps "1", which establishes the normal mode.

Then, a column address strobe signal CAS at time t ₂ shown in FIG. 8 rises, the write enable signal WE at this time is "0" level, the read cycle operation is started. At this point, the column address is fixed, and as a result, the address to be accessed is fixed. Therefore, the same address of the memories MB0 to MB3 in each of the memory devices # 0M to # 3M is simultaneously accessed and the data in the address is read. Then, the read data is supplied to the data terminal D of the output data buffer 12 via the data bus DTi and the buffer BFF2 in sequence as shown in FIG. 6, and the output data buffer 12 is enabled. It is output to the data bus IOi at the timing.

The timing at which the output data buffer 12 is enabled is the same as the timing at which the signal OEW becomes the "1" signal when the OR gate OR10 outputs the "1" signal, and the signal OEW becomes the "1" signal. The conditions are column address strobe signal CAS and signal RASW as can be seen from FIG.
It is necessary for the output enable signal OE to be "1" in the state where is "1". That is, in the example shown in FIG. 8, when the output enable signal OE becomes "1" at time t _3, the output data above conditions the output signal of matching the AND gate AN25 becomes "1" Buffer 12 is enabled,
Data is output at the timing shown in FIG.

Next, the conditions under which the OR gate OR10 outputs the "1" signal will be described. In order for the OR gate OR10 to output the "1" signal, either the signal RWX or the signal NCS should be "1", but in this normal mode, the signals MME and MKA are Because it does not reach the "1" level,
The signal RWX, which is the output signal of the AND gate AN27, never becomes "1". Therefore, the output signal of the OR gate OR10 is uniquely determined by the value of the signal NCS. The signal NCS will be described below.

At time t ₁ shown in FIG. 8, the chip select data is input at the time when the row address strobe signal RAS rises, and the 4-bit chip select data is transferred to the input / output terminals TIOp-0 to TIOp-3. Supplied from Then, the chip select data supplied at this time is taken into the L type flip-flop LFF10 (see FIG. 7) in the pixel interfaces PXI-0 to PXI-3 at the rising edge of the signal RASW. For example, suppose that the 0th bit of the chip select data is supplied from the input / output terminal TIOp-0 shown in FIG. It is supplied to each input terminal. In this case, the signal RASW rises at time t ₁ , but the signals RPW and WPW are not output at this time as described later, and therefore the chip select data is taken in only by the L type flip-flop LFF10 and the D type It is not taken into the flip-flops DFF11 and 12. As a result, the value of the signal FCS becomes "1" or "0" corresponding to the chip select data, and the "1" or "0" signal is supplied to the first bit input terminal of the selector 15. When the value of the signal BCE supplied to the selector 15 is "0", the value of the output signal CSMP of the selector 15 is always "1" regardless of the value of the signal FCS (that is, the value of the chip select data). If the value of the signal BCE is "1", the signal CSMP has the same value as the value of the chip select data. This signal CSMP is the third
It is supplied to one input terminal of AND gate AN5 shown in the figure,
Here, the logical product is taken with the signal NMA which has already become the "1" signal. As a result, the output signal NCS of AND gate AN5
The value of is determined by the value of the signal CSMP. Therefore, if the signal BCE is "1", the value of the signal NCS is uniquely determined by the value of the chip select signal. The signal NCS is supplied to one input end of the OR gate RO10 shown in FIG. 6 and determines the output signal value of the OR gate OR10.

As can be seen from the above, if the value of the signal BCE supplied to the selector 15 (Fig. 7) is "1", the output data buffer 12 follows the value of the chip select data and the data is "1". "Is enabled. That is, of the memory devices # 0M to # 3M, only the memory device whose chip select data is “1” sends the read data. For example, as shown in FIG. 9, when only the chip select data supplied to the memory device # 1M is “1”, 8-bit data D _{0 to} D ₇ are output only from the memory device # 1. It

In this figure, the symbol "X" indicates that it is a don't care bit. That is, the output terminal of the output data buffer 12 of the memory device that does not output data has a high impedance.
Also, if the chip select data for two or more memory devices is "1", data is simultaneously output from these memory devices and a race condition occurs on the common data buses IO _{0 to} IO ₇ (see FIG. 2). ), In this case, "0" is given priority for each bit. This is because the output data buffer 12 in each memory device has an open drain output (however, data is usually read from any one memory device).

Then, as can be seen from FIG. 9, in the reading in the normal mode, since it is possible to individually read 8-bit parallel by designating one of the memory blocks,
It is suitable when using the areas in memory blocks MB0 to MB3 as program areas.

On the other hand, when the signal BCE supplied to the selector 15 (FIG. 7) is "0", the chip select function does not work.

Here, the signal BCE will be described. The value of this signal BCE is a signal that becomes "1" when the command "bit / chip select mask enable" shown in Table 1 is supplied, and the command writing in this case is as follows. Done.

First, as shown in FIG. ₁₀ , at time t ₁₀ , the row address strobe signal RAS rises, and if the column address strobe signal CAS and the write enable signal WE are at “1” level at this time, the command write mode is set. Is selected. That is, the column address strobe signal CAS and the write enable signal WE
When both are "1", the signal MCE which is the output signal of the AND gate AN3 shown in FIG. 3 becomes "1", and this "1" signal is an L type flip-flop at the rising edge of the row address strobe signal RAS. Captured by LFF4. Thus, at time t ₁₀ after the output signal of MCC L-type flip-flop LFF4 becomes "1", into the operation of the command write cycle. Also, AND Gate AN9
Output signal MCD becomes "1" while both row address strobe signal RAS and signal RASD are "1". That is, the signal MCD rises slightly later than the rising timing of the row address strobe signal RAS.

On the other hand, the command "bit / chip select mask enable" command is supplied to the command register 1 shown in FIG. 4 through the address buses A0 to A7, and this command is taken in at the rising edge of the row address strobe signal RAS. Since the command "bit / chip select mask enable" is a code represented by (07) in hexadecimal notation as shown in Table 1, the output of the command register 1 is
MC0 to MC2 are "1" signals, the other outputs are "0" signals, and the "1" signal is supplied to the 0th and 1st bit input terminals of the decoding circuit 3. As a result, the decoding circuit 3 enters a state in which the signal BCE corresponding to the decoding result “3” of the input signal can be set to “1”, and the signal BCE is set to “1” at the timing when the signal MDS supplied to the clock terminal rises. To do. The signal MDS, since rises slightly later than the row address strobe signal RAS, signal BCE is "1" signal at the timing slightly delayed from the time t ₁₀ shown in Figure 10. As can be seen from the above, when the memory device according to this embodiment is used as a normal memory, the signal BCE
Is set to "0" and the signal BCE is set to "1" to enable the bit / chip select mask.

The above is the process until the signal BCE becomes “1”. The above-mentioned command "bit / chip select mask enable" is normally written before access in the normal mode, and the chip select data is valid for the memory devices # 0M to # 3M during the normal mode operation. To set. That is, in the normal mode access, at the timing of time t ₁ shown in FIG. 8F, chip select data is supplied from the input / output terminals IOp-0 to IOp-3 and any of the memory devices # 0M to # 3M is supplied. One (or two or more) is selected, and in the subsequent data reading at time t ₄ , data other than the selected memory device is masked. Similarly, also in the next access timing t _5, input-output terminal IOp-
It supplies chip select data for selecting a desired memory device from 0 to IOp-3. By doing so, a desired memory device can be selected prior to the accelerator in the memory read cycle, and the actual chip selection can be performed at extremely high speed.

The above is the normal mode operation in the read cycle.

(B) Mask Mode Next, the operation of the mask mode in the read cycle will be described.

The signal condition of each part of the circuit for setting the mask mode is the normal mode setting described above except that the write enable signal WE is at "1" level at the rise of the row address strobe signal RAS. It is the same as the condition of. That is, if the row address strobe signal RAS rises at time t ₁ shown in FIG. 8, the column address strobe signal CAS and the output enable signal OE are at “0” level at this time, and write enable signal WE as shown in point P ₃ of (d) is a condition that in the "1" level.

When the above conditions are satisfied, the output signal MME of the AND gate AN2 shown in FIG. 3 becomes a "1" signal, and this "1"
The signal is taken into the L-type flip-flop LFF3 at the rise of the row address strobe signal RAS, and thereafter the output signal MKA of the L-type flip-flop LFF3 maintains the "1" level, and the mask mode is determined. Then the time
When the column address strobe signal CAS rises at t ₂ , the column address is fetched at this point and the address to be accessed is determined. Then, at a time t ₄ when a predetermined time has elapsed since the access address was fixed, the write enable signal WE is set to “0” and the output enable signal OE is set to “1”. Data is output, but this data is appropriately masked for each bit and each memory device. Here, the data output state when the mask processing is performed will be described.

FIG. 11 shows the mask state when reading in the word direction, and BM ₀ to BM ₇ and RPMP shown in the figure show the values of the signals shown in FIGS. 6 and 7, respectively. In this figure, a memory device # 0M, # signal RPMP in 3M is "0", the memory device # 1M, signal RPMP is "1 next to the # 2M, a case where the signal BM ₇ to Bm ₀ is (00111100) Shows.
The signals BM _{0 to} BM ₇ have the same value in each of the memory devices # 0M to # 3M, which will be described later.

Now, when the signals BM _{0 to} BM ₇ and the signal RPMP have the values shown in FIG. 11, the 7th, 6th, 1st and 0th bits of the common data bus IO _{0 to} IO ₇ are in the high impedance state (see FIG. Is a "-" symbol, and the fifth, fourth, third, and second bits have a value of (0100), that is, the data of the memory device in which the signal RPMP is "1" and the signal BMi Only the data of the bit for which "1" is set to the output enable state,
Further, when the output data conflict with each other, the "0" signal has priority. The above is the data output after the mask processing when reading in the word direction.

FIG. 12 shows the mask state when data is read out in the pixel direction, and the meaning of the symbols shown in FIG.
It is similar to that shown in the figure. In this case, only the bits of the memory device for which the signal RPMP is "1" and the signal BMi for which it is "1" are in the output enable state, and the corresponding bits in each memory device are applicable. Bits are output to the input terminals TIOp-0 to TIOp-3, respectively. At this time, if data conflict in the same memory device,
The "0" signal has priority and is output.

The setting of the value of the signal BMi and the value of the signal RPMP, and the read operation after the setting will be described below.

Mask mask setting bitwise at time t ₁ shown in Figure 8 (f), the memory device # 0M～ via a common data bus IO ₀ ~IO ₇ as a bit mask data (8 bits) # Supplied to 3M respectively. This bit mask data is data in which the bit to be masked is "0" and the bit not to be masked is "1". Then, one bit in the bit mask data is supplied to the input end of the L type flip-flop LFF6 via the data bus IOi and the buffer BFFI shown in FIG. 6 (common to each memory device). L type flip-flop LFF6
Supplies the mask data supplied to the input terminal at the rising edge of the signal RASW (at the same timing as the rising edge of RAS) and supplies it as the signal FBMi to the first bit of the selector 11. Here, if the signal BCE is set to "1" by the command writing described above, the output signal of the selector 11
BMi takes a value of "0" or "1" in agreement with the value of the mask data. The signal BMi is supplied to the input terminals of the AND gates AN27 and AN28, thereby contributing to the on / off of the signals OEi and OEPi which are the enable signals of the output data buffer 12 and the buffers BFF5 and BFF6. As is clear from FIG. 3, the signal NCS is not output in the mask mode.

In this case, when the output data buffer 12 is enabled, the data read from the memory Mi (see FIG. 1) is sequentially passed through the buffer BFF2 and the output data buffer 12 and is shared by the memory devices. IO
output to i. When the buffers BFF5 and BFF6 are enabled, the data read from the memory Mi is supplied to the input terminal D of the pixel output data buffer 18 shown in FIG. 7 via the buffers BFF2 and BFF5. At the same time, the output signal of the inverter INV5 becomes "1" and the pixel output data buffer 18 is enabled, so that the data read from the memory Mi is eventually the pixel output data buffer.
I / O pin TIOp-0 (or TIOp-1 to TI
Op-3) is supplied. That is, the signal OEi determines permission / non-permission of data output in the word direction, and the signal OEPi determines permission / non-permission of data output in the pixel direction.

Mask setting for each memory device The mask data for each memory device is used for input / output pin TI when the command "Read plane mask" shown in Table 1 is executed.
It is supplied from Op-0 to TIOp-3. FIG. 13 shows that when executing the command “lead plane mask”, first,
As shown in Figure (a), row address strobe signal
At time t ₃₀ the RAS rises, the command write cycle is initiated if the column address strobe signal CAS and a write enable signal WE is "1".
The operation up to this point is the same as in the case of FIG. 10 described above. However, the value to be written to the command register 1 (FIG. 4) at time t ₃₀ is (10) in the hexadecimal notation as shown in Table 1. As a result, only the MC4 of the output of the command register 1 becomes the "1" signal, and the "1" signal is supplied to the 0th bit input terminal of the main command decoder 4. When the signal MCST supplied to the enable terminal rises, the main command decoder 4 decodes the input signal and sets the signal RGA to "1" signal. in this case,
The value of the signal MCST is determined by the logical product of the signal MCD and the signal CSMP. The signal MCD is a signal which becomes "1" at the rising edge of the signal RASD (Fig. 3) in the command write cycle and maintains the "1" level thereafter, and the signal CSMP (see Fig. 7) is described above. Signal BCE is "0"
If the signal BCE is "1", the signal has a value corresponding to the chip select data. Therefore,
The command "Read plane mask" is written as a signal.
This is performed at the rising edge of the signal RAS under the condition that BCE is "1" and the chip select data is "1" or the signal BCE is "0".

As described above, at time t ₃₀ , the command “read plane mask” is written in the command register 1. However, at this time t ₃₀ , since the signal RASD is the “0” signal as shown by the alternate long and short dash line in FIG. 13A, the signal MCD does not become the “1” signal (see FIG. 3),
As a result, the signal MCST shown in FIG. 4 does not become the "1" signal. Therefore, the main command decoder 4 is not enabled. Next, at time t ₃₁ , the row address / strobe signal RAS, the signal RASD, the column address / strobe signal CAS, and the signal WE all become “1” signals, and as a result, the main command decoder 4 is enabled. Set the signal RGA to "1". Also, at time t ₃₁ , the signal WEW becomes “1” (see FIG. 3), and as a result, the decoder 2 is enabled. At this time, the command data MC0 supplied to the input terminal of the decoder 2
Is a "0" signal, the decoder 2 sets the signal RPW to "1" at the timing when it is enabled. This signal RPW is the D type flip-flop DFF12 shown in FIG.
Since it is supplied to the clock terminal of, the D type flip-flop DFF12 takes in the data supplied to the input at this point. On the other hand, mask data for each memory device (hereinafter referred to as read plane mask data)
Is the input / output terminal TIOp-0 at time t ₃₁ shown in FIG.
.About.TIOp-3, the plane read mask data is supplied to the input terminal of the D type flip-flop DFF12 via the buffer BFF10 shown in FIG. As a result, the read plane mask data is taken into the D type flip-flop DFF12 at time t ₃₁ , and the value of the output signal FRP of the D type flip flop DFF12 matches the value of the read plane mask data. And the signal FR
Since P is supplied to the first bit input terminal of the selector 17,
If the signal PME is "1", the value of the signal RPMP matches the value of the read plane mask data. This signal RPMP is the sixth
It is supplied to the input terminals of the AND gates AN27, AN28, shown in the figure,
It contributes to ON / OFF of the signals OEPi and OEi described above.

The signal PME uses the command "plane mask enable".
This signal is "1" when (see Table 1) is executed. The writing of the command "plane mask enable" is performed at the timing shown in FIG. 10 as in the case of the command "bit / chip select mask enable" described above. There are two types of commands in this embodiment, one for writing data to a predetermined flip-flop in the memory device and the other for not writing data, and the one involving data writing depends on the timing shown in FIG. , Those without data writing are written at the timing shown in FIG.

Functions of signal BMi and signal RPMP Signal BM that contributes to bit-wise masking as described above
i and the signal RPMP that contributes to the mask for each memory device are set, and these signals are supplied to the AND gates AN27 and A28. The output signal of the AND gates AN27 and AN28 is the signal OE.
i, OEPi on / off contribution and signal OEi,
Although it has already been described that OEPi contributes to the data output enable in the word direction and the pixel direction, respectively, the relationship between these signals will be described in detail below.

First, as can be seen from FIG. 6, AND gates AN27 and AN
The conditions under which the 28 outputs a "1" signal are the same except for the conditions for the signal PAM. This signal PAM is a signal which becomes “1” when the command “pixel access mode” (see Table 1) is written at the timing shown in FIG. 10, and when the power is turned on and the command “word access mode” is written. It is a signal that is cleared when it is performed. That is, after executing the command "pixel access mode" to set the pixel access mode, the signal PAM becomes "1" and the AND gate AN28 becomes "1" signal output enable state, and the word access mode is set. In this case, the signal PAM becomes "0" and the AND gate AN27 becomes ready to output the "1" signal.

Now assuming that word access mode is selected,
The AND gate AN27 can output the "1" signal, but among the signals supplied to the AND gate AN27, the signal MKA (3rd
(Refer to the figure) shows “1” after the mask mode is set.
Therefore, the output signal of the AND gate AN27 is ultimately determined by the logical product of the signal BMi and the signal RPMP. That is, when both the signal BMi and the signal RPMP are "1", the output signal of the AND gate AN27 becomes "1", and the signal OEW supplied to one input end of the AND gate AN25.
Becomes "1", the signal OEi becomes "1" and the output data buffer 12 is enabled. Therefore, as illustrated in FIG. 11, only the bits for which both the signal BMi and the signal RPMP are “1” are data buses IO _{0 to} IO _7.
Is output to.

Also, when the pixel access mode is selected, the AND gate AN28 can output the "1" signal. However, the output signal of the AND gate AN28 is the logical product of the signal BMi and the signal RPMP just as in the above case. Determined by Therefore, as shown in Fig. 12, only the data of the bit for which both the signal BMi and the signal RPMP are "1" are input / output terminals.
It is output to TIOp-0 to TIOp-3.

The above is the operation of the read cycle in the mask mode, and the desired memory device and the desired bit can be appropriately masked prior to the access in the read cycle, and these settings and switching can be performed at extremely high speed. be able to.

The conditions for setting the states shown in FIGS. 11 and 12 are summarized. In the case shown in FIG. 11, the mask mode setting, the signal PME, the signal BCE are “1”, and the signal is But
The condition is that PAM is "0". In the case shown in FIG. 12, mask mode setting, signal PAM, signal P
The condition is that ME and signal BCE are "1". Further, as shown in FIG. 18, when reading pixel data (4 bits) corresponding to one dot, the signal RPMP in all the memory devices is set to “1” (see FIG. 12) and it is desired to read it. The signal BMi at the position corresponding to the dot may be set to "1".

(II) Write Cycle Next, the write cycle will be described. Similar to the read cycle described above, the write cycle has a normal mode and a mask mode, and further, in addition to these cycles, there is a command write cycle. These will be described below.

(A) Normal mode This mode is similar to the normal mode in the read cycle, and as shown in FIG. 9, data can be written only to the memory device whose chip select data is "1". This is a mode performed in the word direction.

Setting of this mode is exactly the same as that during the read cycle, at time t ₄₀ shown in FIG. 14 (b), when the row address strobe signal RAS rises, the column address strobe signal CAS is "0", Write enable signal WE and output enable signal OE are “0”
If it is at the level, the normal mode is set, the signal NME and the signal NMA shown in FIG. 3 sequentially become "1" signals, and the normal mode is determined.

Next, at time t ₄₁ shown in FIG.
When the strobe signal CAS rises and the write enable signal WE is "1" at this point, the execution of the write cycle is started. At this point, the column address is fixed, and as a result, the address to be written is fixed. Thus, the same address of the memory device # 0M~ # within 3M is accessed simultaneously, data on the common data bus IO ₀ ~IO ₇ in the address are written at the same time. In this case, as in the read cycle described above,
Time t ₄₀ the row address strobe signal RAS rises
In this case, if the chip select data is writable and the chip select data is supplied at this timing and the signal BCE is "1", the memory device in which the chip select data is "1" Data is written only to. This chip select operation will be described below.

First, at time t ₄₁ , which is the data write timing, the data on the supply data bus IOi is supplied to the 0th, 2nd and 3rd bit input terminals of the selector 10 via the buffer BFF1 shown in FIG. . In this case, in the normal mode, since the signal NMA is the "1" signal, the selector 10 selects the second or third bit input terminal. Therefore,
The data supplied to the second or third bit input terminal of the selector 10 passes through the selector 10 and is further captured by the D type flip-flop DFF7 at the rising edge of the signal WEW and output as the signal SRCi. This signal SRCi is supplied to the memory Mi when the buffer BFF3 is enabled, but it is a signal WEP that enables the buffer BFF3.
Does not become a "1" signal unless the signal NCS becomes "1" as shown in FIG. And the value of the signal NCS is
Since it is determined by the logical product of the signal NMA and the signal CSMP,
When the chip select data is “0” and the signal CSMP is “0”, the signal WEP does not become “1” and the signal SRCi is not supplied to the memory Mi. If the signal WEP is not output, the signals WEP _{0 to} WEP ₇ shown in FIG. 3 are not all output, so that the write enable signal is not supplied to the memories M _{0 to} M ₇ (see FIG. 5). No action is taken. As described above, when the signal BCE is "1", data writing is performed only in the memory device whose chip select data is "1".

Further, the OR gate OR30~OR37 shown in FIG. 3, if the output signal of the AND gate AN40 is "1", the write enable signal WEP ₀ ~WEP ₇ is not affected by the signal BM ₀ to Bm ₇ "1"
Becomes In the normal mode, since the signal NMA is the "1" signal, the output signal of the AND gate AN40 is the signal WP.
Determined by the value of B. Therefore, the signal WPB in normal mode when it is "0", regardless of the value of the signal BM ₀ to Bm _7, writes all at once for each memory M ₀ ~M ₇ is performed.

On the other hand, if the signal WPB becomes "1" and the output signal of the AND gate AN40 becomes "1", the write enable signals WEP _{0 to} WE
The value of P ₇ is determined by the signals BM _{0 to} BM ₇ , and writing is performed on the memory for which the write enable signals WEP _{0 to} WEP ₇ are “1”. That is, when the signal WPB becomes “1”, the mask function for each bit operates in the normal mode, and the signals BM _{0 to} BM ₇ that are mask signals function.

Here, the signals BM _{0 to} BM ₇ are set in the same manner as in the read cycle in the mask mode described above. Also the signal WP
The setting of B is performed as follows. That is, the tenth
According to the timing shown in the figure, the command "write per bit" is written in the same manner as in the case of the "bit / chip select mask enable" command writing described above. The main command code (upper 4 bits of the command code) of this command is (4) _H as shown in the above table. And the main command code (4) _H is the 4th
When written in the main command decoder 4 shown in the figure,
The signal WPB output from the main command decoder 4 becomes "1", enabling bit-wise masking in the normal mode. However, as described above, the signal BMi (i =
As can be seen from FIG. 6, all of 0 to 7) become "1" signals when the signal BCE is "0". Therefore, in order to enable the mask function of the signal BMi, the signal BCE must be "1". "It needs to be said. Therefore, in this case, "bit / chip select mask enable" is executed in advance, or (47) _H is written as the command code. Writing to the L-type flip-flop 6 that determines the value of the signal BMi may be performed in the same manner as in the read cycle of the mask mode described above.

(B) a state shown in a mask mode Figure 14, at time t ₄₀ a write enable signal WE is if the "1" level, the mask mode is set. That is, when the write enable signal WE is set to "1" in the state shown in FIG. 14, the signal MME and the signal MKA shown in FIG. 3 sequentially become "1" signals as in the read cycle, and execution of the mask mode is started. To be done. Next, when the column address / strobe signal CAS rises at time ₄₁ , the column address is fetched at this point and the address to be accessed is determined. Then, at time t ₄₁ when the address to be accessed is determined, data writing is immediately performed to the corresponding address as shown in FIG. In this case, the data written in the memory is masked appropriately for each bit and each memory device. The data writing state when the mask processing is performed will be described below.

FIG. 15 shows the mask state when data is written in the word direction, and the signal WPMP shown in the figure is the output signal of the selector 16 shown in FIG. In Figure 15,
Memory device # 1M, # 2M, signal WPMP becomes "1" in # 3M, signal BM ₇ to Bm ₀ shows a case of (00110011).
The signals BM _{0 to} BM ₇ have the same value in each memory device, which is the same as in the read mode described above.

Now, the signals BM _{0 to} BM ₇ and the signal WPMP are in the state shown in FIG. 15, and the data D _{7 to} D _{0 are} as shown in the figure (001011
When 10) is supplied to a memory Mi of the memory device signals WPMP is "1", only the data which corresponds to the bit position signal BM ₀ to Bm ₇ is "1" Is written. In this case, the same data is written in the memory devices # 1M to # 3M in which the writing is performed.

FIG. 16 shows a mask state when data is written in the pixel direction. In the state shown in this figure, the memory Mi of the memory device in which the signal WPMP is “1”, and Data is written only to the memory Mi corresponding to the bit positions where the signals BM _{0 to} BM ₇ are “1”. In writing in this case, data supplied from the input / output terminals TIOp-0 to TIOp-3 are commonly written to the writable bits in each of the memory devices # 0M to # 3M.

The values of the signals BM _{0 to} BM ₇ shown in FIGS. 15 and 16 are set in the same manner as in the read cycle described above.
The value of WPMP is set as follows.

First, the command "light plane mask" shown in Table 1
And the I / O pins TIOp-0 to TIOp-
3 supplies mask data. This command "write plane mask" is a command for writing data in the D type flip-flop DFF11 shown in FIG.
Command writing is performed at the timing shown in the figure.
That is, at time t ₃₁ shown in FIG. 13, the signal WPW shown in FIG. 4 rises, which causes the input / output terminal TIOp
The mask data supplied from −0 to TIOp-3 is the same time.
At t ₃₁ , it is taken into the D type flip-flop DFF11 via the buffer BFF10 shown in FIG. 7 and output as the signal FWP. As a result, the value of the signal FWP matches the value of the mask data. Since the signal FWP is supplied to the first bit input terminal of the selector 16, if the signal PME is "1", the output signal WPMP of the selector 16 becomes a signal having a value that matches the mask data. Further, the signal PME becomes "1" when the command "plane mask enable" is executed, as described above.

Next, the operation of the signal BMi and the signal WPMP will be described. All of these signals contribute to turning on / off the write enable signals WEP _{0 to} WEP ₇ , as shown in FIG. That is, if the signal WPMP is "0", the output signal MWP of the AND gate AN6 becomes "0", and as a result, the output signal of the OR gate OR2 becomes "0" (the signal NCS is always "0" in the mask mode). ). Therefore, the output signal WEP of the AND gate AN8 becomes "0", and the write enable signal WEP ₀ to each memory Mi is output.
~ WEP ₇ is all "0", and writing to any memory is not permitted.

Even if the signal WPMP becomes "1" and the signal WEP becomes "1" at a predetermined timing, the signal BM
_If any of _{0 to} BM ₇ is “0”, the write enable signal WEPi of the bit set to “0” is not output. That is, writing is permitted only in the signal WPMP and the signal BM _0.
~ Only the bit for which both BM ₇ are "1". Then, writing data in the word direction is performed using the common data bus.
IOi → buffer BFF1 (Fig. 6) → 0, 2
The third bit input terminal → D type flip-flop DFF7 → buffer BFF3 → memory Mi transfers the data to be written, and the data writing in the pixel direction is input / output terminal TIOp-i → buffer BFF10 (FIG. 7) → selector The data to be written is transferred through the path of the first bit input terminal 10 (FIG. 6) → D type flip-flop DFF7 → buffer BFF3.

The above is the operation in the mask mode in the write cycle. The desired memory device and the desired bit can be appropriately masked prior to the access in the write cycle, and these settings and switching can be performed at extremely high speed. be able to.

The conditions for setting the states shown in FIGS. 15 and 16 are summarized. In the case shown in FIG. 15, the mask mode setting, the signal PME, the signal BCE are “1”, and the signal is PA
The condition is that M is "0". In the case shown in FIG. 16, mask mode setting, signal PAM, signal PME
The condition is that the signal BCE is "1".

In addition, this embodiment has a late write cycle mode which is a write cycle at a timing different from the write cycle shown in FIG. In this write cycle, as shown in FIG. 17, data writing is performed after a lapse of a predetermined time (time t ₅₂ ) after the column address is fetched.

The above is the configuration and operation of this embodiment.

A triple port memory may be constructed by adding a serial I / O buffer for serially inputting / outputting data to this embodiment.

Further, although the above embodiment is an embodiment in which four memory devices are combined in parallel and used, one or more arbitrary number of memory devices may be used depending on the application.

Further, in the above-described embodiment, the mask function is provided in the normal mode write cycle, but the mask function may be provided in the normal mode read cycle.

A circuit for performing a logical operation such as a raster operation may be added in the bit interface BTIi and the operation may be performed by a predetermined command. As a memory device for performing such calculation, there is, for example, Japanese Patent Laid-Open No. 61-195901.

[Advantages of the Invention] As described above, according to the present invention, in addition to having the first mode for performing access as a simple memory element and the second mode for performing logical operation and mask on data, In the memory device having the selecting means for selecting the first and second modes, the masking means for masking the data in the first mode is included.
Even if the mask processing is required when the memory is used as the program area, the mask processing can be performed without switching to the second mode. Therefore, the mask processing can be performed in the program area without lowering the processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a connection state of a memory device,
3 is a block diagram showing the structure of the timing control circuit TC, FIG. 4 is a block diagram showing the structure of the command control circuit CC, FIG. 5 is a block diagram showing the structure of the memory block, and FIG. 6 is a bit diagram. FIG. 7 is a block diagram showing the structure of the interface, FIG. 7 is a block diagram showing the structure of the pixel interface, FIG. 8 is a timing chart of the read cycle of the same embodiment, and FIG. 9 is data input / output of each memory device in the normal mode. Figure showing state, No.
10 and 13 are timing charts of the command write cycle, and FIGS. 11 and 12 are diagrams showing the relationship between the mask state and the output data during the read cycle, respectively.
Figure 14 is the write cycle timing chart, Figure 15,
FIG. 16 is a diagram showing the relationship between the mask state and write data in each write cycle, FIG. 17 is a timing chart of the late write cycle, and FIG. 18 is a conceptual diagram showing the relationship between the frame buffer and the display surface. , FIG. 19 is a block diagram showing a circuit example when the bit numbers of the memory and the data bus do not continuously correspond, and FIG. 20 is a circuit example when performing display using two memories having serial ports. It is a block diagram showing. 4 ... Main command decoder, AN40, AN10 to 17 ... AND gate, OR30 to OR37 ... OR gate (mask means above), LFF6 ... L type flip-flop (mask data storage means).

Claims (3)

[Claims] 1. A first access for a simple memory device
And a second mode in which a logical operation and a mask can be performed on the data, and a memory device having a selecting means for selecting the first and second modes, the data is masked in the first mode. A memory device having a masking means for performing. 2. The masking means is provided with masking data storage means for permitting a masking function when a predetermined command is supplied and for setting maskability for each bit. The memory device according to claim 1. 3. The mask means is capable of writing mask data to the mask data storage means at a timing when an address is determined in a write cycle when an access as a simple memory element is performed. The memory device according to claim 2.