JPH0748647B2 - Duty ratio discrimination circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a pulse signal duty ratio determination circuit,
In particular, the present invention relates to a duty ratio discriminating circuit capable of discriminating the duty ratio of a pulse signal whose period changes.

[Conventional technology]

Pulse signals are used to represent digital values in remote control of home electric appliances, index signals of VTR devices, and bar codes. For example, duty ratio 70%
The pulse signal of 1 is determined as “1”, the pulse signal having a duty ratio of 40% is determined as “0”, and data is expressed by a combination of these two types of pulse signals. As an example, the data 1011 is represented by the pulse signal shown in FIG.

A device that expresses 1,0 data by the method described above has a built-in circuit for determining the duty ratio of the input pulse signal.

As an example, a case of making a determination with a microcomputer will be described.

Here, a VTR index signal is assumed as the pulse signal. For the VTR index signal, two types of duty ratio of the playback control signal (hereinafter referred to as PBCTL signal) are set, and 1,0 data is expressed by the difference in duty ratio. The PBCTL signal is recorded in the longitudinal direction of the magnetic tape and is a signal used for servo control during VTR reproduction.

FIG. 9 shows a conventional duty ratio discrimination circuit. This circuit is for discriminating the VTR index signal.

First, the configuration of each part will be described.

The PBCTL signal 1 is a VTR reproduction control signal.

The CPU 101 is a central processing unit that controls the entire system according to a program. In addition, the edge detection signal 110 activates the interrupt processing program.

Both edge detection circuit 102 receives PBCTL signal 1 as input,
When the rising edge or the falling edge of the signal 1 is detected, the high active edge detection signal 110 is output.

The counter 105 receives the clock signal 106 as an input, counts the number of pulses thereof, and outputs a count signal 120.

The clock signal 106 is a pulse signal with a constant interval.

The capture register 107 receives the count signal 120 and the edge detection signal 110, and latches the count signal 120 when the edge detection signal 110 is input. When the CPU 101 executes the reading process of the capture register 107, the capture signal 1
21 is output to the bus line 108.

The bus line 108 is a bus for transferring data.

Next, the operation will be described with reference to the timing chart of FIG.

The edge detection signal 110 is generated at the rising edge of the PBCTL signal 1, and the capture register 107 latches the count signal 120. The capture value at this time is n ₁ . On the other hand, when the edge detection signal 110 is generated, the CPU 101 starts interrupt processing. The CPU 101 is an interrupt processing program and reads the capture signal 121 and stores it in a register in the CPU 101. Therefore, n ₁ will be stored.

After that, the interrupt processing ends.

Next, the edge detection signal 110 is generated at the falling edge of the PBCTL signal 1, and the capture register 107 latches the count signal 120. The capture value at this time is n ₂ . When the edge detection signal 110 is generated, the CPU 101 starts interrupt processing. The CPU 101 reads the previous capture value n ₁ from the register in the CPU 101 by the interrupt processing program, and calculates the difference t ₁ = n ₂ −n ₁ (1) from the current capture value n ₂ . t ₁ indicates the pulse width of the PBCTL signal 1 in the high level section. On the other hand, the cycle T of PBCTL signal 1 is 33 [m
s] is constant. Therefore, whether PBCTL signal 1 is signal "1" (duty ratio 70%) or signal "0" (duty ratio 40%)
%) Can be determined from the relationship. The CPU 101 uses equation (2),
After the program determines which of the expressions (3) holds, the interrupt processing is ended.

After that, similar processing is repeated to sequentially determine the signal “1” or the signal “0”.

[Problems to be Solved by the Invention]

The circuit described above has no problem when the cycle of the PBCTL signal 1 is 33 [ms] (during reproduction). However, in the VTR index search mode, the tape is run at a higher speed than during normal playback, and therefore equations (2) and (3) do not hold. Therefore, the duty ratio cannot be determined by the circuit described above.

That is, the conventional duty ratio determination circuit has a configuration in which the duty ratio cannot be determined when the cycle of the input pulse signal changes.

[Means for Solving the Problems]

The pulse signal duty ratio determination circuit of the present invention includes a counter that counts a predetermined clock, a capture register that latches the value of the counter at the edge of an input pulse, and a clear unit that clears the value of the counter after capture. A compare register that stores a value, a comparator that outputs a match signal when the values of the counter and the compare register are compared and matches, and a storage circuit that stores the level of the input pulse when the match signal occurs, An arithmetic circuit for reading the value of the capture register and performing a predetermined arithmetic operation to set a comparison value in the compare register.

That is, the pulse signal duty ratio determination circuit according to the present invention determines the duty ratio by measuring the period of the pulse signal and latching the level of the pulse signal at the timing corresponding to the period. Therefore, the duty ratio can be determined even if the cycle of the pulse signal changes.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. First, each component will be described.

The PBCTL signal 1 is a VTR reproduction control signal.

The CPU 2 is a central processing unit that controls the entire system according to a program. Further, the edge detection signal 13 activates the interrupt processing program.

The rising edge detection circuit 12 receives the PBCTL signal 1 and
When the rising edge of the TL signal 1 is detected, a high active edge detection signal 13 is output.

The delay circuit 14 delays the edge detection signal 13 by one clock and outputs it as the clearing means 15 to clear the counter 16.

The counter 16 receives the clock signal 17 as an input, counts the number of pulses thereof, and outputs a count signal 40.

The clock signal 17 is a pulse signal with a constant interval.

The capture register 18 receives the edge detection signal 13 and the count signal 40, and latches the count signal 40 when the edge detection signal 13 is input. In addition, the CPU2 sends the capture signal 41 for reading the capture register 18 to the bus line.
Output to 22.

The compare register 19 latches the data on the bus line 22 and outputs the compare signal 42 when the CPU 2 executes the writing process to the compare register 19.

The comparator 20 receives the count signal 40 and the compare signal 42 as inputs, compares them, and outputs a high-active coincidence signal 21 when the comparison result is true.

The bus line 22 is a bus that transfers various data.

The D latch 23 receives the match signal 21 and the PBCTL signal 1, and latches the level of the PBCTL signal 1 when the match signal 21 is input. When the CPU 2 executes the reading process of the D latch 23, it outputs the Q output of the D latch 23 to the bus line 22 as the duty discrimination signal 43.

Next, the operation will be described.

FIG. 2 shows the principle of determining the duty ratio. In the present invention, the duty ratio is determined by the level of the PBCTL signal at a specific time, instead of measuring the pulse width of the PBCTL signal. The time to determine the level is the time when 55% of the period of the PBCTL signal has elapsed from the rising of the PBCTL signal.

In this example, 55%, which is an intermediate value between the duty ratio 40% of the signal “0” and the duty ratio 70% of the signal “1”, is set as the level determination time. However, it may be between 40% and 70%. You may decide anywhere (eg 50%). Signals "0", "1"
Even when the duty ratio is different from that in this example, a value between the duty ratio of the signal “0” and the duty ratio of the signal “1” may be used as the level determination time, as in the present example. For example, the signal “0”
If the duty ratio is 50% and the signal “1” is 90% duty ratio, the level judgment time is set to about 70%.

FIG. 3 shows a timing chart of the operation.

The edge detection signal 13 is generated in synchronization with the rising edge of the PBCTL signal 1, and one clock after that, the clear means 15 is output, so that the counter 16 is cleared. Therefore, the counter 16 operates as an interval timer which is cleared in synchronization with the rising edge of the PBCTL signal 1.

Further, since the rising edge detection signal 13 of the PBCTL signal 1 is output, the capture register 18 latches the count signal 40.

At this time, since the value immediately before clearing the counter 16 is latched, the capture register 18 latches a value equal to the cycle of the PBCTL signal 1.

On the other hand, when the edge detection signal 13 is generated, the CPU 2 starts interrupt processing. In the interrupt processing, the CPU 2 writes a value equal to 55% of the cycle of the PBCTL signal 1 in the compare register 19. Specifically, the capture signal 41 is sent through the bus line 22.
Is read, multiplied by 0.55, and written to the compare register 19 through the bus line 22. After that, the interrupt processing ends.

Since the count signal 40 coincides with the compare signal 42 at 55% of the cycle of the PBCTL signal 1 from the rise of the PBCTL signal 1, the comparator 20 outputs the coincidence signal 21. At this time, the D latch 23 latches the level of the PBCTL signal 1. Therefore, a low level is latched when the signal having a duty ratio of 40% is "0", and a high level is latched when the signal is "1" having a duty ratio of 70%. The CPU 2 can determine the duty ratio only by reading the duty ratio determination signal 43 through the bus line 22. It is not necessary to perform an operation for judging the duty ratio.

Thereafter, similar processing is repeated to sequentially determine the signal “0” or the signal “1”.

The duty ratio discrimination circuit described above operates normally even if the cycle of the PBCTL signal 1 changes.

FIG. 4 is a timing chart when the cycle of the PBCTL signal 1 becomes gradually smaller. In the present invention, the duty ratio determination timing also changes as the cycle changes, so PB
The duty ratio can be determined regardless of the size of the cycle of the CTL signal 1. At this time, for example, the duty ratio discrimination in the cycle 2 needs to be accurately performed at the timing of the cycle 2 × 0.55, but actually, it is performed at the timing of the cycle 1 × 0.55. In practice, the VTR tape speed does not accelerate or decelerate instantly, so for a while the cycle 1
There is no problem even if it is judged at the timing of × 0.55. Figure 5 shows PB
It shows that the duty ratio can be correctly discriminated when the cycle of the CTL signal 1 is longer than the original cycle (), when it is shorter (), and when the duty ratio is inaccurate (). As shown in FIG. 5, the duty ratio can be determined from 0.79 times to 1.37 times the original cycle.

Here, an example in which the duty ratio determination timing is updated every time has been described, but since the cycle variation of the PBCTL signal 1 is gentle, the number of times the duty ratio determination timing is updated may be reduced. In the present invention, the calculation of the CPU 2 is required only for the update process of the determination timing, and the calculation is not necessary for the duty ratio determination. Therefore, if the number of times of updating the determination timing is reduced, the load on the CPU 2 becomes very small.

Further, even when the duty ratios of the signals “0” and “1” are different from those in this example, it is possible to deal with the situation by changing the value written in the compare register 19. For example, when the tape is reversed (rewound), the duty ratio of the signal "0" is 60% and the duty ratio of the signal "1" is 30%. At this time, 45%, which is an intermediate value between 60% and 30%, may be written in the compare register 19.

As described above, the duty ratio discrimination circuit of the present invention is
Since the determination timing is changed according to the cycle of the input pulse signal, the duty ratio can be determined even if the cycle of the input pulse signal changes. Since the duty ratio is determined by latching the level of the input pulse,
There is an advantage that the calculation for the duty ratio determination is unnecessary and the load on the software is small.

Further, there is an advantage that even when the duty ratio of the input pulse signal is changed, it can be dealt with by the program.

FIG. 6 is a block diagram of another embodiment of the present invention. The configurations and operations other than the shift register 32 and the duty ratio discrimination signal 44 are the same as those in the first embodiment, and thus the description thereof will be omitted.

The shift register 32 is an 8-bit shift register which receives the PBCTL signal 1 and the coincidence signal 21 and takes in the level of the PBCTL signal 1 when the coincidence signal 21 is input to the least significant bit. CP
When U2 executes the read process of the shift register 32,
The data held in the shift register 32 is output as a duty ratio discrimination signal.

Next, the operation will be described. The duty ratio determining operation and the determination timing updating process are the same as those in the first embodiment, and thus the description thereof will be omitted. In this embodiment, the determination result of the duty ratio is D
Put in 8-bit shift register 32 instead of latch.
Therefore, it is not necessary to read the duty ratio discrimination signal 44 into the CPU 2 every time, and it is sufficient to read it once every eight cycles. Since the index signal is expressed by a code that combines the signal "0" and the signal "1", the index signal is not missed by being read only every eight cycles. An example in which the code of the index signal is 10100101 is shown in FIG.

In the present embodiment, by incorporating the duty ratio discrimination result in the shift register, the software processing for reading the discrimination result can be reduced.

〔The invention's effect〕

As described above, the present invention determines the duty ratio by latching the level of the pulse signal at the determination timing according to the cycle of the pulse signal. Therefore, there is an effect that the duty ratio can be determined even if the cycle of the pulse signal changes. In addition, there is an effect that software processing is not required for determining the duty ratio.

Further, even if the duty ratio is changed, it can be dealt with by the program, so that the duty ratio can be discriminated even when the tape is reversed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a principle diagram of duty ratio discrimination of this embodiment, FIG. 3 is an operation timing chart of this embodiment, and FIG. 4 is an input pulse in this embodiment. 5 is an operation timing chart when the signal cycle changes, FIG. 5 is a diagram showing duty ratio determination when the input pulse signal cycle changes in this embodiment, and FIG. 6 is a block of another embodiment of the present invention. FIG. 7 is a diagram showing the holding of the duty ratio discrimination result in the embodiment of FIG. 6 of the present invention, FIG. 8 is a diagram showing an example of data by pulse signals, and FIG.
FIG. 10 is a block diagram of a conventional example, and FIG. 10 is an operation timing chart of the conventional example. 1 ... PBCTL signal, 2 ... CPU, 12 ... rising edge detection circuit, 13 ... edge detection signal, 14 ... delay circuit, 15
…… Clearing means, 16 …… Counter, 17 …… Clock signal, 18 …… Capture register, 19 …… Compare register, 20 …… Comparator, 21 …… Match signal, 22 …… Bus line, 23 …… D latch , 32 …… shift register, 40…
… Count value, 41 …… Capture value, 42 …… Compare value, 43 …… Duty ratio judgment value, 44 …… Duty ratio judgment value, 102 …… Both edge detection circuit, 105 …… Counter, 10
6 ... Clock signal, 107 ... Capture register, 108
... bus line, 109 ... CPU, 110 ... edge detection signal, 120 ... count value, 121 ... capture value.

Claims (1)

[Claims] 1. A counter for counting a predetermined clock, a capture register for latching the value of the counter at the edge of an input pulse, clear means for clearing the value of the counter after capture, and a compare register for storing a comparison value. A comparator that outputs a match signal when the values of the counter and the compare register are compared and matches, a storage circuit that stores the level of the input pulse when the match signal occurs, and a value of the capture register And an arithmetic circuit for reading a predetermined value and performing a predetermined arithmetic operation to set a comparison value in the compare register.