JPH0748662B2 - D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D / A converter.

[Conventional technology]

The conventional D / A conversion device, for example, as shown in FIG. 2, inputs the upper m bits of digital data from the upper input terminals 11, 12 to 1m, and performs the D / A conversion on the first D / A. Converter 60,
Lower n of digital data from lower input terminals 21, 22, ..., 2n
A second D / A converter 50 that inputs bits and performs D / A conversion, and
The A converters 60 and 70 are composed of a weighted adder 70 that weights the outputs with a ratio of 2 ⁿ : 1 and performs analog addition, and outputs the outputs to the output terminal 80.

[Problems to be solved by the invention]

In the conventional D / A converter described above, in order to keep the accuracy within 1/2 LSB, the accuracy of the first D / A converter 60 is less than 1/2 LSB of the second D / A converter 50. I have to keep it, and as a result 1 /
A relative accuracy of 2 ^{m + n} is required, for example m = 4, n = 4
And the case even 1/2 ^8, namely 0.4%, in the case of the m = 9, n = 9, 1/2 18, that is, has become necessary 0.0004% of relative accuracy, without adjustment of the precision The drawback is that it is difficult to implement, much less impossible to implement on an integrated circuit.

[Means for solving problems]

The D / A conversion device of the present invention has an upper input terminal for inputting upper m bits of digital data, a lower input terminal for inputting lower n bits of digital data, an output terminal, and an upper portion of digital data higher than the upper input terminal. The first D / A converter that inputs m bits and performs D / A conversion, and the error of the actual output of the first D / A converter with respect to the input of the upper m bits from the ideal output of the upper m bits A memory which is stored in advance corresponding to each input, and when the upper m bits of the digital data are input, the corresponding error is converted and output in 1LSB units of the lower n bits of the digital data, and the lower input A digital arithmetic circuit that inputs the lower n bits of digital data from the terminal and the output of the memory and corrects the digital amount of the lower n bits of the digital data by the output of the memory. The second of the output corrected by the circuit D / A conversion
D / A converter and a weighted adder for adding the outputs of the first and second D / A converters by weighting the upper and lower weights and outputting the result to the output terminal.

[Action]

Since the lower n bits of the digital data are corrected by the error of the first D / A converter held in the memory corresponding to the upper m bits of digital data, the first D / A is substantially corrected. The error of the A converter has been removed, and the error is the second D that D / A converts the corrected lower n bits.
Only the error of the / A converter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the D / A converter of the present invention.

The first D / A converter 6 inputs the upper m bits of digital data from the upper input terminals 11, 12, ..., 1m and performs D / A conversion. In the memory 3 (ROM), the error between the ideal output and the actual output of the first D / A converter 6 for the upper m bits of each digital data is measured, and the error is the lower n bits of the digital data.
It is converted in units of 1 LSB of the bit and is stored as the upper m bits of data as an address, and error data converted in units of 1 LSB of the lower n bits of digital data is output.

The digital arithmetic circuit 4 inputs the error data output from the memory 3 and the lower n bits of the digital data, determines whether the error data should be added to or subtracted from the lower n bits from the content of the error data, and based on the determination. Calculate and output the calculation result. The second D / A converter 5 performs D / A conversion based on the calculation result of the digital calculation circuit 4 including positive and negative signs. The weighted adder 7 weights the outputs of the first and second D / A converters 5 and 6 into upper and lower weights and adds the outputs, and outputs the output terminal 8.
Output to.

Therefore, the error of the second D / A converter 5 is not corrected, but the error of the first D / A converter 6 is corrected by the data of the memory 3, so that it is compared with the conventional D / A converter. hand,
In fact, the accuracy is increased by 2 ⁿ times.

In the above-described embodiment, the second D / A converter 5 is capable of outputting positive and negative, but the data in the memory 3 may be data in which a fixed number is added in advance so that the error does not become negative. Good. In this case, the digital arithmetic circuit 4 may be an adder. Of course, the added constant number causes the output voltage of the output terminal 8 to deviate by that amount, but when used in an audio device or the like, a DC component is unnecessary and DC cut is easy, so there is no problem. . But,
It is obvious that a level shift circuit may be added to eliminate the deviation. According to this embodiment, an inexpensive D / A conversion device that operates with a single power source can be realized.

It is also possible to use the RAM instead of the ROM as the memory 3 and execute the calibration cycle when the power is turned on or when necessary to write the error data in the RAM. Further, it is also possible to use a PROM as the memory 3 and write the error data at the time of factory shipment. In this case, the user is unlikely to readjust later, so that the one-time ROM or the fuse ROM can be used.

〔The invention's effect〕

As described above, according to the present invention, the upper m of digital data are
A first D / A converter for D / A converting bits, a memory circuit for holding error data from an ideal value of the output of the first D / A converter, and a memory circuit for storing lower n bits of digital data. A digital arithmetic circuit that corrects the error data held by the second arithmetic circuit, a second D / A converter that performs D / A conversion on the output of the digital arithmetic circuit,
Since the outputs of the first and second D / A converters are configured with a weighted adder that weights and adds the upper and lower weights, the first and second D / A converters have low accuracy. Also has the effect of realizing high-precision and high-bit D / A conversion in which the error of the first D / A converter is removed, and even when it is implemented in an integrated circuit, the first, second
Since the D / A converter is rough compared to the accuracy of the entire device, it has the effect of being easy to implement.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a D / A converter of the present invention, and FIG. 2 is a block diagram showing a conventional example. 11,12, ..., 1m ... High-order input terminal, 21,22, ..., 2n ... Lower-order input terminal, 3 ... Memory, 4 ... Digital arithmetic circuit, 5 ... Second D /
A converter, 6 ... First D / A converter, 7 ... Weighted adder, 8
… Output terminal.

Claims (1)

[Claims] 1. An upper input terminal for inputting upper m bits of digital data, a lower input terminal for inputting lower n bits of digital data, an output terminal, and an upper m bit of digital data for inputting from the upper input terminal. The first D / A converter that performs D / A conversion according to the above, and the error of the actual output of the first D / A converter with respect to the above m-bit input from the ideal output corresponds to each upper m-bit input. The measured value is stored in advance, and a value obtained by adding a constant whose error correction value does not become negative is stored. When the upper m bits of digital data are input, the corresponding added value is stored in the lower n bits of the digital data. ILSB unit of the digital data is converted and output, the lower n bits of the digital data from the lower input terminal and the memory output are input, and the digital amount of the lower n bits of the digital data is output from the memory. Corrected by the amount the digital arithmetic circuit and a second to D / A converts the corrected output by a digital arithmetic circuit
D / A converter, and a weighting adder for adding the outputs of the first and second D / A converters by weighting the upper and lower levels and outputting the result to the output terminal.