JPH0749733A - I / O interface circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an input / output interface circuit device for high speed operation. Structure: Both ends of a transmission line 3 are connected to a terminal to which a terminal voltage is supplied via a terminal resistor 2, and a driver / receiver section and a data transmission / reception logic circuit 90 for transmitting / receiving data are included. In an input / output interface circuit device in which a plurality of integrated circuits 100 for exchanging data via the transmission line are connected to a transmission line 3, a driver / receiver unit of the plurality of integrated circuits 100 is provided from the plurality of integrated circuits. The driver / receiver unit 200 is configured to be separated and independent, and to be shared as the driver / receiver unit 200.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output interface circuit device, and more particularly, to an input / output interface circuit device having a low input / output capacity composed of MOS transistors.

[0002]

2. Description of the Related Art Recently, with the increase in speed of MPU and memory,
There is an increasing demand for input / output interfaces capable of high-speed transmission. In conventional TTL level transmission, it has become difficult to achieve high speed due to noise such as reflection, and a low amplitude level input / output interface circuit device with low amplitude level like ECL level and further low power consumption is proposed. Is beginning to be. This aims at speeding up the transmission line by charging / discharging the transmission line at high speed by suppressing noise such as reflection by matching-terminating the transmission line and making the amplitude small.

FIG. 6 shows the configuration of a conventional example of the input / output interface circuit device of the small amplitude operation (USP 502348).
8). The operation of this input / output interface circuit device will be briefly described. In the figure, the input / output interface circuit device includes a terminating resistor 2 for matching termination at both ends of the transmission line 3.
Are connected to the transmission line 3 connected to the power supply terminal 1 to which the termination voltage is supplied, and the driver 4, the receiver 8, the electrostatic protection capacitor 5, and the data transmission / reception logic circuit 9 are connected to the transmission line 3.
A very large scale integrated circuit (VLSI) 100 of 0s is configured to be connected in an arbitrary number.

The operation on the transmission line 3 is an open drain N channel M which serves as a driver in the VLSI 100.
When the OS transistor 4 transmits a low level signal (hereinafter referred to as “L”) data from the data transmission / reception logic circuit 90, a high level signal (hereinafter referred to as “H”) at its gate.
Is applied to turn on, and the potential of the transmission line 3 is N.
The output voltage V _OL of the channel MOS transistor 4 is pulled down to "L". On the other hand, at the time of transmitting “H” data, “L” is applied to the gate to turn off the N-channel MOS transistor 4, and the potential of the transmission line 3 is pulled up to the level of the termination voltage supplied to the power supply terminal 1. It becomes "H". That is, the voltage amplitude on the transmission line 3 is the termination voltage (1.2 V) -output voltage V _OL (0.4 V) of 0.
This is a configuration with a small amplitude of 8V. Due to this small amplitude operation, charging / discharging of the stray capacitance in the transmission line 3 can be accelerated.

Further, by matching the terminating resistor 2 with the characteristic impedance of the transmission line 3 and an arbitrary number of loads of the VLSI 100 serving as the load, noise such as reflection is suppressed and high speed is supported. For the receiver, the terminal voltage (1.2V) or "L" which becomes "H" on the transmission line 3
In this configuration, the small amplitude level of the output voltage V _OL (0.4 V) of the driver is compared with V _ref (0.8 V) which is the reference voltage by the differential comparator 8 to receive the data.

[0006]

It is obvious that in the future, higher-speed transfer will be required more and more, and there is a tendency that more VLSIs 100 to be transmitted and received as a transmission system can be connected to the transmission line 3. is there.

In the circuit system of the above-mentioned prior art, a small amplitude operation is performed to speed up charging and discharging of the transmission line 3. However, in addition to the capacity of the transmission line 3, an arbitrary number of VLSIs 100 connected to the transmission line 3 can be used. The load capacity increases and the speeding up due to charging and discharging is hindered. The delay time t ₀ in the transmission line 3 itself to which the load is not connected is the inductance L _{0 of} the unit length of the distributed constant and the capacitance C _{0 of the} unit length.
Then, it is represented by t ₀ = √ (L ₀ + C ₀ ), and if an arbitrary number of VLSIs 100 are connected to this, the load (VLSI 10
The delay time t _L of the transmission line 3 including 0) is VLSI10.
The line capacitance up to the transmission line 3 which is 0, the package capacitance, the junction capacitance of the driver 4 which is the input / output capacitance and the electrostatic protection capacitance 5 are t _L = √ from the load capacitance C _L determined by the number of VLSI 100 and the arrangement interval. It becomes {L ₀ (C ₀ + C _L )}, which is about three times slower in one example.

Further, the characteristic impedance on the transmission line 3 is also reduced to about 1/3 due to the load capacitance C _L , and the terminating resistor 2 must be made small for matching. It also affects the characteristics of 4.

Therefore, the transmission line 3 including the load capacity is also included.
It is very important to reduce the above capacity as much as possible in order to achieve high speed in the transmission system.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an input / output interface circuit device having a high speed.

[0011]

In the input / output interface circuit device of the present invention, both ends of a transmission line are connected to terminals to which a terminal voltage is supplied via terminal resistors, and a driver / receiver section and data transmission / reception are provided. In an input / output interface circuit device comprising a plurality of integrated circuits for transmitting / receiving data via the transmission line, the input / output interface circuit device including a logic circuit for transmitting / receiving data, / A receiver unit is independent of the plurality of integrated circuits and is shared.

In the input / output interface circuit device of the present invention, the driver / receiver section is a logic circuit for taking the logical sum of output signals from a plurality of integrated circuits including a data transmission / reception logic circuit for transmitting / receiving data. A sum circuit,
An N-channel MOS transistor as a driver having a gate connected to the output terminal of the OR circuit, a drain connected to the transmission line, and a source connected to the ground terminal, and electrostatic protection connected between the transmission line and the ground terminal. And a differential comparator as one or more receivers, one input terminal of which is connected to the transmission line and the other input terminal of which is connected to a power supply line to which a reference voltage is supplied. It is characterized by

In the input / output interface circuit device of the present invention, an input terminal for receiving a signal from the differential comparator of the data transmitting / receiving logic circuit in each of the plurality of integrated circuits and an output terminal for outputting a signal to the OR circuit. And are separately provided.

The input / output interface circuit device of the present invention is characterized in that one differential comparator as a receiver is used in common.

In the input / output interface circuit device of the present invention, the driver / receiver unit performs a logical product of a logical product signal of a chip select signal and a read / write signal and an output signal from each integrated circuit. A circuit group, an OR circuit for ORing output signals of the AND circuit group, a gate is connected to the output terminal of the OR circuit, a drain is connected to the transmission line, and a source is connected to a ground terminal. An N-channel MOS transistor as a driver, an electrostatic protection capacitor connected between the transmission line and a ground terminal, one input end connected to the transmission line, and the other input end supplied with a reference voltage. A differential comparator group as a plurality of receivers connected to a power supply line, and a differential comparator group connected between each differential comparator of the differential comparator group and the input / output terminal of the integrated circuit. Puserekuto signal and a read /
And a buffer circuit group for controlling the output impedance of the differential comparator group by a write signal.

[0016]

According to the present invention, in order to reduce the capacity on the transmission line 3, the driver and the receiver of an arbitrary number (n) of VLSIs 100 are separated from each other so as to have a common structure, so that the capacity connected to the transmission line 3 is 1 / N, it is possible to drastically reduce the number, and it is possible to pursue a higher speed, and by connecting a plurality of common drivers and receivers on the transmission line 3, a system that can secure the number of VLSIs 100 that can be transmitted is provided. Can be built.

Further, the characteristic impedance on the transmission line 3 is not significantly lowered, and the matching property of the terminating resistor 2 is not impaired.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the input / output interface circuit device according to the present invention. In the figure,
1 is a power supply terminal to which a termination voltage is supplied, 2 is a termination resistor, 3
Is a transmission line, 4 is an N-channel MOS transistor whose drain is connected to the transmission line 3, and whose source is connected to the ground terminal. 6 is an OR circuit for outputting a drive signal to the N-channel MOS transistor 4. 5 is an electrostatic protection capacitor. , 8 has one input terminal connected to the electrostatic protection capacitor 5 and the transmission line 3,
The other input terminal is a differential comparator connected to an external circuit so that the reference voltage _Vref is supplied, and 100 receives CC, which is a control signal from the outside, for example, a controller, and connects the data transmitting / receiving logic circuit 90 to the logic circuit 90. VLSI, 200 for supplying input / output signals to the OR circuit 6 and the differential comparator 8 via N channel MOS transistor 4, electrostatic protection capacitor 5, OR
This is a driver / receiver unit composed of the circuit 6 and the differential comparator 8. Here, the control signal CC collectively indicates a plurality of types of control signals.

Next, the circuit operation will be described. The VLS selected when "L" is transmitted under the control of CC (eg, address signal, chip select signal CS, write / read signal W / R) which is a control signal from the outside
"H" is ORed from 100 data transmission / reception logic circuit 90
The signal is sent to the circuit 6, and the OR circuit 6 outputs "H" to the NMOS transistor 4 as a driver. At this time NM
The OS transistor 4 is turned on, pulling down the potential of the transmission line 3, and the potential of the transmission line is “L” = V _OL.
(0.4V). This "L" is received by the differential comparator 8 as a receiver, compared with the reference voltage V _ref, and the control signal C
“H” is sent to the data transmission / reception logic circuit 90 of the VLSI 100 selected in C.

When sending "H", the VLSI10
"L" is sent from the data transmission / reception logic circuit 90 of 0 to the OR circuit 6, and the OR circuit 6 outputs "L" to the NMOS transistor 4 as a driver. At this time NMOS
The transistor 4 is turned off, the potential of the transmission line 3 is pulled up to the level of the termination voltage, and the potential of the transmission line 3 becomes "H" = termination voltage (1.2V). The operation of receiving this "H" by the differential comparator 8 serving as a receiver, comparing it with the reference voltage V _ref, and sending "L" to the data transmission / reception logic circuit 90 of the VLSI 100 selected by the control signal CC. To do.

With the above configuration, the load capacity connected on the transmission line 3 is the capacity of one driver / receiver unit 200 and is the NMO which is the input / output capacity.
Only the junction capacitance of the S transistor 4 and the electrostatic protection capacitance for protecting the input terminal of the differential comparator 8 are used. This means that
VLSI 100 connected on conventional transmission line 3
The load capacity can be reduced to 1 / n, which corresponds to one of n pieces.

FIG. 2 shows a further embodied embodiment of the input / output interface circuit device according to the present invention. In the figure, the same reference numerals as those of the embodiment shown in FIG. 1 indicate parts having the same functions and operations. The circuit configuration is embodied from FIG. 1 in that a signal to the gate of the NMOS transistor 4 serving as a driver is transmitted from the VLSI 100 and a control signal from the outside (for example, a chip select signal CS, a write / read signal W / R) and the signal generated by the AND circuit 71 to generate the AND circuit 61, and OR
The output of the differential comparator 8 is controlled by a signal generated by the AND circuit 72 by the chip select signal CS and the write / read signal W / R. That is, it is configured to be output as a reception signal to the VLSI 100 via. As a result, the output of the differential comparator 8 serving as a receiver has a high impedance when not selected by an external control signal, and the NMOS transistor 4 serving as a driver is "L".
The OR circuit 6 that is fixed and in the OFF state and that is the input circuit of the NMOS transistor 4 that is the driver, the output of the differential comparator 8 that is the receiver, and the input / output terminals of the VLSI 100 have good connectivity.

FIG. 3 shows the configuration of another embodiment of the input / output interface circuit device according to the present invention. The same reference numerals as those of the embodiment shown in FIG. 1 indicate components having the same functions and operations.
The circuit configuration is different from that of the embodiment of FIG. 1 in that the circuit configuration is such that the input / output terminals of the VLSI 100 are separated into input terminals and output terminals. This will send or receive V
The LSI 100 can be applied to both a common input / output terminal and a configuration in which the input terminal and the output terminal are separated, and the transmission line 3
It is possible to secure high-speed transmission by reducing the connection capacity of the VLSI 100 for transmission and reception, which is the above load capacity.

FIG. 4 shows the configuration of another embodiment of the input / output interface circuit device according to the present invention. The same reference numerals as those of the embodiment shown in FIG. 3 indicate components having the same functions and operations.
The circuit configuration is different from that of the embodiment shown in FIG.
VL transmitted and received by the number of differential comparators 8 of the receiver unit 202
The point is that the number of SI 100s was unified to one. As a result, the number of VLSI 100 is relatively small,
In a system configuration in which the load on the receiver output is small, the number of differential comparators 8 serving as receivers can be set to one, and the circuit configuration can be simplified. The capacity can be reduced to ensure high-speed transmission.

FIG. 5 shows an example of the electrostatic protection capacitor 5.
In order to protect the differential comparator 8 composed of a CMOS circuit, which is the input end of the receiver, from electrostatic damage by the input signal from the transmission line 3, the gate and source of the P-channel MOS transistor 51 are connected to the power supply terminal VDD and the drain is connected to It is configured to be connected to the output of the transmission line 3 and the resistor 52.

Another embodiment of the present invention is shown in FIG. The same reference numerals as those of the embodiment shown in FIG. 3 indicate components having the same functions and operations. FIG. 7 shows an application example of the embodiment shown in FIGS. 1 and 2 (the embodiment shown in FIGS. 3 and 4 is also possible).
This is an example of constructing a system in which a plurality of receiver units 200 are provided to increase the number of VLSIs 100 that transmit and receive via the transmission line 3.

FIG. 8 shows an application example of the present invention. FIG. 8 shows a part of the general configuration of the computer, and the processor 40
The memory unit 100 that stores data input from 0 or output to the processor 400 is connected to the data bus as the transmission line 3 via the driver / receiver unit 200 via the memory controller 300 controlling the memory unit. In this system, for example, the processor 4
00 operates at high speed, high speed is required in the transmission line 3 for transmitting / receiving data to / from the memory section 100. Therefore, in order to realize high speed in the transmission line 3, it is necessary to reduce the load level on the transmission line 3 and speed up charging / discharging in addition to reducing the signal level. Moreover, this must be a system in which the number of memory units 100 is secured.

Therefore, a high-performance transmission system can be constructed by applying the circuit configuration of the present invention, which has already been described with reference to FIGS. 1, 2, 3, 4, and 7.

[0029]

According to the present invention, it is possible to realize an input / output interface circuit device of a small amplitude operation suitable for speeding up, and to construct a system for further speeding up.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of an input / output interface circuit device according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of another embodiment of the input / output interface circuit device according to the present invention.

FIG. 3 is a circuit diagram showing a configuration of another embodiment of the input / output interface circuit device according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of another embodiment of the input / output interface circuit device according to the present invention.

5 is a circuit diagram showing a configuration of an electrostatic protection capacitor in FIG.

FIG. 6 is a circuit diagram showing a configuration of a conventional input / output interface circuit device.

FIG. 7 is a circuit diagram showing an application example of the input / output interface circuit device according to the present invention.

FIG. 8 is a block diagram showing a configuration of a data processing device to which the present invention is applied.

[Explanation of symbols]

 1 Power Terminal 2 Termination Resistor 3 Transmission Line 4 N Channel MOS Transistor 5 Electrostatic Protection Capacitance 6 OR Circuit 8 Differential Comparator 90 Data Transmission / Reception Logic Circuit 100 VLSI 200 Driver / Receiver Section

Claims (5)

[Claims] 1. A transmission line is connected at both ends to terminals to which a termination voltage is supplied via a terminating resistor, and includes a driver / receiver section and a data transmission / reception logic circuit for transmitting / receiving data. In an input / output interface circuit device in which a plurality of integrated circuits for exchanging data via a transmission line are connected to the transmission line, a driver / receiver unit of the plurality of integrated circuits is made independent from the plurality of integrated circuits and is common. An input / output interface circuit device characterized by being realized. 2. The driver / receiver section includes a logical sum circuit for logically summing output signals from a plurality of integrated circuits configured to include a data transmission / reception logic circuit for transmitting / receiving data, and a gate for the logical logic circuit. An N-channel MOS transistor as a driver, the drain of which is connected to the transmission line and the source of which is connected to the ground terminal, an electrostatic protection capacitor connected between the transmission line and the ground terminal, A differential comparator as one or more receivers whose input end is connected to the transmission line and the other input end is connected to a power supply line to which a reference voltage is supplied. The input / output interface circuit device according to claim 1. 3. A configuration in which an input terminal for receiving a signal from the differential comparator of a data transmission / reception logic circuit in each of the plurality of integrated circuits and an output terminal for outputting a signal to the OR circuit are separately provided. The method according to claim 2, wherein
The input / output interface circuit device according to. 4. The input / output interface circuit device according to claim 3, wherein one differential comparator as a receiver is integrated and made common. 5. The logical product circuit group, wherein the driver / receiver unit takes a logical product of a logical product signal of a chip select signal and a read / write signal and an output signal from each integrated circuit, and a logical product circuit group. A logical sum circuit for taking the logical sum of the output signals of the product circuit group, and an N-channel MOS as a driver whose gate is connected to the output terminal of the logical sum circuit, drain to the transmission line and source to the ground terminal. A transistor, an electrostatic protection capacitor connected between the transmission line and a ground terminal, one input end connected to the transmission line, and the other input end connected to a power supply line to which a reference voltage is supplied. A group of differential comparators as a plurality of receivers, and a chip select signal and a read / write signal connected between each differential comparator of the differential comparator group and the input / output terminal of the integrated circuit. And a buffer circuit group for controlling the output impedance of the differential comparator group by means of a signal. 2. The input / output interface circuit device according to claim 1, wherein an input signal to the logical sum circuit is generated from a signal from VLSI and an output from the receiver is controlled by high impedance.