JPH0749802A - Fault processing device - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a failure processing device capable of quickly and flexibly responding to increase / decrease or change of failure information and failure processing corresponding to the failure information and easily executing change processing. [Configuration] Fault detection circuit 21 of each module 11 to 1n
The fault information detected in 2n to 2n is multiplexed by the data multiplexing circuit 1, stored in the fault information holding memory 2 in a predetermined order, and then read out based on the address information stored in the control information holding memory 4. , The condition circuit 5 handles each fault 31
It is determined whether or not ~ 3k is necessary, and failure processing 3 is performed based on the result.
Implementation of 1 to 3k is instructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing device,
In particular, the present invention relates to a failure processing device that instructs appropriate failure processing according to various failures that have occurred.

[0002]

2. Description of the Related Art Conventionally, in a failure processing device that instructs appropriate failure processing in accordance with various detected failures, the failure processing judgment is made as a failure processing judgment and a predetermined execution is carried out in correspondence therewith. It was realized by using a logic circuit designed to satisfy the logical conditions based on the relationship with the power failure processing, or by designing a program that satisfies these logical conditions and executing it by a processor. .

[0003]

Therefore, in such a conventional fault processing apparatus, the number of fault information to be detected and the number of fault processes corresponding to the occurrence of a fault are increased, and the correspondence relationship between the fault information and the fault process is further improved. When it becomes complicated, a complicated logic circuit or program is required to realize an appropriate fault handling decision, and when the number of fault information or fault handling corresponding to this or the correspondence between them changes, it becomes complicated. It requires a great deal of time and labor to appropriately change the appropriate logic circuit or program, and it has been difficult to respond promptly.

The present invention is intended to solve such a problem, and can quickly and flexibly deal with increase / decrease and change of failure information and failure processing corresponding thereto, and change processing can be easily performed. It is an object of the present invention to provide a fault processing device that can be used.

[0005]

In order to achieve such an object, a fault processing apparatus according to the present invention has a fault information holding memory for temporarily holding fault information and a desired order from the fault information holding memory. The control information holding memory that holds the address information to be read by and the failure information output from the plurality of failure detection circuits are periodically written to a predetermined position of the failure information holding memory, and the address information in the control information holding memory is also written. Memory control means for periodically reading out the failure information from the failure information holding memory based on the failure information, and whether or not various failure processings are necessary based on the failure information read by the memory control means, and failure processing is performed according to the determination result. And condition determining means for instructing the execution of.

[0006]

Therefore, the failure information detected by the failure detection circuit is
After being stored in a predetermined position of the failure information holding memory by the memory control means, it is read based on the address information stored in the control information holding memory, and each failure is read by the condition determination means based on the read failure information. Whether or not processing is necessary is determined, and execution of failure processing is instructed based on the result.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a fault processing apparatus which is an embodiment of the present invention. In the figure, reference numerals 11 to 1n respectively have failure detection circuits 21 to 2n.
A module that outputs the failure information detected in 1 to 2n,
Reference numeral 1 is a data multiplexing circuit that multiplexes fault information from each of the modules 11 to 1n.

Reference numeral 2 is a fault information holding memory for storing the fault information multiplexed by the data multiplexing circuit 1, particularly, it is capable of continuously performing writing and reading at high speed, and 3 is control information holding. The memory control circuit 5 for controlling the reading of the failure information stored in the failure information holding memory 2 based on the contents of the memory 4 includes the failure information read from the failure information holding memory 2 under the control of the memory control circuit 3. It is a conditional circuit for selecting and instructing the failure processing 31 to 3k based on the above.

FIG. 2 is a block diagram of the condition circuit 5.
In the figure, 51 to 5j are flip-flops that latch the failure information read from the failure information holding memory 2, 6 is a NOT gate, 7 is an AND gate, and 8 is an AND.
A flip-flop that latches the output of the gate 7 and a separation circuit 9 that separates the output of the flip-flop 8 as an output to the fault processing 31 to 3k at a predetermined timing.

Next, the operation of the present invention will be described with reference to FIGS. FIG. 3 is an explanatory diagram showing the flow of failure information in each part of FIG. 1, and in the figure, 111 to 11 m are
Fault information output from the fault detection circuits 21 to 2n, 12
0 is the failure information stored in the failure information holding memory 2, 150 is the failure information read from the failure information holding memory 2, 131 to 13k are for failure occurrence determination processing related to the failure processing 31 to 3k. The respective logical conditions are shown.

Now, the failure detection times in the modules 11 to 1n
Faults detected on the paths 21 to 2n are designated as fault information 111.
Are periodically read by the data multiplexing circuit 1. This place
If A ₁₁Is the one detected in module 11
The failure data showing the event is shown, and modules 11 to 11 are shown.
Fault data A from 1n in parallel at the same timing₁₁~
A_1nThat is, the fault information 111 is read and the next timing
Similarly, from module 11 to 1n
The report 112 is read and this is repeated m times.

Therefore, the fault data A ₁₁ -A _m1 indicating different events from the module 11 are sequentially output at each timing and read into the data multiplexing circuit 1 as a part of the fault information 111-11 m. Become. Further, after the fault data A _m1 is read from the module 11, the fault data indicating each event in the next cycle is repeatedly read in sequence from A _{11 in the same} manner as described above.

In the data multiplexing circuit 1, the fault information 111 read in parallel from each of the modules 11 to 1n at the same timing is multiplexed into serial data having a predetermined speed and output, and the fault information 11 subsequently read out.
2 to 11 m are continuously multiplexed and the fault information holding memory 2
Output to.

The failure information holding memory 2 is a memory having a two-sided structure (double buffer structure) as a memory storage area, has two memory buffers separated inside, and stores it in an arbitrary address of one of the memory buffers. At the same time as writing data, it is possible to read the data from any address of the other memory buffer,
It is possible to arbitrarily switch between writing and reading between the two memory buffers.

The memory control circuit 3 has a counter that counts in synchronization with the multiplexed fault information output from the data multiplexing circuit 1, and the counter output is supplied to the fault information holding memory 2 as a write address. To be done.
Thereby, the fault information from the data multiplexing circuit 1 is divided into individual fault data, and is fixedly set to each fault data in the fault information holding memory 2 based on the write address output from the memory control circuit 3. Sequentially stored in the designated positions.

The memory control circuit 3 outputs a memory buffer switching instruction in accordance with the storage capacity of one memory buffer of the fault information holding memory 2. As a result, the failure information from the data multiplexing circuit 1 is written into the other memory buffer at the same time when one memory buffer of the failure holding memory 2 is full, that is, all of the memory buffers are used up and there is no free area.

Further, the memory control circuit 3 supplies the internal counter output as a read address for the control information holding memory 4, and the information read from the control information holding memory 4 based on the counter output, that is, the address information, is used as the fault information. It is supplied to the failure information holding memory 2 as a read address of the failure information stored in the holding memory 2.

At this time, the memory control circuit 3 outputs the internal counter output to the failure information holding memory 2, and at the same time, outputs the information read from the control information holding memory 4 based on the counter output to the failure information holding memory 2. To do.

As a result, the fault information holding memory 2 writes the fault information from the data multiplexing circuit 1 into one of the memory buffers using the counter output from the memory control circuit 3 as a write address, and at the same time, writes the fault information from the memory control circuit 3. The fault information is read from the other memory buffer using the information read from the control information holding memory 4 based on the counter output as a read address.

Therefore, by storing the read addresses in advance in the order of reading at the same address of the control information holding memory 4 as the counter output sequentially output from the memory control circuit 3, a desired order different from the order of writing is obtained. Then, the failure information can be read.

As a result, the fault information 120 read from each of the modules 11 to 1n and sequentially written in the fault information holding memory 2 is only the fault information 120 required for the necessity judgment corresponding to each fault process 31 to 3k. Are read out in a predetermined order necessary for the necessity determination described later and are output to the condition circuit 5 as fault information 150.

Fault information 150 input to the condition circuit 5
Is input to the flip-flop 51 and sequentially shifted, inverted and shifted after the NOT gate 6, and latched by the flip-flops 51 to 5k as fault information for determining necessity of each fault processing 31 to 3k. .

Here, since the negative logic of each event detected by the modules 11 to 1n may be required as the logical condition for determining the necessity of the failure processing, there is no need for such negative logic. Those which are input first and are latched by the flip-flops 5i, 5j, etc. in the subsequent stage of the NOT gate 6, and those which may remain in positive logic are input later and are input by the NOT gate 6
Latched by the flip-flops 51, 52, etc. in the previous stage of
The AND gate 7 outputs the logical product of these.

Therefore, the control information holding memory 4 has a flip-flop in which the failure information is arranged in the order in which it is determined whether or not each failure process is necessary, and each failure information is determined according to the positive / negative logic at the time of each event and the necessity / unnecessity judgment. Address information of each fault data in the fault information holding memory 2 is stored in the address indicated by the counter output sequentially output from the memory control circuit 3 so as to be latched by 51 to 5j.

When the number of flip-flops required in the positive / negative logic of each necessity judgment varies,
The failure information holding memory 2 is provided so that failure data of the same logic is redundantly latched in unnecessary flip-flops.
Read from.

The flip-flop 8 latches the output of the AND gate 7 which is the logical product of all the flip-flops 51 to 5j when the fault information is shifted to the flip-flops 51 to 5j and normally latched, and the separation circuit 9 is
The latch output of the flip-flop 8 is output as an instruction output of the fault processing 31 to 3k corresponding to the executed necessity determination.

From the above, the fault information detected by each of the modules 11 to 1n is stored in the fault information holding memory 2 in a predetermined order.
After being written in the control circuit 5, the failure processing 3 in the conditional circuit 5 is performed according to the information stored in the control information holding memory 4 in advance.
It is read in the order necessary for the necessity determination of 1 to 3k, and the necessity of the failure processing 31 to 3k is instructed based on the determination result.

[0028]

As described above, according to the present invention, the control information holding memory for holding the information defining the reading order of the failure information is provided, and the failure information sequentially written in the failure information holding memory is stored in the control information holding memory. The data is read out in order based on the information in the memory.

Therefore, in the failure processing device that instructs appropriate failure processing based on various failure information, it is possible to quickly and flexibly deal with increase / decrease and change of failure information and failure processing corresponding to the failure information and change processing. It has a special effect that it can be easily implemented.

[Brief description of drawings]

FIG. 1 is a block diagram of a failure processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conditional circuit in the fault processing apparatus of FIG.

FIG. 3 is an explanatory diagram showing a flow of failure information in each part of FIG.

[Explanation of symbols]

 1 Data Multiplexing Circuit 2 Fault Information Retaining Memory 3 Memory Control Circuit 4 Control Information Retaining Memory 5 Conditional Circuit 6 NOT Gate 7 AND Gate 8 Flip Flop 9 Separation Circuit 11-1n Module 21-2n Fault Detection Circuit 31-3k Fault Processing 51- 5j flip-flop

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[Procedure amendment]

[Submission date] May 31, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

[0005]

In order to achieve such an object, a fault processing apparatus according to the present invention has a fault information holding memory for temporarily holding fault information and a desired order from the fault information holding memory. The control information holding memory that holds the address information to be read by and the failure information output from the plurality of failure detection circuits are periodically written to a predetermined position of the failure information holding memory, and the address information in the control information holding memory is also written. Memory control means for periodically reading out the failure information from the failure information holding memory based on the failure information, and whether or not various failure processings are necessary based on the failure information read by the memory control means, and failure processing is performed according to the determination result. And condition determining means for instructing the execution of. In addition, the failure information storage memory is internally separated.
It has two memory buffers, one of which is
At the same time as writing the fault information, from the control information holding memory
The read information is used as the read address for the other memo.
The failure information is read from the rebuffer.

Claims (1)

[Claims] 1. A failure processing device for instructing appropriate failure processing based on failure information from a plurality of failure detection circuits for detecting a failure of a monitored device, comprising a failure information holding memory for temporarily holding the failure information. A control information holding memory for holding address information to be read out in a desired order from the failure information holding memory; and failure information output from the plurality of failure detection circuits, periodically at a predetermined position of the failure information holding memory. A memory control unit that periodically writes the fault information from the fault information holding memory based on the address information in the control information holding memory, and various fault processings based on the fault information read by the memory control unit. And a condition determining means for determining whether or not it is necessary and for instructing execution of failure processing according to the determination result. That failure processing apparatus.