JPH0749810Y2 - Monolithic microwave integrated circuit - Google Patents
Monolithic microwave integrated circuitInfo
- Publication number
- JPH0749810Y2 JPH0749810Y2 JP1989030635U JP3063589U JPH0749810Y2 JP H0749810 Y2 JPH0749810 Y2 JP H0749810Y2 JP 1989030635 U JP1989030635 U JP 1989030635U JP 3063589 U JP3063589 U JP 3063589U JP H0749810 Y2 JPH0749810 Y2 JP H0749810Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- integrated circuit
- microwave integrated
- monolithic microwave
- strip line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
- Waveguides (AREA)
Description
【考案の詳細な説明】 （イ）産業上の利用分野 本考案は、小型化と安定したインピーダンスを両立でき
るモノリシックマイクロ波集積回路（以下、MMICと称
す）に関する。[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a monolithic microwave integrated circuit (hereinafter referred to as MMIC) capable of achieving both miniaturization and stable impedance.
（ロ）従来の技術 GaAs基板上にフィルタ等のマイクロ波集積回路をストリ
ップ線路を用いて構成する場合、例えば特開昭63−5910
3号公報に記載されているように、第２図に示される方
法が用いられていた。(B) Prior art When a microwave integrated circuit such as a filter is formed on a GaAs substrate using a strip line, for example, Japanese Patent Laid-Open No. 63-5910.
The method shown in FIG. 2 was used as described in Japanese Patent Publication No.
第２図において（１）はGaAs基板、（２）は基板（１）
の一主面に設けたストリップ線路導体、（３）は基板
（１）の反対面に設けた接地導体、（４）は基板（１）
を貫通するスルーホールで、該スルーホール（４）を介
してストリップ線路導体（２）と接地導体（３）との電
気的接続が成される。In FIG. 2, (1) is a GaAs substrate and (2) is a substrate (1).
Strip line conductor provided on one main surface, (3) a ground conductor provided on the opposite surface of the substrate (1), and (4) a substrate (1)
Through the through hole (4), the strip line conductor (2) and the ground conductor (3) are electrically connected to each other.
上記ストリップ線路のインピーダンスを整合させる為、
その製造工程においてGaAs基板（１）の反対面をエッチ
ング又はポリッシュにより削る工程が含まれる。この工
程により、GaAs基板（１）の厚みを50〜80μｍまで薄く
し、基板（１）の厚みとストリップ線路導体（２）の線
幅をwheelerの式で求められた比にすることにより、ス
トリップ線路をインピーダンス整合する。To match the impedance of the strip line,
The manufacturing process includes a step of etching the opposite surface of the GaAs substrate (1) by etching or polishing. By this process, the thickness of the GaAs substrate (1) is reduced to 50 to 80 μm, and the thickness of the substrate (1) and the line width of the strip line conductor (2) are set to the ratio obtained by the wheeler's formula, thereby stripping Match the impedance of the line.
（ハ）考案が解決しようとする課題 しかしながら、GaAs基板（１）を誘電体基板として用い
る為には表面のストリップ線路導体（２）と裏面の接地
導体を電気接続する必要があり、その為のスルーホール
（４）の加工が困難である欠点があった。(C) Problems to be solved by the invention However, in order to use the GaAs substrate (1) as a dielectric substrate, it is necessary to electrically connect the strip line conductor (2) on the front surface to the ground conductor on the back surface. There was a drawback that the processing of the through hole (4) was difficult.
また、GaAs基板（１）を機械的に削る為基板自体の強度
が弱くなり、取扱いに不具合であることや、厚みにばら
つきを生じ易い為特性インピーダンスもばらつく欠点が
あった。Further, since the GaAs substrate (1) is mechanically ground, the strength of the substrate itself becomes weak, which is a problem in handling, and the characteristic impedance tends to vary because the thickness tends to vary.
（ニ）課題を解決するための手段 本考案は上記従来の欠点に鑑み成されたもので、ストリ
ップ線路導体（12）を覆う様に誘電体層（13）を設け、
この誘電体層（13）の表面に接地導体（14）を設けるこ
とにより、特性インピーダンスのばらつきを抑え且つ素
子の微細化をも実現したモノリシックマイクロ波集積回
路を提供するものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional drawbacks, and a dielectric layer (13) is provided so as to cover the strip line conductor (12),
A grounding conductor (14) is provided on the surface of the dielectric layer (13) to provide a monolithic microwave integrated circuit in which variations in characteristic impedance are suppressed and element miniaturization is realized.
（ホ）作用 本考案によれば、GaAs基板（11）をそのままの厚みで使
用できるので、機械的強度を保たせることができる。ま
た、誘電体層（13）が数μ〜十数μｍの範囲内で構成で
きるので、接地導体（14）との電気接続が容易である
他、ストリップ線路導体（12）の線幅を縮小できる。(E) Function According to the present invention, since the GaAs substrate (11) can be used with the same thickness, the mechanical strength can be maintained. Moreover, since the dielectric layer (13) can be formed within a range of several μm to several tens of μm, the electrical connection with the ground conductor (14) is easy and the line width of the strip line conductor (12) can be reduced. .
（ヘ）実施例 以下に本考案の一実施例を図面を参照しながら詳細に説
明する。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.
第１図は本考案のMMICを示す断面図で、（11）は表面に
MES−FET、キャパシタ、インダクタンス等の素子が形成
された厚さ300〜600μｍのGaAs基板、（12）はAl,Ti,P
t,Au等から成る多層合金層のパターニングにより構成さ
れGaAs基板（11）上を延在して各素子を電気接続するス
トリップ線路導体、（13）はストリップ線路導体（12）
とGaAs基板（11）表面を覆う誘電体層、（14）は誘電体
層（13）の全面を覆う様に形成した接地導体で、接地導
体（14）は誘電体層（13）のコンタクトホール（15）を
介して下層のストリップ線路導体（12）と電気接続され
る。（16）は基板（11）裏面の接地導体である。Fig. 1 is a sectional view showing the MMIC of the present invention. (11) is on the surface
300-600 μm thick GaAs substrate on which elements such as MES-FET, capacitor and inductance are formed. (12) is Al, Ti, P
Strip line conductors formed by patterning a multi-layered alloy layer made of t, Au, etc. and extending on a GaAs substrate (11) to electrically connect respective elements, (13) is a strip line conductor (12)
And a dielectric layer covering the surface of the GaAs substrate (11), (14) is a ground conductor formed so as to cover the entire surface of the dielectric layer (13), and the ground conductor (14) is a contact hole of the dielectric layer (13). It is electrically connected to the strip line conductor (12) in the lower layer via (15). (16) is a ground conductor on the back surface of the substrate (11).
誘電体層（13）はポリイミド系樹脂をスピンオン塗布す
ることにより得られ、厚みは樹脂の塗布量と回転数、及
び回転時間等のファクターにより制御される。The dielectric layer (13) is obtained by spin-on coating a polyimide resin, and the thickness is controlled by factors such as the coating amount of resin, the number of rotations, and the rotation time.
ウェラー（wheeler）の式に従えば、整合インピーダン
スZ0を最も伝送損失の少い50Ωとする為には、ポリイミ
ド系樹脂の誘電率がεr4であるので、ストリップ線路導
体の線幅Ｗと誘電体層（13）の厚みｈはW/h２となる
ので、誘電体層（13）の厚みをｈ６μｍとした時スト
リップ線路導体（12）の線幅はＷ＝12μｍとなり、従来
がＷ＝100μｍ前後を必要としていたのに対し大幅な微
細化が可能となる。According to the Weller's formula, in order to set the matching impedance Z 0 to 50Ω, which has the least transmission loss, the dielectric constant of the polyimide resin is εr4, so the line width W of the strip line conductor and the dielectric Since the thickness h of the layer (13) is W / h2, the line width of the strip line conductor (12) is W = 12 μm when the thickness of the dielectric layer (13) is h6 μm, and the conventional width is about W = 100 μm. Although it was necessary, it is possible to make it much smaller.
また、ポリイミド系樹脂のスピンオン塗布により誘電体
層（13）を形成するので、その厚みを正確に制御するこ
とが容易であり、従って整合インピーダンスZ0のばらつ
きが少い。Further, since the dielectric layer (13) is formed by spin-on application of a polyimide resin, it is easy to control the thickness accurately, and therefore the matching impedance Z 0 has little variation.
さらに、GaAs基板（11）の裏面にも接地導体（14）を設
けることにより、スリトップ線路導体（12）を両側から
挟むので、より安定した分布定数線路を構成できる。Further, by providing the ground conductor (14) also on the back surface of the GaAs substrate (11), the slit top line conductor (12) is sandwiched from both sides, so that a more stable distributed constant line can be constructed.
（ト）考案の効果 以上に説明した通り、本考案によればGaAs基板（11）上
に設けた誘電体層（13）を用いてストリップラインを構
成し、GaAs基板（11）を厚い状態のまま組立てるので、
基板（11）の割れ、破損が少く、取扱い性に優れた、機
械的強度が強いMMICを提供できる利点を有する。(G) Effect of the Invention As described above, according to the present invention, the strip line is formed by using the dielectric layer (13) provided on the GaAs substrate (11) and the GaAs substrate (11) has a thick state. As it is assembled as it is,
The substrate (11) has few cracks and damages, has an advantage of being easy to handle, and can provide an MMIC with high mechanical strength.
また、スピンオン塗布法で誘電体層（13）を構成するの
で、機械的加工をしたよりも正確な厚みと平坦面を作る
ことができ、従ってばらつきの無い整合インピーダンス
が得られる利点を有する。In addition, since the dielectric layer (13) is formed by the spin-on coating method, it has an advantage that a more accurate thickness and a flat surface can be formed than by mechanical processing, and thus a matching impedance without variations can be obtained.
第１図は本考案を説明する為の断面図、第２図は従来例
を説明する為の断面図である。FIG. 1 is a sectional view for explaining the present invention, and FIG. 2 is a sectional view for explaining a conventional example.
Claims (1)
ストリップ導体と、前記ストリップ導体の上を被覆する
ポリイミド樹脂から成る誘電体膜と、前記ポリイミド樹
脂のスピンオン塗布により形成した平坦面の上に前記ス
トリップ導体を覆うように形成した、前記ストリップ導
体との相対位置によりインピーダンスを決定する接地導
体とを具備することを特徴とするモノリシックマイクロ
波集積回路。1. A strip conductor formed on one main surface of a semi-insulating semiconductor substrate, a dielectric film made of a polyimide resin covering the strip conductor, and a flat surface formed by spin-on coating of the polyimide resin. A monolithic microwave integrated circuit, the ground conductor having an impedance determined by a relative position with respect to the strip conductor, the ground conductor being formed on the ground conductor so as to cover the strip conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989030635U JPH0749810Y2 (en) | 1989-03-16 | 1989-03-16 | Monolithic microwave integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989030635U JPH0749810Y2 (en) | 1989-03-16 | 1989-03-16 | Monolithic microwave integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02120839U JPH02120839U (en) | 1990-09-28 |
| JPH0749810Y2 true JPH0749810Y2 (en) | 1995-11-13 |
Family
ID=31255869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989030635U Expired - Lifetime JPH0749810Y2 (en) | 1989-03-16 | 1989-03-16 | Monolithic microwave integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0749810Y2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6053089A (en) * | 1983-09-02 | 1985-03-26 | Nec Corp | semiconductor equipment |
| JPS62294303A (en) * | 1986-06-13 | 1987-12-21 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
| JPH0622233B2 (en) * | 1987-08-31 | 1994-03-23 | 日本電気株式会社 | Multilayer wiring formation method |
-
1989
- 1989-03-16 JP JP1989030635U patent/JPH0749810Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02120839U (en) | 1990-09-28 |
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