JPH0758910B2 - Parallel A / D converter - Google Patents

Description

TECHNICAL FIELD The present invention relates to a parallel type for converting an analog signal into a digital signal.
It relates to an A / D converter.

2. Description of the Related Art As shown in FIG. 3, a conventional parallel type A / D converter inputs an input signal 1 commonly to one input terminal of comparator rows 4A and 4B, and a reference voltage 2 to a resistor row 3A and a resistor row 3A. Divided by 3B to generate each comparison voltage, which is input to the other input terminals of the comparator rows 4A and 4B, respectively. The comparison outputs from the comparator rows 4A and 4B are input to the logic circuit rows 5A and 5B, and in a normal operating state, one of the logic outputs becomes active and is input to the encoder circuit 6. The encoder circuit 6 is matrixed so as to generate a corresponding code for a specific input, and the code-converted output is output to the buffer circuit array 7
Is transferred to the next stage via. The comparators 4A and 4B are often strobe type, and the signal state of the timing determined by the clock pulse 8 becomes the converted output. 9A and 9B are clock pulse buffers.

Normally, such a parallel type A / D converter is formed by an integrated circuit because of its large circuit scale. In this case, however, the encoder circuit 6 is shared as shown in FIG. Arranged are comparator rows 4A and 4B and logic circuit rows 5A and 5B.
In addition, the clock pulse buffer is 4
It is arranged like 9A, 9B with respect to A, 4B.

However, when a binary code is used as the encoding format, the logic output of the right logic circuit array 5A is not connected to all the most significant bits of the encoder circuit, and conversely the logic output of the left logic circuit array 5B is the highest. The connection to the upper bits does not increase the number of bit lines of the encoder circuit 6 and has better compatibility with the next stage.

Problems to be Solved by the Invention In such a circuit, there is no problem in a normal state in which only one logic output is active in the logic circuit array 5A, 5B and the rest are all inactive. However, as the frequencies of the input signal 1 and the clock pulse 8 become higher, the timing error is more likely to occur, and the state in which the outputs of two or more logic circuits become active occurs. This becomes particularly noticeable at the boundary between the right column and the left column. This is caused by the timing difference between the clock pulse buffers 9A and 9B, the deviation of the circuit type parameters due to the distance between the right column and the left column, and the arrangement of the comparator columns 4A and 4B. Since the upper directions are opposite, it is considered that the deviation of the circuit parameter is increased especially when the mask alignment is deviated.

Thus, when two or more logic outputs are activated at the boundary between the right column and the left column, a large exchange error occurs. FIG. 4 shows the A / D conversion output with respect to the input voltage. The conversion output monotonically increases with respect to the input except the boundary part, but at the boundary part, the conversion output [16] and the logic main force of the logic circuit array 5A corresponding to the decimal conversion output [14] Since the logical output of the corresponding logical circuit array 5B becomes active, this is combined in the encoder circuit 6 to generate the value of the converted output [30], and the converted output [15] and [17] have the value of [31]. Occurs. For this reason, there is a drawback that a very large conversion error occurs and monotonicity is lacking, which is a big problem.

The present invention solves such a problem, and an object of the present invention is to provide a parallel type A / D converter in which the conversion difference is kept small and the monotonicity is maintained with a simple configuration.

Means for Solving the Problems In order to solve the above problems, the present invention logically processes the output of the comparator array for comparing an input signal and a reference voltage and the output of the adjacent comparator to obtain only a necessary logical output. And a logic circuit array for activating the circuit, a part of the column of the circuit system as a first circuit system, and a remaining part of the column as a second circuit system, and the first and second circuit systems. An encoder circuit for converting parallel outputs of the logic circuits as inputs into a digital code, and a transfer prohibiting means for prohibiting transfer of a specific bit of all bits of the encoder circuit to the next stage. The plurality of logic circuits of the circuit system are not connected to the specific bit of the encoder circuit, the plurality of logic circuits of the second circuit system are connected to the specific bit of the encoder circuit, and the transfer prohibiting unit is Logic output of the first circuit system When any one of the forces is active, a configuration is adopted in which transfer of a specific bit of the encoder circuit to the next stage is prohibited.

With the above-described structure, the present invention makes the most significant bit of the second circuit system active if the most significant bit of the encoder is taken as the specific bit and the logic output of the first circuit system becomes active. Can be prevented and the conversion error can be reduced.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a circuit configuration diagram showing an embodiment of a parallel type A / D converter of the present invention, in which the same reference numerals as those in FIG. In FIG. 1, 10 is a logical sum circuit for detecting which one of the logical outputs of the right side logical circuit array 5A is active, and 11 is a logical sum of transfer of the most significant bit of the encoder circuit 6 to the next stage. It is a logic circuit controlled by the logic state of the circuit 10. Here, the first circuit system refers to the circuit column on the right column consisting of the comparator column 4A and the logic circuit column 5A, and the second circuit system refers to the left column consisting of the comparator column 4B and the logic circuit column 5B. The circuit system is shown. In addition, the specific bit of the encoder circuit 6 indicates the most significant bit on the left side. This bit line is connected to the left column but not to the right column. It is clearly divided, and the most significant bit line and the output line of the logical sum circuit 10 are input to the logical circuit 11.

In such a circuit, when the logic output of the logic circuit array 5A corresponding to the conversion output [14] and the logic output of the logic circuit array 5B corresponding to the conversion output [16] are simultaneously activated in decimal, Even if the sum circuit 10 becomes active and the most significant bit of the encoder circuit 6 becomes active, the output of the logic circuit 11 becomes inactive, and the output of [14] is transferred to the next stage. Further, even when the outputs of [15] and [17] occur at the same time, the output of [15] is transferred. further,
When only the 5B logic output of the logic circuit row corresponding to [18] becomes active, the logic output of the OR circuit 10 becomes inactive, so the logic output of the logic circuit 11 is the highest order of the encoder circuit 6. The logical state of the bit appears as it is and becomes active,
The output of [18] will be transferred to the next stage. Therefore, as shown in FIG. 2, the conversion characteristic has a conversion error with respect to the input voltage at the boundary between the right column and the left column as shown by the solid line, but is large as in the conventional example. However, monotonicity is maintained.

As described above, according to the present invention, with a simple circuit configuration, it is possible to prevent a large conversion error of the parallel type A / D converter and maintain monotonicity, and it is extremely useful in practice. It is useful.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a parallel type A / D converter in one embodiment of the present invention, FIG. 2 is a characteristic diagram for explaining the conversion characteristic, and FIG. 3 is a conventional parallel type A / D converter. FIG. 4 is a circuit diagram of the converter, and FIG. 4 is a characteristic diagram for explaining the conversion characteristic. 1 ... Input signal, 2 ... Reference voltage, 4A, 4B ... Comparator row, 5A, 5B ... Logic circuit row, 6 ... Encoder circuit, 10
... OR circuit, 11 ... Logic circuit

Claims (3)

[Claims] 1. A circuit system comprising a comparator array for comparing an input signal with a reference voltage, and a logic circuit array for logically processing the outputs of the adjacent comparators and activating only the necessary logic output. A part of the column of the circuit system is a first circuit system and the remaining part of the column is a second circuit system, and the parallel outputs of the logic circuits of the first and second circuit systems are input and converted into a digital code. An encoder circuit and a transfer prohibiting unit that prohibits transfer of a specific bit of all bits of the encoder circuit to the next stage are provided, and the plurality of logic circuits of the first circuit system are specific bits of the encoder circuit. Not connected to the plurality of logic circuits of the second circuit system are connected to a specific bit of the encoder circuit, and the transfer prohibiting unit is configured to operate when any one of the logic outputs of the first circuit system is active. Identification of the encoder circuit Parallel A / D converter and inhibits the transfer to the next stage of Tsu and. 2. The parallel type A / D converter according to claim 1, wherein the first and second circuit systems are arranged at one end and the other end of the encoder circuit, respectively. 3. The parallel type A / D converter according to claim 1, wherein the specific bit is a most significant bit of the encoder circuit.