JPH0760425B2 - Distributed control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a control means for a plurality of hierarchical processors.

In particular, it is suitable for use in a distributed control type storage processor electronic exchange.

〔Overview〕

The present invention relates to a distributed control system in which an upper processor is connected to a desired lower processor via a bus, means for the upper processor to manage the lower processor without depending on the state of the lower processor, and the upper processor and the lower processor. By providing a means for communication between the two, it is possible to eliminate the need for the control line that establishes the right to use the bus, and to eliminate the influence of the processor with inferior processing power on the overall processing power. It is a thing.

[Conventional technology]

In the conventional example system, as shown in FIG. 2, an upper processor 10 and lower processors 11 to 1n are connected on a bus 23, and an interprocessor communication request signal line 24 and a control line 25 are provided separately from the bus 23. It is prepared, before connecting the bus for communication between the processors, connect and confirm operation between the upper processor 10 and the lower processors 11 to 1n via this separate line, and after these operations are completed, The bus was being used by a particular processor.

[Problems to be solved by the invention]

Such a conventional example system has a drawback that a control line for obtaining a bus use right is required in addition to a bus used for communication. In addition, the procedure between processors is required to obtain the right to use the bus, and the interface of each processor is complicated. Also, when inter-processor communication request signals are generated from multiple lower-level processors at the same time,
There was a drawback that it was difficult to determine which lower-level processor the communication request came from. Furthermore, since data is directly exchanged between the upper processor and the lower processor,
There is a drawback in that the processing capacity of the system is determined by the speed of a processor having a poor processing capacity.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a distributed control system in which a bus use right is established by a simple means and the processing capacity of the system is not restricted by a processor having a poor processing capacity.

[Means for solving problems]

The present invention provides a distributed control system comprising a higher processor and a plurality of lower processors connected to the upper processor via a bus, wherein a bus control circuit is provided between the upper processor and the lower processor. The control circuit is connected to an upper processor by an upper processor bus, and is connected to the lower processor by a lower processor bus, and is provided commonly to the plurality of lower processors to connect the upper processor and the lower processor. A communication memory for temporarily storing data exchanged between the upper processor bus and the one end of the upper processor monitoring control bus and one end of the communication memory; and the lower processor bus is the upper processor. Connected to the other end of the supervisory control bus and the other end of the communication memory, When sending information from the processor to any of the lower processors, the upper processor sends a received command signal to the lower processor via the upper processor bus, the upper processor monitoring control bus and the lower processor bus, After that, the upper processor monitoring control bus is blocked, the transmission information content is written to the communication memory via the upper processor bus, and the lower processor that receives the reception command signal transmits the communication via the lower processor bus. Confirms the writing of information to the memory for reading, reads the written information content, and further, the upper processor monitors the read information of the communication memory via the upper processor bus, and reads the read information of the communication memory. The upper processor that has detected the end of reading by monitoring the Characterized in that to return to the initial state by releasing the blockage of the host processor monitors the control bus with releasing the bus usage right of the processor.

[Action]

When the bus ownership of the desired lower processor is established via the upper processor bus, the upper processor monitoring control bus, and the lower processor bus, this upper processor monitoring control bus is blocked, and data from the upper processor to this lower processor is blocked. Is written in the communication memory. While the lower processor reads this written data, the upper processor can perform an operation independent of the lower processor. After the reading is completed, the bus occupation right of the lower processor and the blockage of the upper processor monitoring control bus are released. Data transmission from the lower processor to the upper processor is also executed via the communication memory.

〔Example〕

Hereinafter, a method according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment system of the present invention. The upper processor 10 is connected to the bus control circuit 30 via the upper processor bus 20, and inside the bus control circuit 30, the upper processor bus 20 is connected to one end of the upper processor monitoring control bus 21 and one end of the communication memory 31. The other end of the upper processor monitoring control bus 21 and the other end of the communication memory 31 are connected to the lower processor bus 22, and the lower processor bus 22 includes the first lower processor 11,
The second lower processor 12, ..., And the nth lower processor 1n are connected. In the i-th lower processor 1i, the lower processor bus 22 is connected to the processor 1i2 and the processor bus interface 1i1.

Unless the upper processor 10 permits the lower processor bus 22, the lower processor bus 22 is in a 3-state state, and no lower processor can use the lower processor bus 22.

Now, when sending information from the upper processor 10 to the first lower processor 11, the processor of the first lower processor 11 passes through the upper processor bus 20, the upper processor monitoring control bus 21 and the lower processor bus 22. A reception command is sent to the interface 111, and then the upper processor monitoring control bus 21 is blocked, and the communication memory 31
Write information content to. On the other hand, the first lower processor 11
When the processor interface 111 receives a reception instruction from the upper processor 10, the processor interface 11
An interrupt is generated from 1 to the processor 112 via the interrupt line 113, and the processor 112 reads communication direction information (in this case, the direction from the upper processor 10 to the first lower processor 11) from the processor interface 111. , The operation for checking whether or not the data from the upper processor 10 is written in the communication memory 31 is started. On the other hand, when the upper processor 10 writes all the necessary data in the communication memory 31 after blocking the upper processor monitoring control bus 21, the upper processor 10 shifts to the operation of monitoring the data read information of the communication memory 31. . The data read speed depends on the processing capability of the first lower processor 11, but the upper processor bus 20 becomes independent of the lower processor bus 22 after the lower processor bus 22 is occupied by the first lower processor 11. Since it can operate, the processing can be executed independently of the lower processor bus 22. First lower processor
After 11 has read all the information from the upper processor 10, the upper processor 10 detects the end of reading by monitoring the state of the communication memory 31, and the lower processor bus exclusive right of the first lower processor 11 (that is, the first lower processor bus right). (Interruption to the lower processor 11) is released to return to the initial state where the blockage of the upper processor monitoring control bus is also released.

Next, when transmitting information from the first lower processor 11 to the upper processor 10, the first lower processor 11 gives a transmission request flag to the processor interface 111. On the other hand, the upper processor 10 periodically monitors the transmission request flags from the first lower processor 11 to the nth lower processor 1n via the upper processor monitoring control bus 21. When the transmission request flag is confirmed, the processor interface 111 of the first lower processor 11 is passed via the upper processor bus 20, the upper processor monitoring control bus 21 and the lower processor bus 22.
After sending the send command to the host processor, the upper processor monitoring control bus 21 is blocked. The processor interface 111 that has received the transmission command from the upper processor 10 is the processor 112.
To the processor 112 via the interrupt line 113, the processor 112 receives communication direction information from the processor interface 111 (in this case, the first lower processor 11 to the upper processor 10).
Direction) and the first lower processor 11 writes the data in the communication memory 31. The upper processor 10 is a communication memory after blocking the upper processor monitoring control bus 21.
It shifts to the operation of monitoring the data write information to 31, but
Since the data writing speed depends on the processing capacity of the first lower processor 11, the upper processor 10 can perform work without using the lower processor bus 22. The upper processor 10 detects data writing by monitoring the state of the communication memory 31, reads the data via the upper processor bus 20, and thereafter judges that all the data has been read by monitoring the state of the communication memory 31, The lower processor bus exclusive right of the one lower processor 11 (that is, the interrupt to the first lower processor 11) is released, and the block state of the upper processor monitoring control bus is also released to return to the initial state.

〔The invention's effect〕

As described above, the present invention is provided with the bus control function at the midpoint of the bus between the upper processor and the lower processor.
Furthermore, since the lower processor management function and the function to perform inter-processor communication are provided, special signal lines for inter-processor communication can be reduced, and complicated procedures and interface conditions for inter-processor communication can be simplified. There is an effect that can be converted. Further, when a plurality of lower processors request inter-processor communication with the upper processor, the lower processor has a decision right to select the lower processor, which has an effect of preventing signal collision.

Further, in the distributed control type stored program electronic exchange having a plurality of hierarchical processors, the processing capacity of the upper program influences the exchange control time, but in the present invention, even when the lower processor uses the lower processor bus. Since the upper processor can execute processing unrelated to the lower processor bus, there is an effect that the switching connection time can be shortened.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a block diagram showing the configuration of the conventional system. 10-upper processor, 11 to 1n-lower-processor, 20
...... Upper processor bus, 21 ...... Upper processor monitoring control bus, 22 ...... Lower processor bus, 24 ...... Processor communication request signal line, 25 ...... Control line, 30 ...... Bus control circuit, 31 ...... Communication Memory, 111 ... Processor interface, 112 ... Processor, 113 ... Interrupt line.

Claims (1)

[Claims] 1. A distributed control system comprising an upper processor and a plurality of lower processors connected to the upper processor via a bus, wherein a bus control circuit is provided between the upper processor and the lower processor, The bus control circuit is connected to an upper processor by an upper processor bus, and is connected to the lower processor by a lower processor bus, and is provided commonly to the plurality of lower processors, and the upper processor and the lower processor are connected to each other. Communication memory for temporarily storing data exchanged between them, the upper processor bus is connected to one end of the upper processor monitoring control bus and one end of the communication memory, and the lower processor bus is the upper processor bus. Connected to the other end of the processor monitoring control bus and the other end of the communication memory, When sending information from one of the lower processors to any of the lower processors, the upper processor sends a received command signal to the lower processor via the upper processor bus, the upper processor monitoring control bus and the lower processor bus. After that, the upper processor monitoring control bus is closed, the transmission information content is written to the communication memory via the upper processor bus, and the lower processor that receives the reception command signal is the lower processor bus via the lower processor bus. Confirming information writing to the communication memory, reading the written information content, and further, the upper processor monitors the read information of the communication memory via the upper processor bus, and reads the communication memory. The upper processor, which has detected the end of reading by monitoring information, Distributed control method, characterized in that to return to the initial state by releasing the blockage of the host processor monitors the control bus with releasing the bus usage right of position processor.