JPH076050A - Double system switching method - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to reduce system switching time in a dual system having a non-duplex memory. [Structure] An apparatus has a means for calculating an error check code each time data is written to the non-duplex memory and a means for storing the error check code. The means for calculating the error check code and the value stored in advance are compared to determine whether or not to reload the data. [Effect] If the comparison results of the error check codes match, there is no need to reload the data, and the system switching time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual system having a non-duplicated memory, and more particularly to reducing the time required for system switching.

[0002]

2. Description of the Related Art A conventional dual system having two systems, a processing system (operating system) and a standby system (standby system), duplicates two memories included in the processors of the respective systems, and is always the same. By storing the content data, even if one processor stops due to a failure or inspection, the other processor will
It was that the processing could be continued without restarting.

Various means have been disclosed as means for duplicating the two memories included in the processors of the respective systems. One of them will be cited and explained below. FIG. 5 shows, for example, Japanese Patent Laid-Open No. 2-277141.
6 is a block diagram of a conventional dual system shown in Japanese Patent Laid-Open Publication No. JP-A-2003-138, in FIG. Are connected to form an operating system (processing system). Also, 5 is a CP of the same format as the CPU 1.
U and 6 are memories of the same type as the memory 2, and 8 is a PCU of the same type as the PCU 4, which are connected by a common bus 7 to form a standby system (standby system). The memory 2 and the memory 6 have a local bus 9 in the opposite direction.
They are connected by a, and the data stored in the respective memories are always kept the same, whereby the system is duplicated. Further, 9b is a phase-direction bus that connects the PCU 4 and the PCU 8 and performs system switching and the like.

Next, the operation will be described. Normally, the processing is performed by the operation system, and at the time of failure or inspection, it is switched to the standby system by the bus 9b connecting the PCU4 and the PCU8, and the processing from the time when the standby system is switched. Will continue.

Since the memory 2 and the memory 6 are connected by the local bus 9a, the data written in the memory 2 of the active system is simultaneously written in the memory 6 of the standby system. It is what has been. Therefore, even if the system switching occurs as described above, the contents of the memory 2 and the memory 6 match, so that the system can be switched immediately.

Such a duplex system is multiplexed, for example, having a plurality of low-speed lines, collecting traffic data of the low-speed lines, and performing communication with another communication control device at a distance using the high-speed line. When used as a communication control device, the communication control device has the form of the dual system as described above in order to maintain its main control function and communication on a high-speed line. In some cases, the processing system is switched to the standby system so that communication with a remote communication control device can be continued.

However, the communication control device has a plurality of communication terminals under its control, which are connected by low-speed lines, and the speed information of each low-speed line and the communication terminal and each traffic data are stored in the memory 2 or. It is stored in a plurality of non-duplexed memories (non-duplicated memories) other than the memory 6. Such a plurality of non-duplication memories can be accessed from either the processing system or the standby system, but are logically connected to only one of the two systems, It is used, and if both systems are in an operable state, it is normally used in a processing system. Then, when inspecting the above processing system, the data stored in the plurality of non-duplicated memories is preserved and the system is switched to the standby system.
When a failure occurs in the processing system, there is a possibility that the data stored in the non-duplex memory is destroyed due to a malfunction of the processing system.
After the system switching, the standby system creates data to be stored in the non-duplexed memory from the data stored in the memory 6 of the standby system, as shown in FIG. Download to the non-duplicated memory. Then, the communication control device having such a form of the dual system has all the data to be stored in the respective non-duplication memories with respect to the plurality of non-duplication memories included in the communication control device. Finished downloading,
When the startup of the low-speed line is completed, the switching from the processing system to the standby system is completed.

[0008]

A conventional method for switching a dual system is configured as described above, and in a dual system having a dual memory and a non-duplex memory, the system When switching occurs, it is necessary to recreate the data of the non-duplex memory from the data of the duplex memory and download it, and it takes time for the standby system to start up and complete the system switching. was there.

The present invention has been made to solve the above problems, and an object thereof is to shorten the time until the completion of switching in a dual system having a non-duplex memory.

[0010]

A dual system switching method according to the present invention has a dual memory in which a processing system and a standby system store the same data, and performs main processing. In the dual system having only the non-duplex memory, the data to be stored in the non-duplex memory is stored in the non-duplex memory so that the standby system can use the non-duplex memory when the system is switched. In the reloading dual system switching method, means for calculating an error check code based on the data each time data is written in the non-duplex memory, and the calculated error check code Means for storing in the memory, wherein the standby system is configured to store the non-duplex memory at the time of switching from the processing system to the standby system. A means for calculating an error check code based on the stored data and comparing the calculated error check code with the stored error check code, and the comparison result, data to the non-duplex memory. And a means for judging whether or not to reload the system, and when it is judged not to reload the data into the non-duplex memory, the system switching is immediately completed.

Further, the dual system switching method according to the present invention uses a parity check code as the error check code. Further, the double system switching method according to the present invention uses the sum check code as the error check code. Further, the double system switching method according to the present invention uses a CRC code as the error check code.

In the method of switching the dual system according to the present invention, only the system which has the dual memory in which the processing system and the standby system each store the same data, and which is performing the main processing. 2 with non-duplicated memory
In the heavy system, when the system is switched, the data to be stored is reloaded into the non-duplex memory so that the standby system can use the non-duplex memory.
In the heavy system switching method, means for calculating an error correction code based on the data each time data is written in the non-duplex memory, and the calculated error correction code is stored in the non-duplication memory. The standby system, the standby system uses the error correction code stored in the non-duplex memory when switching from the processing system to the standby system. Is provided so that the system switching can be completed without reloading the data into the non-duplex memory.

The dual system switching method according to the present invention uses a BCH code as the error correction code. The dual system switching method according to the present invention uses Reed Solomon as the error correction code.

In the dual system switching method according to the present invention, the processing system and the standby system each have a dual memory in which the same data is stored, and only the system performing the main processing is non-operational. 2 with dual memory
In the heavy system, when the system is switched, the data to be stored is reloaded into the non-duplex memory so that the standby system can use the non-duplex memory.
In the heavy system switching method, a flag corresponding to the non-duplex memory, which is turned on when data is written to the non-duplex memory, and data of the non-duplex memory corresponding to the turned-on flag Means for calculating the error check code or the error correction code based on the above, and means for storing the calculated error check code or the error correction code in the non-duplicated memory and turning off the flag after the storage. And a means for determining whether or not the standby system reloads data into the non-duplex memory according to the status of the flag when the processing system is switched to the standby system. When it is determined that the data is not reloaded to the non-duplex memory, the system switching is immediately completed.

Also, in the duplex system switching method according to the present invention, the calculation of the error check code or the error correction code based on the data of the non-duplex memory corresponding to the ON flag and the non-duplication The storage in the duplicated memory is performed during the idle time of the CPU of the processing system.

Further, the duplex system switching method according to the present invention calculates the error check code or the error correction code based on the data of the non-duplex memory corresponding to the flag which is turned on, and the non-duplication system. The storage in the duplicated memory is performed at a constant cycle based on the clock of the CPU of the processing system.

[0017]

According to the present invention, the dual memory having the processing system and the standby system, respectively, storing the same data, and the non-duplex memory used only by the system performing the main processing. In the dual system switching method, the standby system reloads the data to be stored in the non-duplicated memory in order to use the non-duplicated memory when the system of the dual system having A means for calculating an error check code using a parity check code, a sum check code, a CRC code or the like based on the data each time the data is written in the non-duplex memory; and the calculated error check code, Means for storing in the non-duplicated memory, and when switching from the processing system to the standby system, A standby system that calculates an error check code based on the data stored in the non-duplex memory, and compares the calculated error check code with the stored error check code; A means for judging whether or not the data is reloaded to the non-duplex memory according to the comparison result, and when it is judged not to reload the data to the non-duplex memory, the system switching is immediately completed. Therefore, if the calculated error check code matches the stored error check code, it is determined that the data stored in the non-duplicated memory is valid, and The system switching will be completed without reloading the data to the duplicated memory, thus shortening the time until the system switching is completed. Rukoto can.

Further, according to the present invention, the processing system and the standby system each have a duplicated memory storing the same data, and only the system performing the main processing has a non-duplicated memory. In a dual system, when the system is switched, the standby system is
In a dual system switching method for reloading data to be stored in the non-duplicated memory so that the duplicated memory can be used, every time data is written in the non-duplicated memory, a BCH code is generated based on the data. Alternatively, it has means for calculating an error correction code using Reed-Solomon or the like, and means for storing the calculated error correction code in the non-duplicated memory, and from the processing system to the standby system. At the time of switching, the standby system uses the error correction code stored in the non-duplication memory to perform the non-duplication.
A means for correcting an error in the data of the redundant memory is provided, and the system switching is completed without reloading the data into the non-redundant memory. Even if the stored data is damaged, the error in the data is corrected, so there is no need to reload the data to the non-duplexed memory, which can shorten the time until the system switching is completed. it can.

Further, according to the present invention, the processing system and the standby system each have a duplicated memory storing the same data, and only the system performing the main processing has a non-duplicated memory. In a dual system, when the system is switched, the standby system is
In a dual system switching method for reloading data to be stored in the non-duplicated memory so that the duplicated memory can be used, the non-duplicated memory is supported, and data is written in the non-duplicated memory. Has a flag that turns on,
The error check code or the error correction code based on the data of the non-duplicated memory corresponding to the flag that is turned on in a certain period based on the idle time of the CPU of the processing system or the clock of the CPU And a means for storing the calculated error check code or error correction code in the non-duplicated memory at the idle time or the constant period and turning off the flag after the storage. When the processing system is switched to the standby system, the standby system includes means for determining whether to reload data into the non-duplex memory according to the status of the flag. If you decide not to reload the data to the non-duplex memory, make sure to complete the system switching immediately. Therefore, the error check code or the error correction code is calculated and stored without lowering the throughput of the processing system, and the contents were updated when the system was switched, but the calculation was still performed. Only the non-duplication memory that does not store the error check code or the error correction code and the non-duplication memory in which the calculated error check code and the stored error check code do not match are reloaded with data. As a result, it is possible to shorten the time until the completion of system switching without lowering the processing capacity of the processing system.

[0020]

【Example】

Example 1. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a dual system having a non-duplicated memory according to the first embodiment. In FIG. 1, 1 and 5 are CPUs of the same type, 2 and 6 are memories of the same type, 13 is a common bus, 10 is a processing system main card, and has a CPU 1 and its memory 2, and 11 is a standby system. It is a main card and has a CPU 5 and its memory 6. The processing system main card 10 and the standby system main card 11 form a dual system, and by exchanging data via the common bus 13, the memory 2 and the memory 6 of each main card are separated. Data of the same content is stored and duplicated. Also, 1
2a to 12n are plural sub cards, and 14a to 14n are non-two each of plural sub cards 12a to 12n.
The error check code areas 15a to 15 are included in the non-duplex memories 14a to 14n, respectively.
There is n. The sub cards 12a to 12n are connected to each other via the common bus 13 and also to the processing system main card 10 and the standby system main card 11. However, until the system switching occurs, the sub card 12
Logically, a to 12n are connected only to the main card of either system.

Next, the operation of the first embodiment will be described. Duplex systems with non-duplexed memory typically
The processing is performed by the processing system,
The processing system main card 10 and the sub cards 12a to 12n are operating. Also, at this time, the spare main card 1
1, the memory 2 included in the processing system main card 10
The data with the same contents as the data written in
Is being written to.

When data is written in the non-duplex memory 14a of the sub card 12a, the CPU 1
Calculates an error check code from the written data, writes the data in the non-duplex memory 14a, and stores the calculated error check code in the error check code area 15a of the non-duplex memory 14a. Here, the error check code is calculated and stored for each block of data to be written, and the CPU 1 causes the non-duplex memory 14b of the sub cards 12b to 12n other than the sub card 12a to be stored.
Similarly, in the write operation for 14n, the above error check code is calculated and stored.

Here, when a failure occurs in the processing system main card 10, as shown in the flow chart of the series of operations in FIG. 7, first, the execution of the process is switched to the standby system main card 11. The sub cards 12a-1
2n is logically connected to the spare main card 11. The CPU 5 of the spare main card 11
Scans the data in all areas of the non-duplexed memories 14a to 14n and calculates an error check code.

Next, the CPU 5 performs this scan,
The calculated error check code is compared with the error check codes stored in the error check code areas 15a to 15n, and if they match, the startup of the standby system is completed. Further, due to the malfunction of the processing system main card 10 that has caused a failure, the non-duplex memories 14a to 14a
If the data stored in any of 4n is destroyed, the error check is performed by comparing the calculated error check code with the error check code stored in the error check code areas 15a to 15n. Code mismatch occurs. For example, the above 2
If a code mismatch occurs during the comparison operation of the error check codes stored in the duplicated memory 14a, the above CP
The U5 creates the data to be stored in the non-duplex memory 14a in the memory 6, and downloads (reloads) the created data from the memory 6 to the non-duplication memory 14a. However, the non-duplication memory 14a due to the malfunction of the processing system main card 10 as described above.
Destruction of the stored data of ~ 14n does not occur frequently, and in most cases, the error check codes match and the startup is completed without requiring the download.

In the first embodiment, because of the above-described configuration, when the calculated error check code and the stored error check code match, the non-duplexed memories 14a to 14n. Since it is determined that the data stored in the processing main card 10 is valid and the data is not reloaded to the non-duplex memories 14a to 14n, the processing main card 10 in the first embodiment shown in FIG. The time t2 from the occurrence of a failure to the completion of startup of the standby main card 11 is shorter than the time t1 from the failure occurrence in the processing system to the completion of startup of the standby system in the conventional example shown in FIG. As a result, the time required to complete the system switching can be shortened.

Example 2. The second embodiment of the present invention will be described below. In the second embodiment, the configuration is the same as that of the first embodiment, and the parity check code is used as the error check code.

The case where odd parity is used for the parity check code will be described below. For example 100
A parity bit (a-P) of 1 bit is added to write data of a byte, and the parity (a-P) is added.
P) is stored in the error check code areas 15a to 15n. Then, assuming that 1 byte of the 100-byte data is updated, the parity (b-P) of the 1-byte updated data is calculated, and the parity (b-P) and the error Check code area 1
The exclusive OR of the parities (a-P) stored in 5a to 15n is calculated.

Next, the error check code area 15 is used as the solution of the exclusive OR as the parity (a'-P) for the updated data in 1 byte out of 100 bytes.
Store in a to 15n.

In the second embodiment, since the parity check code is used as the error check code, the stored data is updated and the new parity check code for the updated data is used as described above. It is not necessary to read all the new storage data including the update data and calculate the parity when calculating the above. This makes it possible to shorten the calculation time and switch the system without lowering the processing capacity of the CPU 1. A dual system switching method capable of shortening the time can be obtained.

Example 3. The third embodiment of the present invention will be described below. The third embodiment has the same configuration as that of the first embodiment and uses a sum check code as an error check code.
When the data stored in the non-duplexed memories 14a to 14n is updated, a sum check code for the updated data is calculated, and the sum check code and
A new sum check code is calculated from the sum check code stored in the error check code areas 15a to 15n.

Also in the third embodiment, since the sum check code is used as the error check code, all the new storage data including the update data is read and the sum check code is used as in the second embodiment. Since it is not necessary to calculate, the calculation time can be shortened and the decrease in the processing capacity of the CPU 1 can be prevented. Further, there is an effect that the reliability of the error check can be further improved as compared with the second embodiment using the parity check code.

Example 4. Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a schematic diagram of the non-two according to the fourth embodiment.
FIG. 3 is a block diagram showing a dual system having a duplicated memory. 2, the same reference numerals as those in FIG. 1 in the first embodiment indicate the same or corresponding portions, and the non-duplicated memory 14a
To 14n are divided into blocks, and 14a1 to 14n, respectively.
It is assumed that the non-duplicated memories 14a1 to 14nm are divided into m blocks and have error check code areas 15a1 to 15nm, respectively.

Next, the operation of the fourth embodiment will be described. In the fourth embodiment, a CRC code is used as the error check code.

The CRC code has a higher ability to find the data check in the memory than the parity check code or the sum check code, and is very reliable. However, on the other hand, when an update write occurs, like the parity check code or the sum check code, the CRC code of the update data is calculated, and the calculated CRC code and the old C stored
A new CRC code cannot be calculated from the RC code, and a new CRC code must be calculated from all the data in the updated memory.

Therefore, in order to reduce the calculation time, the non-duplicated memories 14a to 14n in the above-described first to third embodiments are divided into blocks, and the non-duplicated memories 14a1 to 14a1 to 14n are divided into blocks as shown in FIG.
It was set to 14 nm. The non-duplex memories 14a1 ...
Error check code area 15a1 at 14nm
-15 nm is provided, and the CRC code is stored therein. For example, when a part of the data stored in the non-duplex memory 14a1 is rewritten, the CP
U1 reads all the new data stored in the non-duplex memory 14a1, calculates a new CRC code, and stores the CRC code in the error check code area 15a1.

Then, a failure occurs, and the processing system 10
When the standby system 11 is switched to the standby system 11, the CPU 5 of the standby system 11 causes the non-duplex memory 14 to operate.
A CRC code is calculated for each a1 to 14 nm, and each calculated CRC code is compared with the old CRC code stored in the error check code area 15a1 to 15 nm.

In the fourth embodiment, the CRC code is used as the error check code, and the non-duplex memory 14a is used.
-14n are divided into blocks, and non-duplexed memories 14a1 -1
4 nm, and each non-duplicated memory 1 is divided into blocks.
Since the error check code areas 15a1 to 15nm for storing the CRC code are provided in 4a1 to 14nm, and the CRC code is calculated for each of the blocked non-duplex memories 14a1 to 14nm.
There is an effect that a code can be calculated quickly, a highly reliable memory can be inspected, and a dual system switching method that can shorten the system switching time can be obtained.

Example 5. A fifth embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block diagram of a dual system having a non-duplex memory according to the fifth embodiment.
In FIG. 3, the same reference numerals as those in FIG. 1 in the first embodiment indicate the same or corresponding portions, and 16a to 16n are error correction code areas.

Next, the operation of the fifth embodiment will be described. The duplex system switching method of the fifth embodiment is almost the same as that of the first embodiment in terms of its configuration.
Error check code areas 15a to 15n are set as error correction code areas 16a to 16n, and the non-duplication memory 14a
In addition to detecting the data check of 14n to 14n, if the data check can be corrected, the correction is performed using the error correction code stored in the error correction code areas 16a to 16n. Therefore, only the operation different from that of the first embodiment will be described below.

For example, when processing is performed by the processing system main card 10 and data is written in the non-duplex memory 14a of the sub card 12a, the CPU 1 calculates an error correction code each time the data is written. Then, the data is written in the non-duplication memory 14a and the calculated error correction code is stored in the error correction code area 16a of the non-duplication memory 14a. The error correction code is calculated and stored for each block of data to be written, and the CPU 1 causes the non-duplicated memories 14b to 14n of the sub cards 12b to 12n other than the sub card 12a to be stored. Similarly, in the write operation for, the error correction code is calculated and stored.

When a failure occurs in the processing system main card 10, first, the execution of processing is switched to the standby system main card 11, and the sub card 1
2a to 12n are logically the standby main card 11
Connected to. Then, the CPU 5 of the standby main card 11 scans the data in all areas of the non-duplex memories 14a to 14n, and the error correction code area 1
Using the error correction codes stored in 6a to 16n,
When it finds a modifiable data check, it modifies the data sequentially.

Then, the non-duplex memories 14a to 14
When the scanning of the data in all areas of n is completed, the start-up of the standby system is completed.

In the fifth embodiment, the non-duplication memories 14a to 14n are provided with the error correction code areas 16a to 16n for storing error correction codes, and the data to be written in the non-duplication memories 14a to 14n. The error correction code is calculated from the error correction code and the CPU 5 of the standby system main card 11 stores the error correction code stored in the error correction code areas 16a to 16n when the system is switched from the processing system to the standby system. Since the data check is corrected by using the code, the CPU 5 does not need to create the data to be stored in the non-duplex memories 14a to 14n and download the data. To obtain a dual system switching method that can speed up the startup of the standby system and shorten the system switching time. It can be.

Example 6. The sixth embodiment of the present invention will be described below. In the sixth embodiment, a BCH code is used as the error correction code, and the error correction code area 16 is used.
The data is stored in a to 16n.

Although the BCH code does not have a high error correction capability, its calculation is simpler than that of other error correction codes, so that the calculation time can be shortened. Therefore, it is effective for a dual system in which a light data check is likely to occur.

Also in the sixth embodiment, when the system is switched from the processing system to the backup system, the CPU 5 of the backup main card 11 is stored in the error correction code areas 16a to 16n. BCH
Since the data check is modified by using the code, the CPU 5 causes the non-redundant memories 14a to 14a to operate.
It is not necessary to create the data to be stored in n and to download the data. This makes it possible to speed up the startup of the standby system and shorten the system switching time. You can get the way.

Example 7. The seventh embodiment of the present invention will be described below. In the seventh embodiment, Reed Solomon is used as the error correction code, and the error correction code area 1 is used.
The data is stored in 6a to 16n.

Although the Reed-Solomon is complicated in its calculation, it has a high error correction capability, so that a severe data check is likely to occur, and a large amount of data should be stored in the non-duplex memories 14a to 14n. In particular, it is particularly effective for a dual system in which it takes a long time to create and download it.

In the seventh embodiment as well, it is not necessary to create and download the above-mentioned data, whereby the start-up of the standby system can be speeded up,
A dual system switching method that can shorten the system switching time can be obtained.

Example 8. An eighth embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows the non-2
FIG. 3 is a block diagram showing a dual system having a duplicated memory. 4, the same reference numerals as those in FIG. 1 in the first embodiment indicate the same or corresponding portions, and 17a to 17n are flags.

In the first embodiment, the non-duplex memory 1 is used.
An error check is performed every time data is written to 4a to 14n.
A code is calculated, and the calculated error check code is used as the error check code area 15a to 15n.
Further, in the fifth embodiment, an error correction code is calculated every time data is written in the non-duplex memories 14a to 14n, and the calculated error correction code is stored in the error correction code areas 16a to 16n. Was stored in. However, in a dual system in which memory access frequently occurs, the load of the CPU 1 of the processing system increases due to the calculation of the error check code or the error correction code, and the throughput decreases. Therefore, in the eighth embodiment, the flags 17a to 17n are provided in the non-duplex memories 14a to 14n, respectively.

Next, the operation of the eighth embodiment will be described when an error check code is used. However, the same operation as that of the first embodiment is omitted. First, when processing is being performed by the processing system main card 10, CP
When U1 writes data to the non-duplex memory 14a included in the sub card 12a, the flag 17
When a is turned on, the data is immediately written, and then the data is written to the non-duplex memory 14a again, the flag 17a is confirmed and the flag 17a is checked.
If a is on, that data is also written immediately. At that time, if the flag 17a is off, it is turned on and the data is immediately written.

When the data processing amount of the processing system is reduced and the CPU 1 is in the idling state, the C
The PU 1 scans the entire area of the non-duplexed memory 14a having the flag 17a turned on, sequentially calculates an error check code, and stores the calculated error check code in the error check code area 15a. Store sequentially. Then, the CPU 1 turns off the flag 17a that is turned on when all the error check codes are calculated and stored in the error check code area 15a.

Further, the CPU 1 is the sub card 1
Similarly, in the write operation to the non-duplex memories 14b to 14n of the sub cards 12b to 12n other than 2a,
The operation of the flags 17b to 17n and the calculation and storage of the error check code are performed.

When a failure occurs in the processing system main card 10, the standby system main card 11
Execution of the process is switched to the sub card 12a-
12n is logically connected to the standby main card 11.

C of the spare main card 11
The PU 5 first confirms the states of the flags 17a to 17n included in the non-duplexed memories 14a to 14n. At this time, for example, if only the flag 17b is on, the CPU 5 determines that the error check code stored in the error check code area 15b of the non-duplex memory 14b is not reliable, and The data to be stored in the non-duplex memory 14b is created and downloaded.

Next, the CPU 5 performs the same operation as that of the first embodiment on the non-duplex memories 14a and 14c to 14n having the flags 17a and 17c to 17n in the off state, and performs the preliminary operation. Completed the startup of related systems.

In the eighth embodiment, the flags 17a to 17n are provided in the non-duplication memories 14a to 14n,
Turn on the flag of the non-duplex memory where the write occurred,
During the idle time of the CPU 1, the error check code is calculated only for the non-duplicated memory having the ON flag, so the error check code can be calculated without lowering the system throughput. Therefore, it is possible to obtain a method for switching a dual system that can shorten the system switching time.

In the eighth embodiment, the flag 17a is used.
.About.17n are provided in the non-duplication memories 14a to 14n, but tables may be provided in the duplication memories 2 and 6 and stored in the tables.

Example 9. The ninth embodiment of the present invention will be described below. The ninth embodiment has the same configuration as that of the eighth embodiment, and the error check code is calculated during the idle time of the CPU1 in the eighth embodiment, but the error check code is calculated at a constant cycle using the clock of the CPU1. The error check code is calculated.

Also in the ninth embodiment, the flags 17a to 17n are provided in the non-duplexed memories 14a to 14n,
Turn on the flag of the non-duplex memory where the write occurred,
Since the error check code is calculated only for the non-duplexed memory having the ON-state flag at a constant cycle using the clock of the CPU 1, the error check code is not reduced without decreasing the system throughput. It is possible to obtain a method for switching the dual system, which can reduce the system switching time.

[0062]

As described above, according to the dual system switching method of the present invention, the processing system and the standby system each have a dual memory storing the same data, and the main processing is performed. In a dual system in which only the system performing the non-duplex memory has a non-duplex memory, the standby system should store the non-duplex memory so that the standby system can use the non-duplex memory when the system is switched. In the dual system switching method of reloading data, every time data is written in the non-duplex memory, an error check code using a parity check code, a sum check code, a CRC code or the like is calculated based on the data. Means and means for storing the calculated error check code in the non-duplicated memory,
At the time of switching from the processing system to the standby system, the standby system calculates an error check code based on the data stored in the non-duplex memory, and the calculated error check code and the above A means for comparing with the stored error check code and a means for judging whether or not to reload the data into the non-duplex memory according to the comparison result are provided, and the data is loaded into the non-duplication memory. When it is determined not to reload, the system switching is immediately completed. Therefore, when the calculated error check code and the stored error check code match, the non-duplex memory is stored. The stored data is judged to be valid, and the system switching is completed without reloading the data to the non-duplex memory. It and becomes to, thereby there is an effect that it is possible to shorten the time to completion switching system.

Further, according to the dual system switching method of the present invention, the system having the dual memory in which the processing system and the standby system store the same data, and performing the main processing. In a dual system having only non-duplex memory, when the system is switched, the data to be stored is reloaded into the non-duplex memory so that the standby system can use the non-duplex memory. In the heavy system switching method, every time data is written in the non-duplex memory, B is set based on the data.
It has means for calculating an error correction code using a CH code or Reed-Solomon, and means for storing the calculated error correction code in the non-duplicated memory. When switching to the non-duplexing mode, the standby system includes means for correcting an error in the data of the non-duplexing memory using the error correction code stored in the non-duplexing memory. Since the system switching is completed without reloading the data to the memory, even if the data stored in the non-duplex memory is damaged during the system switching, the error of the data is corrected. Therefore, there is no need to reload the data into the non-duplex memory, which has the effect of shortening the time until completion of system switching.

Further, according to the dual system switching method of the present invention, the system in which the processing system and the standby system each have a dual memory storing the same data, and the main processing is performed. In a dual system having only non-duplex memory, when the system is switched, the data to be stored is reloaded into the non-duplex memory so that the standby system can use the non-duplex memory. In the heavy system switching method, a flag corresponding to the non-duplex memory and having a flag which is turned on when writing data to the non-duplex memory, is provided in the processing system C.
A means for calculating the error check code or the error correction code based on the data of the non-duplex memory corresponding to the flag which is turned on in a certain period based on the idle time of the PU or the clock of the CPU; , The idle time or the fixed period,
Means for storing the calculated error check code or error correction code in the non-duplexed memory and turning off the flag after storage, and when switching from the processing system to the standby system The standby system includes means for determining whether to reload the data to the non-duplex memory according to the status of the flag, and immediately when the determination is made not to reload the data to the non-duplication memory. Since the system switching has been completed, it is possible to calculate and store the error check code or the error correction code without deteriorating the processing capability of the processing system, and to complete the system switching. It has the effect of shortening the time until.

[Brief description of drawings]

FIG. 1 is a block diagram showing a dual system having a non-duplex memory according to first to third embodiments of the present invention.

FIG. 2 is a block diagram showing a dual system having a non-duplexed memory according to a fourth embodiment of the present invention.

FIG. 3 is a block diagram showing a dual system having a non-duplex memory according to fifth to seventh embodiments of the present invention.

FIG. 4 is a block diagram showing a dual system having a non-duplexed memory according to eighth and ninth embodiments of the present invention.

FIG. 5 is a block diagram showing a conventional dual system.

FIG. 6 is a diagram showing a time required for switching a conventional dual system.

FIG. 7 is a diagram showing a time required for switching the dual system according to the first embodiment of the present invention.

[Explanation of symbols]

 1 CPU 2 Memory 3 Common Bus 4 PCU 5 CPU 6 Memory 7 Common Bus 8 PCU 9a Local Bus 9b Bus 10 Processing Main Card 11 Spare Main Card 12a to 12n Sub Card 13 Common Bus 14a to 14n Non-Duplicate Memory 15a -15n Error check code area 16a-16n Error correction code area 17a-17n Flag

Claims (10)

[Claims] 1. A processing system and a standby system each have a dual memory storing the same data,
In a dual system in which only the system performing the main processing has a non-duplex memory, the non-duplex memory is stored in the non-duplex memory so that the standby system can use the non-duplex memory when the system is switched. In the dual system switching method for reloading data to be rewritten, a means for calculating an error check code based on the data each time the data is written in the non-duplex memory, and the calculated error check code Means for storing in the non-duplex memory, and at the time of switching from the processing system to the standby system, the standby system outputs an error check code based on the data stored in the non-duplex memory. A means for calculating and comparing the calculated error check code with the stored error check code; And a means for determining whether or not to reload the data into the non-duplicated memory according to the comparison result of 1., and when it is determined not to reload the data into the non-duplicated memory, the system switching is immediately completed. A double system switching method characterized by the above. 2. The dual system switching method according to claim 1, wherein a parity check code is used as the error check code. 3. The dual system switching method according to claim 1, wherein a sum check code is used as the error check code. 4. The dual system switching method according to claim 1, wherein CRC (Cycle Redu) is used as the error check code.
ndancy Check) code is used for the dual system switching method. 5. The processing system and the standby system each have a dual memory storing the same data,
In a dual system in which only the system performing the main processing has a non-duplex memory, the non-duplex memory is stored in the non-duplex memory so that the standby system can use the non-duplex memory when the system is switched. In the dual system switching method of reloading data to be rewritten, a means for calculating an error correction code based on the data each time the data is written in the non-duplex memory, and the calculated error correction code Means for storing in the non-duplex memory, and the standby system uses the error correction code stored in the non-duplex memory when switching from the processing system to the standby system. A means for correcting an error in the data of the non-duplex memory, and completing the system switching without reloading the data to the non-duplex memory. Characteristic dual system switching method. 6. The method for switching a dual system according to claim 5, wherein the error correction code is BCH (Bose-Chaudhuri-hocq).
enghen) code is used for the dual system switching method. 7. The dual system switching method according to claim 5, wherein Reed Solomon is used as the error correction code. 8. The processing system and the standby system each have a dual memory storing the same data,
In a dual system in which only the system performing the main processing has a non-duplex memory, the non-duplex memory is stored in the non-duplex memory so that the standby system can use the non-duplex memory when the system is switched. In a dual system switching method for reloading data to be stored, the flag corresponds to the non-duplex memory and is turned on when writing data to the non-duplex memory, and corresponds to the flag turned on. Means for calculating an error check code or error correction code based on the data of the non-duplex memory, and storing the calculated error check code or error correction code in the non-duplex memory, and storing the flag after storage. When the processing system is switched to the standby system, the standby system has a means for turning it off. A means for judging whether or not to reload the data to the non-duplex memory is provided according to the situation, and when it is judged not to reload the data to the non-duplex memory, the system switching is immediately completed. A double system switching method characterized by the following. 9. The dual system switching method according to claim 8, wherein the calculation of the error check code or the error correction code and the storage in the non-duplex memory are performed by a CPU of the processing system. A dual system switching method characterized by being performed during idle time. 10. The dual system switching method according to claim 8, wherein the calculation of the error check code or the error correction code and the storage in the non-duplex memory are performed by a CPU of the processing system. A dual system switching method characterized by being performed at a constant cycle based on a clock.