JPH076079A - Elastic memory circuit - Google Patents

Abstract

(57) [Summary] [Object] For example, regarding an elastic memory circuit used in a mobile communication system using the TDMA method, an object thereof is to prevent loss of read data. In an elastic memory circuit having a write address generating means 2 and a memory means 1, a sync signal detecting means 3 for sending a sync detection signal when a sync signal in input data is detected, and an input sync detection signal. From the time of input using the read clock (1
After delaying by / 2), the load timing generating means 4 which sends out as read load timing, and of the input write addresses, add (1/2) of the number of write addresses to the write address when the read load timing is applied. The read address generating means 5 for sending the read address as a read address to the memory means is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elastic memory circuit used in a communication system using the TDMA system, for example.

A base station of a mobile communication system using the TDMA system sequentially takes out data of each mobile station, writes the data in a memory, and then reads the written data.
At this time, since the clocks of the mobile stations are asynchronous, it is necessary to prevent the read data from being lost when reading the data of different mobile stations.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional example. In the figure, the write address generating portion 23 is composed of, for example, an octal counter, and repeatedly generates write addresses from 0 to 7 using a write clock (hereinafter, abbreviated as W-CK) to generate a memory 11 To the phase comparison part 61. Therefore, the input data is sequentially written in parallel to the corresponding write address in the memory 11 by using W-CK.

The read address generating section 53 also repeatedly generates read addresses from 0 to 7 and sends them to the multiplexer 12 and the phase comparing section 61, so that the multiplexer 12 can read from 0 to 7 read addresses. The write data is sequentially read and taken out as serial data.

Since the phase comparison part 61 compares the phases of the write address and the read address of the same address and adds the corresponding phase difference signal to the phase synchronization part 62, the phase synchronization part 62 has a phase difference of 180 degrees. The phase-controlled R-CK is sent to the required part.

As a result, for example, the read address of address 0 is sent out at the timing exactly in the middle of the write address of the adjacent address 0 (timing of write address "3"). The same applies to the addresses of other addresses. The phase-locked portion 62 is composed of, for example, a low-pass filter composed of an operational amplifier (not shown), a voltage-controlled oscillator, or the like.

[0007]

As described above, the phase-locked portion is composed of a low-pass filter using an operational amplifier, a voltage-controlled oscillator, and the like. However, these characteristics vary depending on voltage fluctuations and ambient temperature fluctuations. Change.

Further, in the base station of the mobile communication system using the TDMA method, the data of each mobile station taken out is written in the memory by using the clock extracted from each data, but the clock of each mobile station is asynchronous. Therefore, the W-CK interval is different.

For this reason, when the data of the mobile station is switched, the phase-locked portion of the base station must be immediately synchronized with the clock of the switching-destination mobile station, but the phase-locked portion has a large time constant (for example, a low value). Since there is a pass filter,
Clock synchronization takes a long time, and there is a possibility that a part of the data will be lost when the data of the switching destination mobile station is read.

At this time, if the characteristics of the phase locked portion fluctuate due to changes in environmental conditions, there is a problem that the possibility of missing read data becomes higher. An object of the present invention is to prevent loss of read data.

[0011]

FIG. 1 is a block diagram showing the principle of the first aspect of the present invention. In the figure, 1 is a memory means for writing input data including a synchronization signal to an applied write address and reading data from the applied read address,
Reference numeral 2 is a write address generating means for generating a write address, and 3 is a sync signal detecting means for sending a sync detection signal when a sync signal in input data is detected.

Reference numeral 4 denotes (1/1 / the number of write addresses from the time of input of the input synchronization detection signal using a read clock).
After being delayed by 2), the load timing generation means 5 for sending out as read load timing, 5 of the input write addresses to the write address at the time when the read load timing is applied is (1 /
It is a read address generating means for sending the address obtained by adding only 2) to the memory means as a read address.

Also, 22 is an address obtained by adding (1/2) of the number of read addresses to the read address at the time when the write load timing is applied among the read addresses to be input, and sent to the memory means as a write address. 42 is a write address generating means, and 32 is a load timing generating means for transmitting the input synchronization detection signal as write load timing after delaying (1/2) the number of read addresses from the input time point using a write clock.
Is a sync signal detecting means for sending a sync detection signal when the sync signal in the read data is detected.

In the first aspect of the present invention, the read start address is set to the read start address at the address approximately in the center between the start value and the end value of the write address, and the read of the written data is started from this address. Also, the second aspect of the present invention is different from the first aspect of the present invention in that the read start address is used to control the address at which writing is started.

[0015]

According to the first aspect of the present invention, for example, when 8-bit data including a sync signal and a data portion is input, the write address sent from the write address generating means 2 of FIG. Data is sequentially written from address 0 to address 7. This write address is also added to the read address generating means 5.

Further, the sync signal detecting means 3 detects the sync signal in the input data and sends the sync detection signal to the load timing generating means 4. The load timing generating means uses the read clock to delay the synchronization detection signal by "4" write address from the input time point, and then sends it to the read address generating means 5 as the read load timing.

Therefore, the read address generating means sends the address obtained by adding 4 addresses to the write address at the time when the read load timing is applied to the memory means as the read start address. As a result, when the write address is 0, the read address is 4, and the phase between the write start and the read start is 180 degrees out of phase, so there is no possibility of reading unwritten data and there is no loss of read data.

The second aspect of the present invention is different from the first aspect of the present invention in that the function on the writing side and the function on the reading side are exchanged, and the effect is the same as the above.

[0019]

FIG. 2 is an explanatory view of the first embodiment of the present invention.
(a) is a block diagram, (b) is a TDMA signal explanatory drawing. Also,
FIG. 3 is an operation explanatory diagram of FIG. 2, and FIG. 4 is a configuration diagram of the second embodiment of the present invention.

The symbols on the left side of FIG. 3 are explanatory diagrams of the operation of the same symbols in FIG. In addition, the same reference numerals indicate the same symmetrical objects throughout the drawings. Hereinafter, the write / read address generation portion is composed of an octal counter, and addresses 0 to 7
The operation of the figure will be described on the assumption that 8 addresses are transmitted.

First, in a mobile communication system using the TDMA system, as shown in FIG. 2 (b), guard time bits (GB) are added before and after the burst signal train so that burst signals from mobile stations do not overlap. It is provided in. In the present invention, the final position of this guard time bit (the beginning position of UW) is obtained by establishing synchronization using a unique word (UW).
This position is the beginning of the write address (hereinafter abbreviated as W address). Then, the read address generation circuit (
The address generated by (hereinafter, abbreviated as R address generation circuit) is set to (W address + 4 addresses), so the guard time bit (GB) is not written to the memory, but since this bit is invalid data, Usually, the following signal processing is not performed.

Now, the W address generating portion 21 of FIG.
Is composed of an octal counter in the same manner as above, generates a W address using a write clock (hereinafter abbreviated as W-CK), and sends it to the memory 11 and the R address generation part 51. . Therefore, the input data A, B, C ...
It is written in parallel in the area from W address 0 to address 7 in 11 in order (see FIG. 3-).

Further, the sync signal detecting section 31 sends the sync detection signal S ₁ to the load timing generating section 41 when the sync signal (UW) in the input data is detected. The load timing generation section 41 uses the input synchronization detection signal as a read clock.
(Hereinafter, it is abbreviated as R-CK.) After passing through a 3-bit delay part (not shown), it is sent to the R address generation part 51 as the read load timing L ₁ (FIG. 3-
, See).

Here, originally, the W address generation portion 21 and the R
It is desirable that the operating phase of the address generating part 51 is 180 degrees out of phase (when the generated W address is 0, the R address is 4), but at time t ₀ in FIG.
When the W address generated at is 0, the R address generation part 51
The R address generated at 5 is 5, which is 1 bit shifted with the desired phase.

Therefore, the fourth bit after the synchronization detection signal is transmitted
To make it the first bit of the data to be read (the W address is "6" from Fig. 3-), the R address at this timing must be set to the desired value "2".

For this reason, since the number of addresses is 8, if the R load timing delayed by 3 bits is sent to the R address generating portion to stop the operation for 1 bit, the R address is changed as shown at time t ₁ in FIG. Since the R address "2" from the generation part is duplicated, the data "C" is also read twice.

That is, the R address generating portion 51 adds "4" to the W address "6" input when the read load timing is applied and sends the R address "2" to the multiplexer 12. The multiplexer 12 takes out the data C at the R address "2" and sends it out as read data (see FIG. 3-).

Then, four bits after the input of the next synchronization detection signal S ₂ (time t _{2 in} FIG. 3), the R address generating portion 51 generates the desired R address "1". In this case, the operating phases of the W address generation part and the R address generation part are correctly shifted by 180 degrees, so it appears that the R address generation part does not reset the R address, but in practice it does not. There is. It should be noted that the lack of data read out at time t _2, is no overlap.

Next, the structure shown in FIG. 4 is the reverse of the structure shown in FIG. 2 (a). That is, the input data containing the synchronization signal written in the memory 11 is used as the R address generation part.
The R address generated at 52 is used for reading, but when the sync signal detecting section 42 detects a sync signal in the read data, it sends a sync detection signal to the load timing generating section 32. Therefore, the load timing generation part sends the write load timing to the W address generation part 22 in the same way as above, and therefore this generation part 22 uses the R address and the write load timing to generate an address such that the W bit is not lost. Memory and set this address as the W address.
Send to 11.

[0030]

As described in detail above, according to the present invention, it is possible to prevent the loss of read data.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a first present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention, (a) is a configuration diagram, and (b) is a TDMA signal explanatory diagram.

FIG. 3 is an operation explanatory diagram of FIG. 2;

FIG. 4 is a configuration diagram of a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional example.

[Explanation of symbols]

1 memory means 2 write address generating means 3 synchronization signal detecting means 4 load timing generating means 5 read address generating means

Claims (2)

[Claims] 1. A write address generating means (2) for generating a write address, and a memory means (1) for writing input data including a synchronization signal to the applied write address and reading the data from the applied read address. In the elastic memory circuit having, a sync signal detecting means (3) for sending a sync detection signal when the sync signal in the input data is detected, and the input sync detection signal is inputted by using a read clock. Load timing generating means for transmitting as read load timing after delaying by (1/2) of the number of write addresses from the time point
(4) and the read address to be sent to the memory means as a read address, which is an address obtained by adding (1/2) of the number of write addresses to the write address at the time when the read load timing is applied among the input write addresses An elastic memory circuit provided with a generating means (5). 2. In the elastic memory circuit, when a sync signal in read data is detected, a sync signal detecting means (42) for sending a sync detection signal, and the input sync detection signal are written using a write clock. After a delay of (1/2) of the number of read addresses from the input time, the load timing generating means (3
2) and a write address to be sent to the memory means as an address obtained by adding (1/2) of the read address number to the read address at the time when the write load timing is applied An elastic memory circuit provided with a generating means (22).