JPH0762822B2 - Display controller - Google Patents

Description

The present invention relates to a display control technique and a technique particularly effective when applied to a control system for a display device such as a CRT display device, for example, a personal computer. Technology effective for display control method in CRT controller used in advanced graphic display system.

[Prior Art] A graphic display system equipped with a CRT display device has a CPU (microprocessor) as shown in FIG. 9, for example.
1 and the display data is formed based on the commands from the main memory 2 and the CPU 1 and drawn on the image memory 3 called a frame buffer, or the display data is read from the image memory 3 to display the screen of the CRT display device 4. It is composed of a CRT controller 5 having a function of displaying above. In this case, the frame buffer 3
As shown in FIG. 10, it often has a larger image storage area than the display screen of the CRT display device 4. Then, based on the address set in the start address register which is provided inside the CRT controller and indicates the display start position, the desired one screen of data in the frame buffer is read and displayed. Reference numerals 6 and 7 are buses, and 8 is a parallel-serial conversion circuit that converts parallel data read from the image memory 3 into serial data and supplies the serial data to the CRT display device 4 in synchronization with a synchronization signal SYNC from the CRT controller 5. Is.

As such a CRT controller, there is an LSI such as HD63484 manufactured by Hitachi, Ltd., for example.

[Problems to be Solved by the Invention] In the conventional CRT controller, the start address is set to the start address register indicating the display start position by a method in which the CPU directly writes to the start address register. ] Hitachi, Showa
Published in June 1984, "HD63484ACRTC (Advanced CRT Control
ler) User's Manual ").

Therefore, for example, when displaying moving images such as animation or flight simulation by drawing and switching between multiple screen data while displaying them, the CPU can be used after the drawing process in the CRT controller is completed.
It was necessary to rewrite the start address register by. As a result, the CPU must be involved in each screen switching control. In this case, since it is difficult for the CPU to know when the drawing of one screen is finished again, there is a disadvantage that the overhead of the CPU is large and the screen switching becomes slow.

An object of the present invention is to reduce the overhead of the CPU in the case of switching and displaying while drawing a plurality of screens and to improve the switching speed of the display screens.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

That is, a command for switching the address by the start address register that specifies the display start position is prepared, and the CRT controller interprets this command and outputs the display start address given by the CPU in the form of a parameter after drawing. It is provided with the function of promptly writing to the start address register to change the start address and switching the screen.

[Operation] According to the above means, a command for switching the display screen is inserted between the drawing command and the drawing command in advance, and the command is changed to CP.
When the display is switched from U to CRT controller, the start address register is automatically changed without CPU involvement when the drawing of a certain screen is finished, so that multiple screens can be switched and displayed. It is possible to achieve the above-mentioned object of reducing the CPU overhead in and reducing the display screen switching speed.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the overall configuration of a CRT controller LSI to which the present invention is applied.

Although not particularly limited, each circuit block surrounded by an alternate long and short dash line C in the drawing is formed on one semiconductor chip such as a single crystal silicon substrate.

The CRT controller LSI of this embodiment is roughly divided into
A processor unit 1 having a drawing function and a control function for the entire LSI
0, a display control unit 20 having a function of reading display data from the image memory, and a timing control circuit that forms a timing signal inside the LSI and a synchronization signal for the CRT display device.
It is composed of 30 and.

This CRT controller is connected to a CPU (central processing unit) as shown in FIG. 9 by a system data bus 6, and commands and parameters supplied from the CPU are
The data is supplied from the system data bus 6 to the processor unit 10 via a FIFO (first in first out) buffer 40. A frame buffer as shown in FIG. 9 is connected to the CRT controller via the frame address / data bus 7.

The processor unit 10 includes a command register 11 for receiving a command from the CPU via the FIFO 40, a decoder 12 for decoding the command fetched in the command register 11, and a CPU.
Execution unit consisting of micro ROM (read-on memory) 13 in which micro programs for forming various control signals for executing commands corresponding to commands from are stored, and ALU (arithmetic logic unit) and various registers
It is composed of 14 and.

The processor unit 10 decodes commands from the CPU 12
To generate a micro address of the micro ROM 13. As a result, the corresponding series of microinstructions are read out. The execution unit 14 is sequentially controlled by the read microinstruction group, and drawing data and drawing address for an external frame buffer formed as a result are supplied to the frame buffer.

Further, in the CRT controller of this embodiment, the processor unit 10 also forms a control signal for the display control circuit 20 and the timing control circuit 30 by the micro instruction read from the micro ROM 13. That is, not only the drawing function for the frame buffer but also the control of the entire controller is performed.

Further, the CRT controller of this embodiment is configured to switch the display screen in the CRT display device by a command given in advance from the CPU.

A first embodiment of the display control circuit 20 which enables the switching of the screen by such a command is shown in FIG.

The display control circuit 20 of FIG. 2 has a start address register 21 in which a display start address is set, and a memory width register 22 in which data MW defining the memory width of the frame buffer is set. The display data held in the frame buffer is not particularly limited, but has a plurality of bits for one display pixel. The display data corresponding to each display raster on the display screen is stored in consecutive storage addresses of the frame buffer. The memory width data MW is made coincident with, for example, an interval of storage addresses where display data corresponding to one display raster on the frame buffer is stored. The memory width MW can be set in the register 22 by the CPU directly or by setting a dedicated command and executing the dedicated command. The memory width MW set in the memory width register 22 is directly supplied to the adder 23. In the start address register 21, the address data to be displayed in the frame buffer should be set. Display start address set in this start address register 21
SA is supplied to the adder 23 via the selector 24. Adder
The addition result in 23 is temporarily held in the temporary register 25 and then passed through the selector 26 to the address incrementer 27.
Is supplied to. The address incrementer 27 can display the first display raster, in other words,
The display start address SA in the start address register 21 can be directly supplied via the selector 26 so that address data to which the memory width data MW is not added can be set.

Further, the head address data held in the temporary register 25 can be supplied to the adder 23 again via the selector 24 so that the start address data corresponding to the second and subsequent display rasters can be formed. .

In the display control circuit 20 configured as described above, when the screen switching command is loaded in the command register 11, the output of the decoder 22 that decodes this command (or the microinstruction read from the micro ROM 23 by this) causes The display start address data SA that has been fetched in the FIFO buffer 40 together with the command as a parameter of the screen switching command is fetched in the start address register 21.

The display start address data SA fetched in the start address register 21 is initially the address incrementer.
Supplied directly to 27. The address data of the address incrementer 24 is incremented one after another and output as a display address. When the output of the address data for one raster of the screen is completed, the address data SA in the start address register 21 is supplied to the adder 23 together with the memory width data MW in the memory width register 22. As a result, the start address of the raster on the second line of the display screen is obtained. This address is held in the temporary register 25 and supplied to the address incrementer 27. By the same operation of the address incrementer 27 as described above, 2
The display address of the raster of the line is generated and output one after another. When the second line of the display screen is displayed, the selector
The address (the start address of the second row) held in the temporary register 25 by switching 24 is supplied to the adder 23. Then, the memory width data is added again here to obtain the head address of the raster of the third row.

By repeating the above operation, a display address for one screen is generated.

The adder 23, the address incrementer 27, etc. in the display control device 20 of the above embodiment are operated only while the enable signal E is supplied from the timing control circuit 30.

Further, the selectors 24 and 26 are switched by the display control circuit 20.

FIG. 3 shows the corresponding part in the timing control circuit 30 which forms the enable signal E.

In the timing control circuit 30, a horizontal synchronization counter 31 for counting the system clock CLK supplied from the outside is provided.
And a vertical synchronization counter 32 for counting the carry signal of the counter 31. These counters 31
And 32 are programmable counters. The count number of these counters can be set to any value by the CPU. by this,
For example, if the count values of counters 31 and 32 are m and n respectively,
An m × n timing space as shown in FIG. 4 is formed. Display screen A is called in this timing space. Therefore, in the timing control circuit 30 of FIG. 3, a register for setting the horizontal display start timing is provided.
33s, a register 33e for setting the display end timing in the horizontal direction, and registers 34s, 34e for setting the display start timing and the end timing in the horizontal direction, respectively.

Furthermore, the count value of the horizontal synchronization counter 31 and the register
A comparator 35a for comparing the value of 33s is provided.
When the count value of the counter 31 coincides with the horizontal display start timing, the flip-flop 36 is set. Further, a comparator 35b for comparing the count value of the counter 31 and the value of the register 33e is provided. When the count value of the counter 31 coincides with the horizontal display end timing, the above flip-flop
36 is reset. Output Q of this flip-flop 36
Is output as a horizontal display timing signal HDISP and supplied to a CRT display device or the like.

Further, the count value of the vertical synchronization counter 32 and the register 34
A comparator 37a for comparing the value of s is provided, and when the count value of the counter 32 coincides with the vertical display start timing, the flip-flop 38 is set. On the other hand, a comparator 37b for comparing the count value of the counter 32 and the value of the register 34e is provided, and when the count value of the counter 32 coincides with the vertical display start timing, the flip-flop 38 is reset. The output Q of the flip-flop 38 is output as the vertical display timing signal VDISP, and C
It is supplied to RT display devices.

Further, in this embodiment, the horizontal display timing HDISP
AND gate that ANDs vertical display timing VDISP
39 is provided, and the output of the AND gate 39 is supplied to the display control circuit 20 as the enable signal E. As a result, the enable signal E as shown in FIG. 5 is supplied to the display control circuit 20 only at the timing of displaying the screen A in the timing space of FIG. 4, and the display addresses for reading the image data regarding the screen A are successively read. Will be generated.

Further, the carry signal CRT of the vertical synchronization counter 32 is also supplied to the processor internal 10. The processor unit 10 knows that the scanning of one screen is completed by this signal, and can perform the processing such as fetching the next command from the FIFO buffer 40.

In the above embodiment, as shown in FIG. 6, a screen switching command CMc ₁ , which has display start addresses SAa, SAb as parameters between a series of drawing command groups CMa ₁ , CMb ₁ , CMa ₂ ,. The command group including CMc ₂ , ...
It is supplied from the CPU to the FIFO buffer 40 in advance. In this way, as soon as the drawing of one screen is completed, the screen switching command is loaded and the control according to the screen switching command is executed. Thus, according to the set of commands as shown in FIG. 6, when the drawing of the screen A is completed while the screen B is being displayed, the display is switched from the screen B to the screen A promptly, and the screen can be switched at high speed. And the CPU overhead will be significantly reduced.

In the above embodiment, the drawing of the screen during the drawing process is completed in a very short time, and the screen switching command is executed after the drawing is completed, so that the display screen up to that time is displayed for a very short time. Disappear.

Therefore, in the next embodiment, as shown in FIG. 7, a frame interval register 51 for designating a frame interval by setting the number of repetitions of the screen to be displayed in the display controller 20, A frame counter 52 for counting the carry signal CRY from the vertical synchronization counter 32 and a comparator 53 for comparing the count value of the frame counter 52 with the set value of the frame interval register 51 are provided. Further, although not particularly limited, a flip-flop 54 is provided which is set by the load signal LD2 of the display start address to the start address register 21 formed by decoding the above-mentioned screen switching command. While the flip-flop 54 is set, a wait signal WAIT for waiting the fetching of the next command into the command register 11 by the load signal indicated by the symbol LD1 in FIG. 2 is generated.

The flip-flop 54 is reset by the coincidence detection signal output from the comparator 53. As a result, the wait signal WAIT disappears and the fetching of the next command is executed. In other words, the frame counter 52 that counts the carry signal CRY output from the vertical synchronization counter 32 at the end of each frame starts counting when the output Q of the flip-flop 54, that is, the wait signal WAIT is changed to the high level, When the count value matches the setting value of the frame interval register 51, the output signal from the comparator 53 causes the flip-flop 54
Is reset and the wait signal WAIT is changed to low level.

As a result, in this embodiment, even if the drawing by the next drawing command started after the screen switching is completed in a very short time, the fetching of the next screen switching command is waited for a predetermined interval, so that a certain screen The display period does not become extremely short.

FIG. 8 shows another embodiment of the present invention.

The display control circuit 20 of this embodiment is provided with four start address registers 21a, 21b, 21c and 21d for setting the start address of the image data of one screen to be displayed.
The display start address of any of the start address registers 21a to 21d is selected by the multiplexer and can be supplied to the adder 23 via the selector 24. The selection of the display start address by the multiplexer 28 is performed by, for example, the command register from the FIFO buffer 40.
It is performed by a signal formed by decoding a part of the code of the screen switching command loaded in 11.

Further, the CPU can directly set the display start address in each of the start address registers 21a to 21d via the FIFO buffer 40. The configuration other than the start address registers 21a to 21d and the multiplexer 28 is the same as that of the embodiment shown in FIG.

With such a structure, the same operation and effect as those of the embodiment shown in FIG. 2 can be obtained.

As described above, in the above embodiment, the address switching by the start address register that specifies the display start position is prepared as a command of the CRT controller, and the CRT controller decodes this command and forms the parameter form. Since the display start address given by the CPU is set in the start address register immediately after the drawing is finished and the start address is changed to perform display, the drawing command and drawing command can be changed in advance. Enter the command for switching the display screen
When the drawing of a certain screen is completed, the start address register is automatically changed without the involvement of the CPU. The CPU overhead is reduced and the display screen switching speed is improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, the display control circuit of the above embodiment is provided with the micro ROM itself in which the micro program is stored and the execution unit under its control, and decodes the screen switching command fetched from the FIFO buffer in the display control circuit. Thus, it is possible to cause the execution unit to perform the same processing as the change of the display start address and the generation of the display address based on the change in the display start address in the above embodiment. Conventionally, Hitachi Ltd. HD
In the CRT controller such as 63484, the display control unit is configured by the hardware of the micro program control system as described above. Therefore, in such a CRT controller, the present invention can be realized only by changing the microprogram in the display control unit so that the above-mentioned screen switching command can be executed without changing the hardware.

[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in a graphic display system including a CPU, a CRT display device, and a CRT controller, it is possible to reduce CPU overhead when performing display control such that display screens are switched one after another while drawing. As a result, the processing speed of moving images such as animation and flight simulation can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a CRT controller having a drawing function, and FIG. 2 is a block diagram showing a configuration example of a main part of a display control circuit therein. FIG. 3 is a block diagram showing a configuration example of a timing control circuit, FIG. 4 is an explanatory diagram showing a relationship between a display screen and display timings in a horizontal direction and a vertical direction, and FIG. 5 is formed by the timing control circuit. 6 is a timing chart of control signals according to the present invention, FIG. 6 is a flow chart showing an example of the flow of commands processed by the CRT controller, FIG. 7 is a block diagram showing another embodiment of the present invention, and FIG. FIG. 9 is a block diagram showing still another embodiment of the present invention, FIG. 9 is a block diagram showing a structural example of the graphic display system, and FIG. 10 is a memory map showing the positional relationship of display screens in the frame buffer. 1 ... CPU (central processing unit), 2 ... main memory, 3
...... Frame buffer (image memory), 4 ... CRT display device, 5 ... CRT controller, 10 ... Processor section, 1
1 …… Command register, 13 …… Micro ROM, 20 …… Display control circuit, 21 …… Start address register, 33s, 33
e, 34s, 34e …… Display timing setting register.

Claims (4)

[Claims] 1. A FIFO buffer, which is formed on one semiconductor chip and can previously store and hold a plurality of commands supplied from an external microprocessor, and a display device based on the drawing commands stored in the FIFO buffer. A drawing control circuit for forming image data to be displayed on the screen and forming a signal for writing to an external image memory; and a drawing control circuit in the image memory corresponding to the size of the display screen of the display device. A display control device having a display control circuit for forming a signal for reading and outputting image data, wherein the display control circuit has a register for designating a start address of an image data group to be displayed in the image memory. Then
Set the above start address for this register to the above
It is configured to be executed by the screen switching command read from the FIFO buffer and its accompanying parameter, and when the drawing command, the screen switching command and the display start address are fetched into the FIFO buffer, the drawing control is performed. After the circuit executes the drawing process according to the drawing command, the display control circuit is configured to read the display image data group based on the display start address and automatically switch the display screen. A display control device characterized by. 2. A plurality of registers for designating a start address of an image data group to be displayed in the image memory are provided, and the selection of the addresses in these registers decodes a screen switching command read from the FIFO buffer. The display control device according to claim 1, wherein the display control device is configured to be executed by executing the command or by specifying a parameter of the command. 3. The display device according to claim 1, wherein display is started by the start address set in the register and fetching of the next command is not executed until the end of one screen is reached. The display control device according to item 2 or item 3. 4. A display count register is provided for setting the number of times the screen designated by the start address set in the register is to be displayed, and the number of times the image data in the image memory is read is set in the display count register. Claim 1 is characterized in that the fetching of the next command is not executed until the number of times is reached.
The display control device according to item 2 or item 3.