JPH0765092A - Element for neural network - Google Patents

Abstract

(57) [Abstract] [Purpose] High-speed, adaptable to the backpropagation model in neural network theory and capable of high integration.
A small nerve gyrus element is provided. [Structure] The device comprises a semiconductor part and a superconductor part. The semiconductor portion includes a Schottky gate electrode 1 for applying a voltage for controlling a current flowing into the superconductor portion, a synapse region 2 having a high mobility two-dimensional electron gas layer therebelow, and a Schottky gate electrode 1. A quasi-one-dimensional channel region 3 whose resistance value changes according to the voltage applied to it, a current coupling region 4 for allowing a current from the quasi-one-dimensional channel region 3 to flow into the superconductor portion 6, and a synapse region for an external input. A plurality of units composed of synapse electrodes 5 applied to 2 are arranged in a substantially annular shape around the superconductor portion 6. The input side of the superconductor portion 6 is coupled to the current coupling region 4 via the heavily doped region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neural network element, and more particularly to a neural network element which is a unit constituting a neural network of a neurocomputer.

In recent years, with the progress of computer technology, a neuro computer has been attracting attention as a non-Neumann type computer which has the advantage that parallel processing for speeding up becomes possible. There is a method of configuring a computer by using a neural network as a method of realizing this neurocomputer in hardware. The neural network is a network imitating the human brain, and is constructed by complexly connecting a plurality of neural network elements corresponding to the neurons in the brain. Therefore, in order to speed up and downsize the entire network, it is necessary to speed up the neural network element which is a component thereof and further downsize it by high integration.

[0003]

2. Description of the Related Art A back propagation model is a typical model expressing a neural network. According to this model, the neural network elements that make up the neural network are
The requirements must meet the following two points.

1) Multiple inputs are individually weighted, and at least one output is obtained based on the weighted result. 2) An output is obtained when the sum of inputs exceeds a certain threshold.

Conventionally, as an element for satisfying the above requirements, a VL mainly utilizing a CMOS LSI is used.
There are SI neurochips and optical nerve circuit elements that apply optical technology.

[0006]

However, in the semiconductor device having the CMOS structure of the prior art, carrier mobility and miniaturization are limited due to the structure, and one neural circuit device is formed. In order to do so, a plurality of LSIs are required. Therefore, there is a limit in terms of integration and miniaturization.

Further, in the case of the optical nerve circuit element, it is necessary to form an optical path in the circuit, which causes a problem in miniaturization. An object of the present invention is to provide a high-speed and small-sized neural network element that can be adapted to a back propagation model and can be highly integrated.

[0008]

In order to solve the above problems, the present invention provides a Schottky gate electrode 1, a Sipnus region 2, a quasi-one-dimensional channel region 3 and a current coupling as shown in FIG. 1, for example. A region 4 and a Sipnus electrode 5, which individually weight multiple inputs and make the total sum flow into the superconductor part, and a constant value when the total input flow exceeds a certain threshold value. Superconductor part 6 to obtain the output of
And, and is configured.

[0009]

The operation of the present invention will be described with reference to FIG. The input from the outside is applied to the synaptic electrode 5. The synapse electrode 5 is formed on the synapse region 2 having a two-dimensional electron gas layer below which the electrons can move only in a plane with high mobility, and the voltage applied to the synapse electrode 5 remains as it is. 2 is applied to the underlying two-dimensional electron gas layer. Then, a current corresponding to the resistance value of the pseudo one-dimensional channel region 3 flows into the pseudo one-dimensional channel region 3 through the two-dimensional electron gas layer.

Here, the Schottky gate electrode 1 has
A constant voltage is applied in advance to control the current that passes through the pseudo one-dimensional channel region 3 and flows into the current coupling region 4. Due to this voltage, the two-dimensional electron gas layer below the Schottky gate electrode 1 becomes a depletion layer, and the movement of electrons in the two-dimensional electron gas layer is suppressed. As a result, the electrical resistance value of the pseudo one-dimensional channel region 3 changes, and the current flowing into the pseudo one-dimensional channel region 3 is controlled. With the above operation, weighting is applied to the input from the outside.

Next, the current passing through the pseudo one-dimensional channel region 3 flows into the current coupling region 4. Current coupling area 4
, The superconductor part 6 that is initially in a superconducting state is synthesized with the electric current that has passed through another quasi-one-dimensional channel region.
Applied to. When the sum of the inflowing currents exceeds a certain value (hereinafter referred to as a threshold value) determined by the kind of the constituent material of the superconductor portion 6, the superconducting phenomenon disappears and the superconductor portion 6 A voltage determined by the type of constituent material is generated as an output at the end of the superconductor portion 6 which is not coupled to the semiconductor portion. With the above operation, the function of obtaining a constant output is realized when the total sum of the inflowing inputs exceeds a certain threshold value.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described with reference to the drawings. FIG. 2 shows a plan view of the embodiment having five synapse electrodes.

In FIG. 2, Schottky gate electrodes 120, 122, 124, 126, 128 for applying a voltage for controlling a current flowing into the superconductor portion are substantially annular around the superconductor portion 132. Are arranged at regular intervals. The gaps between the Schottky gate electrodes are pseudo one-dimensional channel regions 110, 112, 114, 116, and 1.
18, the pseudo one-dimensional channel regions 110, 112,
The outside of 114, 116, 118 is the synapse region 101,
103, 105, 107, 109, and the inside of the pseudo one-dimensional channel regions 110, 112, 114, 116, 118 becomes the current coupling region 134.

Further, the synapse electrodes 100, 102, 10
4, 106 and 108 are synaptic regions 101 and 101, respectively.
One for each of 103, 105, 107, and 109.

Further, the two-dimensional electron gas layer in which electrons can move only in a plane with high mobility is a quasi-one-dimensional channel region 1
10, 112, 114, 116, 118, the synapse regions 101, 103, 105, 107, 109, the current coupling region 134, and the superconductor part 132 are continuously formed below the parts.

Next, a sectional view taken along line X1-X2 in FIG. 2 will be described with reference to FIG. In FIG. 3, semi-insulating-G
Substrate 60 made of aAs, undoped-GaAs
Layer 62 made of Al, undoped-AlGa
Spacer layer 64 made of As and N-type-AlGaA
An electron supply layer 66 made of s is stacked. Further, the Schottky gate electrode 12 is formed on the electron supply layer 66.
2, 126 and a contact layer 68 made of n ⁺ -type GaAs are formed, synapse electrodes 100 and 106 and a superconductor portion 132 are formed on the contact layer 68, and an insulating layer 140 is formed on the uppermost portion. The lead 130 is formed.

Further, the superconductor portion 132 is composed of the Nb layer 160,
The Al layer 161, the AlO _x layer 162, and the Nb layer 163 are laminated, and the Nb layer 163 is connected to the lead 130.
The two-dimensional electron gas layer 70 has the Schottky gate electrode 12
When a voltage is applied to 2,126, the voltage is distributed in a plane except the lower part.

The lower portion of the superconductor portion 132 is a highly-doped region 164, and the two-dimensional electron gas layer 70 and the superconductor portion 132 are ohmic-bonded to each other. Furthermore, the lower parts of the synaptic electrodes 100, 106 are alloyed,
The synaptic electrodes 100 and 106 and the two-dimensional electron gas layer 70 are ohmic-bonded.

Next, the operation will be described. Here, in order to simplify the description, the synapse electrode 100 and the synapse region 10 are shown.
1, a unit including the quasi-one-dimensional channel region 110, the Schottky gate electrodes 120 and 122, and the current coupling region 134 will be described.

Input from the outside is applied to the two-dimensional electron gas layer 70 below the synapse region 101 via the synapse electrode 100. Then, a current corresponding to the resistance value of the pseudo one-dimensional channel region 110 flows into the pseudo one-dimensional channel region 110. Here, a constant voltage is applied to the Schottky gate electrodes 120 and 122 in advance in order to control the current that passes through the pseudo one-dimensional channel region 110 and flows into the current coupling region 134. The two-dimensional electron gas layer 70 under the Schottky gate electrodes 120 and 122 becomes a depletion layer according to this voltage, and the two-dimensional electron gas layer 7
The movement of electrons in 0 is suppressed. As a result, the electrical resistance value of the pseudo one-dimensional channel region 110 changes, and the current flowing into the pseudo one-dimensional channel region 110 is controlled. With the above operation, the external input is weighted according to the voltage applied to the Schottky gate electrode.

Regarding the above operation, the synapse electrode 10
2, synapse area 103, quasi-one-dimensional channel area 11
2, a unit composed of Schottky gate electrodes 122 and 124 and a current coupling region 134, a synapse electrode 104,
Synapse region 105, quasi-one-dimensional channel region 114,
A unit including the Schottky gate electrodes 124 and 126 and the current coupling region 134, the synapse electrode 106, the synapse region 107, the pseudo one-dimensional channel region 116, the Schottky gate electrodes 126 and 128, and the current coupling region 1.
34, a synapse electrode 108, a synapse region 109, a pseudo one-dimensional channel region 118, Schottky gate electrodes 128 and 120, and a current coupling region 134.
The same applies to each of the units consisting of.

Next, the pseudo one-dimensional channel regions 110, 1
The current that has passed through 12, 114, 116, and 118 flows into the current coupling region 134. The currents flowing from the respective quasi-one-dimensional channel regions are combined in the current coupling region 134 and concentrated in the lower part of the superconductor portion 132. The superconductor portion 132 is initially in a superconducting state, and no voltage is generated on the lead 130. Here, when the total of the currents concentrated in the superconductor portion 132 exceeds a threshold value (equal to the critical current of the superconductor portion 132), the superconducting phenomenon disappears and the lead 13 is formed.
A voltage (critical voltage of the superconductor portion 132) is generated at 0. With the above operation, the function of obtaining a constant output is realized when the total sum of the inflowing inputs exceeds a certain threshold value.

In FIG. 4, the Schottky gate electrode 120,
Synapse electrodes 100, 102, 104, 106 when a constant voltage is applied to 122, 124, 126, 128,
An example of the relationship between the voltage of 108 and the output voltage is shown.

FIG. 4A shows a state in which the output voltage at the lead 130 is 0 mV. That is, the Schottky gate electrodes 120, 122, 124, 126, 128.
The electrical resistance value of each quasi-one-dimensional channel region changes according to the voltage applied to the synaptic electrode 10.
The current flowing from 0, 102, 104, 106, 108 into each quasi-one-dimensional channel region is controlled and weighted. Thereafter, the weighted current passes through each quasi-one-dimensional channel region and concentrates in the current coupling region 134. However, since the sum of the currents does not exceed the threshold value, the superconducting state of the superconductor portion 132 is It is maintained and no voltage is generated on the lead 130.

FIG. 4B shows a state in which an output voltage is generated on the lead 130. That is, the electrical resistance value of each quasi-one-dimensional channel region changes according to the voltage applied to the Schottky gate electrodes 120, 122, 124, 126, 128, which causes the synapse electrode 100,
The current flowing into each quasi-one-dimensional channel region from 102, 104, 106, 108 is controlled and weighted.
Then, the weighted current passes through each quasi-one-dimensional channel region and concentrates in the current coupling region 134, and the total of the currents exceeds the threshold, so that the superconducting state of the superconductor portion 132 disappears. However, a voltage is generated on the lead 130.

With the above operation, a function necessary as a neural circuit element, that is, at least one output is provided for a large number of individually weighted inputs, and the sum of the weighted inputs is a threshold value. It can be seen that it has a function that its output is obtained when it exceeds.

According to this embodiment, since all the functions as a neural circuit device can be realized by one device, the neural network can be highly integrated and miniaturized, and the high electron mobility can be realized. Since the three-dimensional electron gas layer is used, the speed can be increased.

[0028]

According to the present invention, since a semiconductor device capable of high integration can be used to realize all the functions as a device for a neural network by one device, the highly integrated neural network can be achieved. It can be miniaturized and downsized. Furthermore, since a two-dimensional electron gas layer with high electron mobility is used, a high speed neural network device can be realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the principle of the present invention.

FIG. 2 is a plan view showing an embodiment of the present invention.

3 is a diagram showing a cross section taken along line X1-X2 in FIG.

FIG. 4 is a diagram showing an operation status of the embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Schottky gate electrode 2 ... Synapse region 3 ... Pseudo one-dimensional channel region 4 ... Current coupling region 5 ... Synapse electrode 6 ... Superconductor part 60 ... Semi-insulating-GaAs substrate 62 ... Undoped-GaAs channel layer 64 ... Undoped -AlGaAs spacer layer 66 ... N-type-AlGaAs electron supply layer 68 ... n ⁺ -type-GaAs contact layer 70 ... Two-dimensional electron gas layer 100, 102, 104, 106, 108 ... Synapse electrode 101, 103, 105, 107, 109 ... Synapse region 110, 112, 114, 116, 118 ... Pseudo one-dimensional channel region 120, 122, 124, 126, 128 ... Schottky gate electrode 130 ... Lead 132 ... Superconductor part 134 ... Current coupling region 140 ... Insulating layer 160 ... Nb layer 161 ... Al layer 162 ... AlO _X layer 63 ... Nb layer 164 ... heavily doped regions

Claims (3)

[Claims] 1. A neural network having at least one output for a number of individually weighted inputs, the output of which is obtained when the sum of the weighted inputs exceeds a certain threshold. In the device, a large number of inputs are individually weighted, and the total sum of the inputs that flow into the superconductor part (1, 2, 3, 4, 5) exceeds a certain threshold. An element for a neural network, comprising: a superconductor portion (6) that obtains a constant output when 2. The semiconductor section (1, 2,
3, 4, 5) are Schottky gate electrodes (1) for applying a voltage for controlling a current flowing into the superconductor portion.
And a synapse region (2) having a two-dimensional electron gas layer having a high electron mobility in the lower portion and the two-dimensional electron gas layer in the lower portion, and having a resistance value depending on a voltage applied to the Schottky gate electrode (1). Quasi-one-dimensional channel region with variable (3)
And a current coupling region (4) having the above-mentioned two-dimensional electron gas layer in the lower part and allowing a current from the quasi-one-dimensional channel region (3) to flow into the superconductor part (6), and a synapse of an external input. A plurality of units composed of a synapse electrode (5) applied to the region (2) are arranged in a substantially annular shape around the superconductor portion (6) having the two-dimensional electron gas layer in the lower part. A neural network element characterized by the above. 3. A neural network characterized in that the input side of the superconductor part (6) according to claim 1 or 2 is coupled to the current coupling region (4) via a heavily doped region. Element.