JPH076580A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To realize a nipple mode by the use of two pairs of data buses by constituting of two pairs of precharge signal generation means, two pairs of data buses, opening/closing means of N pairs of bit lines alternately connected to the data buses and a pair of data bus selection means, etc. CONSTITUTION:A semiconductor storage circuit is constituted of two pairs of precharge signal generation means Q1-Q4, two pairs of data buses 15 and anti 15', 16 and anti 16', N=four pairs, etc., of bit lines 11, anti 11' to 14, anti 14' connected to these buses alternately, the opening/closing means Q5-Q12 of these lines, two pieces of amplifier means C1, C2 connected to the buses 15 and anti 15', 16 and anti 16' and a pair of selection means Q13, Q20, etc., of data buses. By such a constitution, the number of data buses where the data buses are shared in time division at the time of read, write cycle by one time address designation are reduced, and the nipple mode of N=4 bits, etc., is realized, and the semiconductor storage circuit with high integration is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit, and more particularly to a semiconductor memory circuit which can realize data reading or writing at high speed.

[0002]

2. Description of the Related Art Some semiconductor memory devices employ a nibble mode function because of the necessity of high-speed reading or high-speed writing in large-capacity memory (for example,
"A100ns 256K DRAM with Pa
ge-Nibble Mode "ISSCC 83 D
IGEST OF TECHNICAL PAPERS
pp228-229).

Here, the nibble mode is a function for speeding up reading and writing of the memory as a whole by continuously transmitting Nbit (normally 4 bit) information by addressing once and fetching or writing the information from the memory cell. Say.

A conventional circuit configuration example for realizing the nibble mode is described in the above-mentioned document (ISSCC83 DIGEST).
OF TECHNICAL PAPERS p22
9) and Japanese Patent Publication No. 55-40956.

That is, the circuit structure of the conventional nibble mode is
N bit in read mode and N in nibble mode
Data is taken out from N-bit bit lines by a pair of data buses, the width of the data is increased, and then the data of each pair is sequentially read to the output. In the write mode, N-bit data is serially read from the read terminal, and N-bit data is transferred to N pairs of data buses,
Writing is sequentially performed on N memory cells from the N pairs of bit lines through the opening / closing means of the N pairs of bit lines.

[0006]

However, in the conventional nibble mode circuit system, the number of logarithms of the data bus is N in the nibble mode of N bits. Further, since there are N pairs of data buses, it is necessary to provide N sub-amplifiers, write buffers, and N signal data pre-charged signal generation circuits.

[0007] Then, these cause a problem of increasing the size of the semiconductor chip.

An object of the present invention is to provide a semiconductor memory circuit which can realize an N-bit nibble mode by two pairs of data buses in order to solve the above problems.

[0009]

According to the present invention, there are provided two pairs of precharge signal generating means, two pairs of data buses, N pairs of bit line opening / closing means alternately connected to the data buses, and the data. It consists of two amplification means connected to the bus and a pair of data bus selection means. By controlling precharge signal generation, opening / closing of N pairs of bit lines, and selection of data bus, N bits are selected. In a semiconductor memory circuit for sequentially reading or writing information.

[0010]

According to the structure of the present invention, since the data buses can be shared in a time division manner in the read and write cycles in one address designation, the number of data buses can be reduced, and the semiconductor memory circuit can be reduced. Can be integrated.

[0011]

Embodiments of the present invention will be described in detail below.

FIG. 1 is a circuit diagram of a nibble mode showing an embodiment of the present invention. There are sense amplifiers A1 to A4 and their associated bit line pairs l1, bars l1, l2, bars l2, l3, bars l3, l4 and bar l4. A large number of memory cells are connected to the bit line pair via transistors opened and closed by word lines. Bit line l1 and bar l1 amplified by the sense amplifier A1
Bit line switching means transistors Q5, Q6 for transferring the above information to the first data bus 15 and bar 15
And the bit line 12, which is amplified by the sense amplifier A2
Bit line switching means transistor Q for transferring the information on the bar 12 to the second data bus 16 and bar 16
7 and Q8 and the information on the bit line 13 and bar 13 amplified by the sense amplifier A3 are transferred to the first data bus 15 and
Bit line switching means transistors Q9 and Q10 for transferring to the bar 15 and bits for transferring information on the bit lines 14 and 14 amplified by the sense amplifier A4 to the second data bus 16 and bar 16 There are line switching means transistors Q11 and Q12. A pair of precharge signal generation means transistors Q1 and Q2 for precharging the data bus 15 and bar 15 and a pair of precharge signal generation means transistors Q3 and Q4 for precharging the data bus 16 and bar 16. There is. Amplifying means sub-amplifier C1 for amplifying information on the data bus 15 and bar 15 and the data bus 16 and bar 15
There is an amplification means sub-amplifier C2 for amplifying the information of No. 6 in FIG. Transistors Q13 and Q14 for transferring information on the data bus 15 and bar 15 to the output buffer E and transistors Q17 and Q18 for transferring information on the data bus 16 and bar 16 to the output buffer E are two pairs of data buses. A selecting means for selecting a pair of data buses is configured. The output buffer E for outputting the information on l7 and bar l7 transferred through the transistors Q13 and Q14 or the transistors Q17 and Q18 is connected to the output terminal DO. An input buffer D for inputting write information, transistors Q15, Q16 for transferring the output of the input buffer D to the write buffer B1, and transistors Q19, Q20 for transferring the output of the input buffer D to the write buffer B2. And constitutes a selecting means for selecting one pair of data buses from two pairs of data buses. The information output from the input buffer D is amplified, and the data bus l
5, write buffer B1 for transfer to bar 15,
A write buffer B2 for amplifying the information output from the input buffer D and transferring it to the data bus 16 and the bar 16
There is. In the write cycle, the bit line switching means transistors Q5 and Q6 transfer the write information transferred from the write buffer B1 to the data bus 15 and bar 15 to the bit line 11 and bar 11 and the transistors Q7 and Q8 from the write buffer B2. Data bus 16,
The write information transferred to the bar l6 is transferred to the bit line l
2, transfer to the bar 12 and the transistors Q9 and Q10 are
The write information transferred from the write buffer B1 to the data bus 15 and bar 15 is transferred to the bit lines 13 and 13 and the transfer gates Q11 and Q12 transfer the write information transferred from the write buffer B2 to the data bus 16 and bar 16. It serves to transfer to bit line 14 and bar 14.

FIG. 2 is a timing chart of a read cycle of the nibble mode circuit shown in FIG. 1, and FIG.
Similarly, it is a timing diagram of a write cycle of the circuit shown in FIG.

First, the circuit operation of the circuit according to the present invention for the read cycle will be described with reference to FIG. Here, it is assumed that the head bit designated by the address in the 4 bits of the nibble mode read information is the information on the bit lines l1 and bar 11 amplified by the sense amplifier A1, and the sense amplifiers are sequentially processed according to the cycle of CAS. A
It is assumed that the information amplified by 1, A2, A3 and A4 is read out as the waveforms a, b, c and d indicated by DO. In reality, no matter which sense amplifier the head bit information was amplified by, the control signal changes according to each case, and the mechanism similar to the circuit operation described below starts from the head bit for which nibble reading is designated as usual. Can be realized by Write buffer B1 during the read cycle
And B2 are reset and do not operate.

(1) Between times t1 and t2, φ1 and φ2 are at high level, and transistors Q1, Q2 and Q3, Q
Since 4 is on, the data buses 15, bar 15 and 15 and bar 16 are precharged. That is, the two pairs of data buses are precharged by the precharge signal generating means. Φ after the first fall of bar CAS
Both 1 and φ2 become low level at time t2. afterwards,
φ3 and φ4 become high level, and transistors Q5 and Q6
And Q7 and Q8 are turned on. That is, the bit lines l1,
The bars 11, 12 and 12 open. Note that φ3 and φ4 become high level in synchronization with the first bar CAS falling cycle. At this time, the sense amplifiers A1 to A4 have finished or are amplifying the information on each bit line. The information on the bit line 11 and the bar 11 passes through the transistors Q5 and Q6 and the data bus 15 and
The information transferred to the bit line 15 and transmitted on the bit line 12 and the bar line 12 passes through the transistors Q7 and Q8 and the data bus l.
6, transferred to bar 16. Considering the circuit corresponding to FIG. 1 by the conventional method, four pairs of data buses are required, but in the present invention, two pairs of data buses are used in a time division manner.
Therefore, the signals φ3 to φ6 for controlling the opening / closing between the bit lines and the data bus are always set to the high level or the low level at the timing when the information on the pair of bit lines is transferred to the pair of data buses. It is necessary to. Therefore, when φ3 and φ4 are high level and the information on the bit line l1, bar l1 and l2, bar l2 is transferred to the data bus l5, bar l5 and l6, bar l6, φ5 and φ6 are low level and the bit line is The opening / closing means is closed, and the information on the bit lines 13 and 13 and the bit lines 14 and 14 is not transferred. In addition, φ3
Towards the level of ~φ6 is that the level is boosted to V _DD or more potential, the on-resistance small next to the transistor Q5～Q12, expected high-speed transfer is desirable. Even in the write cycle, φ3 to φ6 are preferably set to a level higher than V _DD + V _T in order to write the V _DD level to the memory cell. During the first low level cycle of CAS, the information transferred to the data bus is amplified by the amplification means sub-amplifiers C1 and C2. At this time, φ7 has already been set to a high level, and transistor Q1
3 and Q14 are turned on, the information of the data bus l5 and bar l5 amplified by the sub-amplifier C1 is l7 and bar l.
7, and the information is output from the output buffer E as shown by the waveform a of DO. On the other hand, at the same time as this, the data bus 16 and the bar 16 amplified by the sub-amplifier C2.
Information is set to φ7 by changing φ8 to a low level.
It is not transferred to the data bus 7, but is waiting on the data bus until it is transferred to the output buffer E and output in synchronization with the low level cycle of the second CAS. In order to realize the high-speed serial access, which is a characteristic of the nibble mode read, since the bit line information needs to be transferred to the data bus at least during the bar CAS cycle which is one cycle before, φ3 and φ4 are The high level must be synchronized with the low level cycle of the first bar CAS. φ7 and φ8 are transistors Q13, Q14 and Q1
It is desirable that the signal is boosted to a level of V _DD or higher in order to reduce the on resistance of Q7 and Q18 to speed up the operation.
Especially the data bus 15, bar 15 or 16 or bar 16
1, 17 and bar 17 need not be transistors as shown in FIG. 1 as long as the circuit has a function of transferring information by the signals of the functions corresponding to φ7 and φ8.

(2) Between times t3 and t4, the bar CAS
Is set to a high level and the sub-amplifier C1 is reset. This is a preparation for amplification when the information on the bit lines 13 and 13 is transferred to the data bus 15 and 15 in the next low cycle of the bar CAS.
At approximately the same time as this, φ3 is set to the low level, the transistors Q5 and Q6 are turned off, the bit line opening / closing means is closed, and the bit lines 11 and 11 are disconnected from the data buses 15 and 15.

After that, φ1 becomes high level, the transistors Q1 and Q2 of the precharge signal generating means are turned on, and the data bus 15 and bar 15 are precharged to transfer information on the next bit line 13 and bar 13. Provide. At the same time, the sub-amplifier C2 is still amplifying the information on the data bus 16 and bar 16 and
It will not be reset.

(3) φ1 is set to the low level in synchronization with the time t4 when the bar CAS is set to the low level for the second time. After that, φ5 is set to the high level and the transistors Q9 and Q1 are
When 0 is turned on and the bit line is opened, the information on the bit line 13 and bar 13 is transferred to the data bus 15 and bar 15. The information transferred to the data bus 15 and the bar 15 is amplified by the amplification means sub-amplifier C1. This information is obtained by setting φ7 to a low level in this low level cycle of the second bar CAS l7, bar l7.
The data bus is not selected, that is, the data bus is not selected and is output in synchronization with the third low level cycle of the bar CAS. Therefore, the data bus 15 and the bar 15 are kept on standby while being amplified by the sub-amplifier C1. There is.

As described in (1), since the information to be output next is waiting on the data bus one cycle before the bar CAS low level cycle, the conventional high speed access in the nibble mode can be realized. . On the other hand, at the same time as this, in the first low-level cycle of the bar CAS, the information waiting while being amplified by the sub-amplifier C2 on the data bus 16 and the bar 16 is φ8 as a high level, When Q17 and Q18 are turned on, the second data bus is selected and transferred to l7 and bar l7,
Information is output from the output buffer as shown by the waveform b of DO.

The transfer from the data bus to l7 and the bar l7 is performed by the bar C after the first bar CAS low level cycle.
It is desirable to perform it while the AS is at a high level in consideration of high speed access.

(4) At time t5, the bar CAS is set to a high level and the amplification means sub-amplifier C2 is reset. φ4 is low level. After that, φ2 becomes high level and the data bus 16 and bar 16 are precharged. On the other hand, sub-amplifier C
1 is not reset, and the information amplified by the sub-amplifier on the data bus 15 and bar 15 is in the standby state. The operation of these circuits is the same as in (2).

(5) Third CA bar at time t6
In synchronization with the low-level cycle of S, the circuit operation similar to (3) outputs the information on the data bus 15 and bar 15 that was on standby in (4) as shown by the waveform c of DO. . In parallel with this, the information of the bit lines 14 and 14 is transferred to the data bus 16 and 16 by the same circuit operation as described in (4), and is output in the next cycle in which the CAS level becomes low. Data bus l
6, Wait on bar 16.

After that, the nibble mode can be read by repeating the cycle described in detail in (2) and (3). That is, as shown in FIG. 2DO, the bit line information is sequentially read as waveforms a, b, c and d. Similarly, when the bar CAS cycle is repeated 5 times or more,
(2) By repeating the cycle described in (3),
Information can be cyclically read as a, b, c, d, a, b ....

In the write cycle, four data can be sequentially written by the same circuit operation as the read cycle. That is, FIG. 3 shows a timing diagram of the write cycle in the nibble mode.

For writing to the bit line, the input information entering the serial of the terminal DI is input buffer E data bus selecting means (Q13 to Q20) write buffer B1 or B.
Opening / closing means for two or two pairs of data buses and bit lines (Q5
~ Q12).

Here, the hatched portion of DI in FIG. 3 indicates an invalid input portion, and e, f, g, and h indicate nibble write information. Writing can be realized by sharing the data bus in a time-sharing manner by controlling the control signals φ1 to φ8 at the timings shown in FIG. 3 as in the read cycle. The difference from the read cycle is that when write information is transferred to the data bus, the sub-amplifier attached to the data bus resets.

[0027]

As described above, according to the present invention, the number of data buses required in the conventional method is shared by time-sharing the data buses in the read and write cycles in one addressing in the nibble mode. Since the circuit can be realized in less than half of the above, the chip occupation area of the data bus can be reduced.

In particular, when the present invention is used in a nibble mode dynamic random access memory with multiple output pins when there is a limitation on the chip size when it is mounted in a package and an increase in the number of data buses poses a problem, it is smaller than the conventional method. This is effective because the device can be manufactured with dimensions.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing a read cycle of the circuit of FIG.

3 is a timing chart showing a write cycle of the circuit of FIG.

[Explanation of symbols]

 l1, bar l1 to l4, bar l4 bit line l5, bar l5 first data bus l6, bar l6 second data bus Q1 to Q20 transistors φ1 to φ8 control signals A1 to A4 sense amplifiers C1 and C2 subamplifiers B1 and B2 Write buffer D Input buffer E Output buffer

Claims (1)

[Claims] 1. A first to fourth memory cell, wherein the first to fourth memory cells each store data, and the first to which data is respectively supplied from the first to fourth memory cells. To a fourth bit line pair, a first and a second data line pair, and a first or second logic level connected between the first bit line pair and the first data line pair. A first switch circuit to which a first control signal is applied, wherein when the first control signal has the first logic level, the data applied to the first bit line pair is Transferring to a first data line pair and substantially disconnecting the first bit line pair and the first data line pair when the first control signal has the second logic level. The first switch circuit for A second switch circuit connected between the second pair of bit lines and the second pair of data lines, to which a second control signal having the first or second logic level is applied. , The second control signal has the first logic level, the data provided to the second bit line pair is transferred to the second data line pair, and the second control signal is transferred to the second data line pair. The second switch circuit for substantially disconnecting the second bit line pair and the second data line pair when having a second logic level; the third bit line pair; A third switch circuit connected between the first data line pair and receiving a third control signal having the first or second logic level, wherein the first control signal is the Has a second logic level When the third control signal has the first logic level, the data provided to the third bit line pair is transferred to the first data line pair, and the third control signal is transferred to the first data line pair. If you have 2 logic levels,
Between the third switch circuit for substantially disconnecting the third bit line pair and the first data line pair, and between the fourth bit line pair and the second data line pair. A fourth switch circuit connected to the first control signal and having a fourth control signal having the first or second logic level, wherein the second control signal has the second logic level, When the fourth control signal has the first logic level, the data applied to the fourth bit line pair is transferred to the second data line pair, and the fourth control signal is transferred to the second data line pair. If you have 2 logic levels,
The fourth switch circuit for substantially disconnecting the fourth bit line pair and the fourth data line pair, and the first and second data line pairs, the first switch circuit being connected to the first and second data line pairs, respectively. Alternatively, the output buffer circuit is provided with fifth and sixth control signals having a second logic level, wherein the first and fifth control signals have the first logic level and the third And a sixth control signal has the second logic level, the data given to the first data line from the first memory cell is output, and the second and sixth control signals are output. Data having a first logic level and the first, fourth and fifth control signals having the second logic level, the data provided from the second memory cell to the second data line. To output the third and fifth When the control signal has the first logic level and the first and sixth control signals have the second logic level, the third memory cell outputs the first signal.
Outputting the data given to the data line, the fourth and sixth control signals have the first logic level, and the second and fifth control signals have the second logic level. The second memory cell from the fourth memory cell,
And the output buffer circuit for outputting the data given to the data line, the data from the first bit line pair given to the first data line is outputted from the output buffer circuit. Data is supplied from the second bit line pair to the second data line pair during the certain period, and the data from the second bit line pair supplied to the second data line pair is output from the output buffer. A semiconductor memory circuit, wherein data is applied from the third bit line pair to the first data line pair during a period of being output from the circuit.