JPH0766543A - Printed board - Google Patents

Printed board

Info

Publication number
JPH0766543A
JPH0766543A JP5216352A JP21635293A JPH0766543A JP H0766543 A JPH0766543 A JP H0766543A JP 5216352 A JP5216352 A JP 5216352A JP 21635293 A JP21635293 A JP 21635293A JP H0766543 A JPH0766543 A JP H0766543A
Authority
JP
Japan
Prior art keywords
chip
components
land
common
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5216352A
Other languages
Japanese (ja)
Inventor
Yasushi Sakamoto
康 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Group Corp
Original Assignee
Aiwa Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aiwa Co Ltd filed Critical Aiwa Co Ltd
Priority to JP5216352A priority Critical patent/JPH0766543A/en
Publication of JPH0766543A publication Critical patent/JPH0766543A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To reduce the gap between chip components in a state that the chip components are arranged in series in the longitudinal direction and to make possible the improvement of the mounting density of the chip components by a method wherein a common land, to where at least two pieces of chip-shaped circuit components can be made an electrical connection in common, is provided. CONSTITUTION:Chip components 11a and 11b, which are a 2125 type square- shaped chip capacitor, for example, are made to arrange in series in such a way that the respective one end of the components 11a and 11b is made a Shared connection to a common land 20a. Moreover, the respective other one end of the components 11a and 11b is made to connect to lands 13a and 13b. The interval between the components 11a and 11b in such a state can be reduced to a dimension (a), which is limited due to the mounting accuracy of a chip component mounter. The dimension (a) is the smallest length between chips in the mounting accuracy of the chip component mounter, is decided in every mounter and the mounting density of the chip components can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、各種の電子機器に適用
されるプリント基板に係り、特にチップ状回路部品を直
列に配置させたプリント基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board applied to various electronic devices, and more particularly to a printed circuit board in which chip-shaped circuit components are arranged in series.

【0002】[0002]

【従来の技術】抵抗やコンデンサ等のチップ状回路部品
(以下チップ部品と称す)を用いて基板上に配線パター
ンを形成する場合、チップ部品実装密度が高い程、すな
わちチップ部品間隔が狭い程、多くのチップ部品を一枚
の基板上に実装することができ、基板の小型化が図れ
る。図5に小型の角形チップコンデンサ(チップ部品)
の斜視図を示す。このような角形チップコンデンサの1
つのタイプである2125タイプのチップコンデンサ1
は図5に示した、長さ(L)が約2mm、幅(W)が約
1.25mmそして厚さ(t)が約0.6mmの規格で
形成される。
2. Description of the Related Art When a wiring pattern is formed on a substrate by using chip-shaped circuit components such as resistors and capacitors (hereinafter referred to as chip components), the higher the chip component mounting density, that is, the narrower the chip component spacing, Many chip components can be mounted on one board, and the board can be miniaturized. Figure 5 shows a small rectangular chip capacitor (chip component).
FIG. One of such rectangular chip capacitors
Two types of 2125 type chip capacitors 1
Is formed according to the standard shown in FIG. 5 having a length (L) of about 2 mm, a width (W) of about 1.25 mm and a thickness (t) of about 0.6 mm.

【0003】上記コンデンサ1等のチップ部品を長手方
向に直列配置する構成を図6に示す。特に、図6(a)
は平面図を示し、図6(b)は図6(a)X−X′断面
図である。図6(a)では特にランド配置をわかり易く
するため、半田(図6(b)の4)の図示を省略して示
す。図6(a)及び図6(b)に示すように、プリント
基板2上に配設されたそれぞれランド3a,3bとラン
ド3c,3d上に、チップ部品1aとチップ部品1bの
2つのチップ部品が直列に半田付け(半田:4)接続配
置されている。このようなチップ部品1aと1bの直列
配置では、上記2125タイプのチップ部品を使用した
場合、各チップ部品に関連するランドのセンターライン
(従って各チップ部品間のセンターライン)間の間隔が
3.5mm,従って長さが2mmのチップ部品では部品
間の間隔が1.5mmとなる。
FIG. 6 shows a configuration in which chip components such as the capacitor 1 are arranged in series in the longitudinal direction. In particular, FIG. 6 (a)
Shows a plan view, and FIG. 6 (b) is a sectional view taken along line XX 'in FIG. 6 (a). In FIG. 6A, the solder (4 in FIG. 6B) is omitted in order to make the land arrangement particularly easy to understand. As shown in FIGS. 6A and 6B, two chip parts 1a and 1b are provided on the lands 3a and 3b and the lands 3c and 3d, respectively, which are arranged on the printed circuit board 2. Are connected in series by soldering (solder: 4). In such a serial arrangement of the chip components 1a and 1b, when the above-mentioned 2125 type chip components are used, the distance between the center lines of the lands associated with the respective chip components (and thus the center lines between the respective chip components) is 3. For a chip component having a length of 5 mm and a length of 2 mm, the distance between the components is 1.5 mm.

【0004】[0004]

【発明が解決しようとする課題】上記各チップ部品1
a,1b間の間隔は、従来、半田量の適正化のためのラ
ンドパターン設計部品配置を含む基板設計精度、チップ
部品を基板に実装するための実装機の実装精度等による
種々の制限から、上述した約1.5mmより短くするこ
とができなかった。従って、図6に示したような従来の
チップ部品1aと1bの直列配置構成では実装密度の向
上が困難であった。
Each of the above chip parts 1
The spacing between a and 1b has conventionally been limited due to various restrictions due to board design accuracy including land pattern design component placement for optimizing the amount of solder, mounting accuracy of a mounting machine for mounting chip components on a substrate, and the like. It could not be made shorter than about 1.5 mm described above. Therefore, it is difficult to improve the mounting density in the conventional serial arrangement configuration of the chip components 1a and 1b as shown in FIG.

【0005】本発明はチップ部品の長手方向での直列配
置状態で、チップ部品間隔を縮小でき、実装密度を向上
し得るプリント基板を提供することを目的とする。
It is an object of the present invention to provide a printed circuit board which can reduce the chip component interval and improve the mounting density when the chip components are arranged in series in the longitudinal direction.

【0006】[0006]

【課題を解決するための手段】請求項1に記載された本
発明に係るプリント基板は、少なくとも2個のチップ状
回路部品を直列に配置してなるプリント基板において、
前記少なくとも2個のチップ状回路部品に対して電気的
接続を共有し得る共通ランドを設けてなることを特徴と
する。
A printed circuit board according to the present invention as defined in claim 1 is a printed circuit board in which at least two chip-shaped circuit components are arranged in series,
It is characterized in that a common land capable of sharing electrical connection is provided for the at least two chip-shaped circuit components.

【0007】請求項2に記載された本発明に係るプリン
ト基板は、請求項1のプリント基板のチップ状回路部品
がチップ状回路部品実装機の実装精度の最小間隔で配置
され、該チップ状回路部品に対応するランドを設けてな
ることを特徴とする。
According to a second aspect of the present invention, in the printed circuit board according to the first aspect, the chip-shaped circuit components of the printed circuit board according to the first aspect are arranged at a minimum interval of mounting accuracy of the chip-shaped circuit component mounting machine. It is characterized in that lands corresponding to the parts are provided.

【0008】請求項3に記載された本発明に係るプリン
ト基板は、請求項1のプリント基板の共通ランド側面中
央部に凹部を設けてなることを特徴とする。
According to a third aspect of the present invention, there is provided a printed circuit board according to the first aspect, wherein a concave portion is provided at a central portion of a side surface of the common land of the printed circuit board according to the first aspect.

【0009】請求項4に記載された本発明に係るプリン
ト基板は、請求項1のプリント基板のチップ状回路部品
の直列配置長手方向における前記共通ランドの幅を、該
共通ランド以外のランド幅よりも大きくしたことを特徴
とする。
According to a fourth aspect of the printed circuit board of the present invention, the width of the common land in the longitudinal direction of series arrangement of the chip-shaped circuit components of the printed circuit board of the first aspect is smaller than that of the land other than the common land. It is also characterized in that

【0010】[0010]

【作用】請求項1記載のプリント基板によれば、少なく
とも2個のチップ状回路部品に対して電気的接続を共有
し得る共通ランドが設けられているため、チップ状回路
部品の部品間隔をチップ実装機の実装精度の制限値、例
えば0.5mm程度にまで低く抑えることが可能とな
り、実装密度の向上が実現できる。
According to the printed circuit board of the present invention, since at least two chip-shaped circuit components are provided with a common land capable of sharing electrical connection, the chip-shaped circuit components can be separated from each other by a chip interval. It becomes possible to suppress the mounting accuracy of the mounting machine to a lower limit value, for example, to about 0.5 mm, and it is possible to improve the mounting density.

【0011】請求項2のプリント基板によれば、チップ
状回路部品がチップ状回路部品実装機の実装精度の最小
間隔で配置され、該チップ状回路部品に対応するランド
が設けられているため、チップ状回路部品が所定ランド
上に最小間隔で装着され実装密度の向上が実現できる。
According to the printed circuit board of the second aspect, the chip-shaped circuit components are arranged at the minimum interval of the mounting accuracy of the chip-shaped circuit component mounting machine, and the lands corresponding to the chip-shaped circuit components are provided. The chip-shaped circuit components are mounted on the predetermined land at the minimum interval, and the mounting density can be improved.

【0012】請求項3のプリント基板によれば、少なく
とも2個のチップ状回路部品に対して電気的接続を共有
し得る共通ランドが設けられているため、チップ状回路
部品の部品間隔を、チップ実装機の精度の制限のみ、例
えば0.5mm程度まで低く抑えることが可能となり、
実装密度の向上が実現できると共に、前記共通ランド側
面中央部に凹部を設けているために、半田によってチッ
プ部品が互いに不都合に引き寄せられるのを防止する。
According to the third aspect of the present invention, since at least two chip-shaped circuit components are provided with common lands capable of sharing electric connection, the chip-shaped circuit components can be separated from each other by a chip interval. Only the accuracy of the mounting machine can be limited, for example, it can be reduced to about 0.5 mm,
The mounting density can be improved, and since the recess is provided in the central portion of the side surface of the common land, it is possible to prevent the chip components from being disadvantageously attracted to each other by the solder.

【0013】また請求項4のプリント基板によれば、少
なくとも2個のチップ状回路部品に対して電気的接続を
共有し得る共通ランドが設けられているため、チップ状
回路部品の部品間隔を、チップ実装機の精度の制限の
み、例えば0.5mm程度にまで低く抑えることが可能
となり、実装の向上が実現できると共に、チップ状回路
部品の直列配置長手方向における前記共通ランドの幅
を、該共通ランド以外のランドの幅よりも大きくしてい
るため、チップ部品を共通ランドに半田付けする際のず
れに対し余裕があり、安定した実装が可能となる。
Further, according to the printed circuit board of the fourth aspect, since the common land capable of sharing the electrical connection is provided for at least two chip-shaped circuit components, the component intervals of the chip-shaped circuit components can be reduced. Only the accuracy of the chip mounting machine can be limited to, for example, about 0.5 mm, and mounting can be improved, and at the same time, the width of the common land in the longitudinal direction of the serial arrangement of the chip-shaped circuit components is set to the common width. Since the width of the lands other than the lands is larger than that of the lands, there is a margin against a deviation when soldering the chip component to the common land, and stable mounting is possible.

【0014】[0014]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0015】図1は本発明に係るチップ部品の直列配置
構成の一実施例を示す図であり、特に図1(a)は平面
図、図1(b)は図1(a)のY−Y′断面図である。
図1(a)では図6(a)と同様に、ランド配置をわか
り易くするための半田14の図示を省略して示す。
1A and 1B are views showing an embodiment of a serial arrangement of chip parts according to the present invention. In particular, FIG. 1A is a plan view, and FIG. 1B is a view of Y- of FIG. 1A. It is a Y'sectional view.
Similar to FIG. 6A, FIG. 1A does not show the solder 14 for facilitating understanding of the land arrangement.

【0016】図1に示すように、本実施例では上述した
2125タイプの角形チップコンデンサであるチップ部
品11a及びチップ部品11bがそれぞれ一端を共通ラ
ンド20aに共有接続するように直列配置させる。ま
た、チップ部品11a及びチップ部品11bのそれぞれ
他の一端をそれぞれランド13a及びランド13bに接
続させる。このような状態でのチップ部品間隔は、チッ
プ部品実装機の実装精度から制限される寸法aに縮小す
ることができる。
As shown in FIG. 1, in this embodiment, the chip components 11a and 11b, which are the above-mentioned 2125 type rectangular chip capacitors, are arranged in series so that one ends thereof are commonly connected to the common land 20a. The other ends of the chip component 11a and the chip component 11b are connected to the lands 13a and 13b, respectively. The chip component interval in such a state can be reduced to the dimension a limited by the mounting accuracy of the chip component mounter.

【0017】図1におけるb1,b2は各チップ部品の
各電極に対する長手方向の有効半田長さ(ランド長さ)
であり、各チップ部品の電極形状により決定される。a
はチップ部品実装機の実装精度の最小チップ部品間距離
で、各実装機ごとに決定される。よって共通ランド20
aの長さをa+1/2×b1+1/2×b2とすること
により例えば2個のチップ部品11a,11bを実装す
るための最小長さcが得られ、これにより実装密度を上
げることができる。
In FIG. 1, b1 and b2 are effective solder lengths (land lengths) in the longitudinal direction with respect to each electrode of each chip part.
And is determined by the electrode shape of each chip component. a
Is the minimum inter-chip component distance of the mounting accuracy of the chip component mounter and is determined for each mounter. Therefore, common land 20
By setting the length of a to a + 1/2 × b1 + 1/2 × b2, for example, the minimum length c for mounting the two chip components 11a and 11b can be obtained, which can increase the mounting density.

【0018】図2及び図3は図1に示したチップ部品の
直列配置を利用して種々形成した平面図であり、特に、
図2はチップ部品を多数直列配置した場合、一方図3は
それぞれ図1と図2で示したチップ部品直列配置を基板
上に同時に行った場合を示す。図2、図3とも図1
(a)と同様にランド配置をわかり易く示すために半田
14の図示を省略して示す。
FIGS. 2 and 3 are plan views showing various shapes formed by using the serial arrangement of the chip parts shown in FIG.
2 shows a case where a large number of chip components are arranged in series, while FIG. 3 shows a case where the chip component series arrangements shown in FIGS. 1 and 2 are simultaneously performed on a substrate. 2 and 3 are both shown in FIG.
As in (a), the illustration of the solder 14 is omitted in order to clearly show the land arrangement.

【0019】まず、図2では4個のチップ部品11c,
11d,11e,11fが共通ランド20b,20c,
20dを介し、ランド13cとランド13d間で直列配
置されている。このように共通ランドを多数介在させる
ことによって多数のチップ部品を高密度に実装すること
ができる。
First, in FIG. 2, four chip parts 11c,
11d, 11e, 11f are common lands 20b, 20c,
It is arranged in series between the land 13c and the land 13d via the 20d. By interposing a large number of common lands in this way, a large number of chip components can be mounted at high density.

【0020】次に図3では、図1に示した直列配列のチ
ップ部品11a,11bが共通ランド20aを介して部
品間隔を狭めて設けられ、且つ、図2に示した直列配列
のチップ部品11c,11d,11e,11fが共通ラ
ンド20b,20c,20dを介して設けられている。
このように直列配置のチップ部品は多くの共通ランドを
介することによって種々の組合せあるいは配置パターン
で部品間隔を縮小配置することができ、その結果実装密
度を向上させることができる。
Next, in FIG. 3, the chip components 11a and 11b arranged in series as shown in FIG. 1 are provided with a narrow component interval through the common land 20a, and the chip components 11c arranged in series as shown in FIG. , 11d, 11e, 11f are provided via common lands 20b, 20c, 20d.
In this way, the chip components arranged in series can be arranged in a reduced size by various combinations or arrangement patterns by interposing a large number of common lands, and as a result, the mounting density can be improved.

【0021】上記実施例で示した共通ランドはチップ部
品の半田付け信頼性、半田の表面張力による部品の片寄
り等を防止するため、種々の形状が考えられる。図4は
中央部に凹部を形成した種々の共通ランド形状を用いて
チップ部品を直列配置した状態を示す平面図であり、特
に図4(a)では共通ランドの凹部をテーパー状に設
け、図4(b)では共通ランドの凹部を曲線的に設けた
ものである。図4において、チップ部品11gとチップ
部品11h間の間隔をあるチップ部品実装機の実装精度
から制限される値、0.5mmとし、共通ランドの中心
に凹部を形成しているため、半田付け時に半田によって
チップ部品が互いに引き寄せられることが防止される。
また、共通ランドの中央部に凹部を形成することにより
必然的に共通ランド両サイドに広がりを持たせることが
可能となり、チップ部品に対して側面での半田付け性を
向上させることができた。
Various shapes can be considered for the common land shown in the above embodiment in order to prevent the reliability of soldering of chip parts and the deviation of parts due to the surface tension of solder. FIG. 4 is a plan view showing a state in which chip parts are arranged in series by using various common land shapes in which a concave portion is formed in the central portion. Particularly, in FIG. 4A, the concave portion of the common land is provided in a tapered shape. In FIG. 4 (b), the recess of the common land is provided in a curved shape. In FIG. 4, the distance between the chip component 11g and the chip component 11h is set to 0.5 mm, which is a value limited by the mounting accuracy of the chip component mounter, and the recess is formed at the center of the common land. The solder prevents the chip components from being pulled together.
Further, by forming the concave portion in the central portion of the common land, it is possible to inevitably have a spread on both sides of the common land, and it is possible to improve the solderability on the side surface of the chip component.

【0022】[0022]

【発明の効果】以上説明したように、本発明によればチ
ップ状回路部品を直列配置する際に、共通部のランドパ
ターン(共通ランド)を一つにすることによって、チッ
プ部品間隔を縮小することが可能となり、実装密度を向
上させることができる。
As described above, according to the present invention, when the chip-shaped circuit parts are arranged in series, the land pattern of the common part (common land) is made to be one to reduce the chip part interval. This makes it possible to improve the packaging density.

【0023】また本発明に係る共通ランドを所定形状に
することによってチップ部品の半田付け性を向上させる
ことも可能となる。
Further, by forming the common land according to the present invention into a predetermined shape, it becomes possible to improve the solderability of the chip component.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るチップ部品の直列配置構成プリン
ト基板の一実施例を示す図である。
FIG. 1 is a diagram showing an embodiment of a printed circuit board in which chip components are arranged in series according to the present invention.

【図2】本発明に係る多数のチップ部品の直列配置構成
を備えたプリント基板平面図である。
FIG. 2 is a plan view of a printed circuit board having a serial arrangement configuration of a large number of chip components according to the present invention.

【図3】図1と図2のチップ部品の直列配置構成を備え
たプリント基板平面図である。
FIG. 3 is a plan view of a printed circuit board having a serial arrangement configuration of the chip components of FIGS. 1 and 2.

【図4】本発明に係る共通ランド形状(中央部に凹部形
成)の例を示す平面図である。
FIG. 4 is a plan view showing an example of a common land shape (a recess is formed in the central portion) according to the present invention.

【図5】チップコンデンサの形状を説明するための斜視
図である。
FIG. 5 is a perspective view for explaining the shape of a chip capacitor.

【図6】従来の実装方式によりチップ部品を直列配置し
たプリント基板を示す図である。
FIG. 6 is a diagram showing a printed circuit board in which chip components are arranged in series by a conventional mounting method.

【符号の説明】[Explanation of symbols]

1a,1b,11a,11b・・・11h チップ部品 2,12 プリント基板 3a,3b,3c,3d,13a,13b・・・13f
ランド 4,14 半田 20a,20b,20c,20d,21a,21b,2
2 共通ランド
1a, 1b, 11a, 11b ... 11h Chip parts 2, 12 Printed circuit boards 3a, 3b, 3c, 3d, 13a, 13b ... 13f
Land 4,14 Solder 20a, 20b, 20c, 20d, 21a, 21b, 2
2 common land

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも2個のチップ状回路部品を直
列に配置してなるプリント基板において、 前記少なくとも2個のチップ状回路部品に対して電気的
接続を共有し得る共通ランドを設けてなることを特徴と
するプリント基板。
1. A printed circuit board in which at least two chip-shaped circuit components are arranged in series, and a common land which can share electrical connection with the at least two chip-shaped circuit components is provided. Printed circuit board characterized by.
【請求項2】 前記チップ状回路部品がチップ状回路部
品実装機の実装精度の最小間隔で配置され、該チップ状
回路部品に対応するランドを設けてなることを特徴とす
る請求項1記載のプリント基板。
2. The chip-shaped circuit component is arranged at a minimum interval of mounting accuracy of a chip-shaped circuit component mounter, and lands corresponding to the chip-shaped circuit component are provided. Printed board.
【請求項3】 前記共通ランド側面中央部に凹部を設け
てなることを特徴とする請求項1記載のプリント基板。
3. The printed circuit board according to claim 1, wherein a concave portion is provided in a central portion of a side surface of the common land.
【請求項4】 チップ状回路部品の直列配置長手方向に
おける前記共通ランドの幅を、該共通ランド以外のラン
ド幅よりも大きくしたことを特徴とする請求項1記載の
プリント基板。
4. The printed circuit board according to claim 1, wherein the width of the common land in the longitudinal direction of the serial arrangement of the chip-shaped circuit components is larger than the width of the land other than the common land.
JP5216352A 1993-08-31 1993-08-31 Printed board Pending JPH0766543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5216352A JPH0766543A (en) 1993-08-31 1993-08-31 Printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5216352A JPH0766543A (en) 1993-08-31 1993-08-31 Printed board

Publications (1)

Publication Number Publication Date
JPH0766543A true JPH0766543A (en) 1995-03-10

Family

ID=16687215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5216352A Pending JPH0766543A (en) 1993-08-31 1993-08-31 Printed board

Country Status (1)

Country Link
JP (1) JPH0766543A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114223A (en) * 2008-11-05 2010-05-20 Alps Electric Co Ltd Method of mounting chip component and substrate module mounted with chip component
CN108551722A (en) * 2018-06-05 2018-09-18 肖国选 Unit pcb board
US11495587B2 (en) 2018-09-27 2022-11-08 Nichia Corporation Light emitting device and method of producing light emitting device
US11641717B2 (en) 2021-08-30 2023-05-02 International Business Machines Corporation Soldering of end chip components in series
US11948925B2 (en) 2018-09-27 2024-04-02 Nichia Corporation Light emitting device and method of producing light emitting device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114223A (en) * 2008-11-05 2010-05-20 Alps Electric Co Ltd Method of mounting chip component and substrate module mounted with chip component
CN108551722A (en) * 2018-06-05 2018-09-18 肖国选 Unit pcb board
US11495587B2 (en) 2018-09-27 2022-11-08 Nichia Corporation Light emitting device and method of producing light emitting device
US11948925B2 (en) 2018-09-27 2024-04-02 Nichia Corporation Light emitting device and method of producing light emitting device
US11641717B2 (en) 2021-08-30 2023-05-02 International Business Machines Corporation Soldering of end chip components in series

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