JPH0766552A - Wiring board manufacturing method - Google Patents
Wiring board manufacturing methodInfo
- Publication number
- JPH0766552A JPH0766552A JP20743693A JP20743693A JPH0766552A JP H0766552 A JPH0766552 A JP H0766552A JP 20743693 A JP20743693 A JP 20743693A JP 20743693 A JP20743693 A JP 20743693A JP H0766552 A JPH0766552 A JP H0766552A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pattern
- dummy
- manufacturing
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】
【目的】高密度、高アスペクト比配線の多層化に伴う配
線および絶縁層による凹凸を抑制し、信頼性の高い薄膜
多層基板を製造する方法を提供することにある。
【構成】基板上１に配線パターンを形成し、配線間の粗
密を解消するため樹脂等を用いてダミー配線８を形成す
る。配線とダミー配線が混在するパターンの上に絶縁層
４を塗布する。このダミー配線を形成することにより、
基板上の配線の粗密を解消し、絶縁膜を塗布した際に表
面の平坦性を向上することが出来る。
【効果】本発明によれば、高アスペクト比の配線に対す
る絶縁膜を平坦に形成することができる。
(57) [Abstract] [PROBLEMS] To provide a method for manufacturing a highly reliable thin film multilayer substrate by suppressing unevenness due to wiring and an insulating layer due to multilayering of high density and high aspect ratio wiring. [Structure] A wiring pattern is formed on a substrate 1, and a dummy wiring 8 is formed by using a resin or the like in order to eliminate the density of wiring. The insulating layer 4 is applied on a pattern in which wiring and dummy wiring are mixed. By forming this dummy wiring,
It is possible to eliminate the density of wiring on the substrate and improve the flatness of the surface when an insulating film is applied. [Effect] According to the present invention, an insulating film for a wiring having a high aspect ratio can be formed flat.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路また
は、薄膜多層基板の製造方法に関し、特に幅100μm以下
の微細配線を持つ薄膜多層配線基板の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit or a thin film multilayer substrate, and more particularly to a method for manufacturing a thin film multilayer wiring substrate having fine wiring with a width of 100 μm or less.
【０００２】[0002]
【従来の技術】従来、逐次積層の薄膜多層基板では、図
１に示すようにアルミナ等の基板１の上に表面凹凸を無
くすための下地膜２を形成し、その上に所定の回路３で
示す配線パターンが形成された。その上に一様な膜厚を
もつ絶縁層４が設置される。これらの上に更に第２の配
線パターンを形成することにより配線の多層化を行う。2. Description of the Related Art Conventionally, in a thin film multi-layer substrate of successive lamination, as shown in FIG. 1, a base film 2 for eliminating surface irregularities is formed on a substrate 1 made of alumina or the like, and a predetermined circuit 3 is formed thereon. The wiring pattern shown was formed. An insulating layer 4 having a uniform film thickness is provided thereon. By further forming a second wiring pattern on these, the wiring is multi-layered.
【０００３】ところで、このような薄膜多層基板では、
図２に示すように、回路基板の表面には、配線パターン
３、および絶縁層４、によって表面凹凸が生じ、この凹
凸によって回路基板表面の平坦化が妨げられる。この凹
凸は、多層化が進むにつれて顕著となり、後の上層配線
層形成時のフォト工程において、断線や配線パターンの
太り、配線パターンのやせといった問題が生じ、配線基
板の信頼性の低くするものである。By the way, in such a thin film multilayer substrate,
As shown in FIG. 2, the wiring pattern 3 and the insulating layer 4 cause surface irregularities on the surface of the circuit board, and the irregularities prevent the surface of the circuit board from being flattened. This unevenness becomes more remarkable as the number of layers increases, and problems such as disconnection, thickening of the wiring pattern, and thinning of the wiring pattern occur in the photo step of forming the upper wiring layer later, which lowers the reliability of the wiring board. is there.
【０００４】そこで従来、配線基板の絶縁層を平坦化す
る方法としては、プレスを用いる方法（特開平4-38157
号公報）や、研磨を用いる方法（特開平4-290095号公
報）が用いられてきた。しかし、プレスを用いる方法
は、微細なスタッド(ビアの形成を目的とした微細な配
線パターン)が存在する場合において、スタッドを押し
つぶす懸念がある。また、基板が大きく反っている場合
は、基板端部と基板中心部で絶縁膜厚が異なるといった
問題があった。一方、研磨を用いる方法では、絶縁層表
面に傷を残すと同時に配線密度が高い部分では、効率の
良い研磨が出来ないといった問題があった。Therefore, conventionally, as a method for flattening the insulating layer of the wiring board, a method using a press (Japanese Patent Laid-Open No. 4-38157)
Japanese Patent Laid-Open No. 4-290095) and a method using polishing (Japanese Patent Laid-Open No. 4-290095). However, the method using a press has a risk of crushing the stud when there is a fine stud (a fine wiring pattern for the purpose of forming a via). Further, when the substrate is largely warped, there is a problem that the insulating film thickness is different between the substrate end portion and the substrate center portion. On the other hand, the method using polishing has a problem that scratches are left on the surface of the insulating layer and, at the same time, efficient polishing cannot be performed in a portion having a high wiring density.
【０００５】また、スクリーン印刷を用いる方法(特開
平4-221886号公報)が考えられているが、絶縁層に樹脂
を用いると、ワニス状態では表面が平坦になる。しか
し、ワニスを硬化させると溶剤が抜けて体積収縮すると
同時に、樹脂自身も硬化収縮するので表面段差は期待す
る程小さくならない。また、配線が微細になるにつれ、
位置合わせ精度が高くなり、ずれが生じた場合は、配線
上に絶縁層が重なり、段差がさらに大きくなる可能性が
ある。A method using screen printing (Japanese Patent Laid-Open No. 4-221886) has been considered, but if a resin is used for the insulating layer, the surface becomes flat in a varnish state. However, when the varnish is hardened, the solvent escapes and the volume shrinks, and at the same time, the resin itself hardens and shrinks, so that the surface level difference does not become smaller than expected. Also, as the wiring becomes finer,
When the alignment accuracy becomes high and a shift occurs, the insulating layer may overlap the wiring, and the step may be further increased.
【０００６】[0006]
【発明が解決しようとする課題】絶縁層表面の平坦性
は、近年要求される高性能の電子回路基板の製造プロセ
スにおいて、配線密度の大幅な向上のための重要な技術
である。特に高アスペクト比の配線パターンに対して
は、表面凹凸が大きくなるために平坦性の向上は必須で
ある。このため、本発明では、簡易な方法で平坦な表面
を持つ層間絶縁膜の形成方法を提供するものである。The flatness of the surface of the insulating layer is an important technique for greatly improving the wiring density in the manufacturing process of a high-performance electronic circuit board which has recently been required. Particularly for a wiring pattern having a high aspect ratio, the surface unevenness is large, so that improvement of flatness is essential. Therefore, the present invention provides a method for forming an interlayer insulating film having a flat surface by a simple method.
【０００７】[0007]
【課題を解決するための手段】本発明は、配線の間にダ
ミーパターンを設置し、配線層表面のパターン密度が一
定となるように形成することにより、その後形成する絶
縁層の表面を平坦にするものである。According to the present invention, a dummy pattern is provided between wirings and is formed so that the pattern density on the surface of the wiring layer is constant, so that the surface of an insulating layer to be formed thereafter is made flat. To do.
【０００８】配線形成後の絶縁層の段差の一例を図３に
示す。FIG. 3 shows an example of steps of the insulating layer after the wiring is formed.
【０００９】絶縁層表面の段差は、図３に示すように主
として２つの部分に分けることが出来る。即ち、配線間
に生じる段差６と配線が有る部分（配線が密の部分）と
配線が無い部分（配線が粗な部分）の段差７とに分けら
れる。このうち、後者（粗密の差）が原因の凹凸は、配
線が密の部分全体が盛り上がるようになっており、研磨
等によっても削ることが困難である。The step on the surface of the insulating layer can be mainly divided into two parts as shown in FIG. That is, it is divided into a step 6 formed between the wirings, a step 7 having a wiring (a dense wiring portion) and a step 7 having no wiring (a rough wiring portion). Among these, the latter unevenness (difference in density) is raised in the whole area where the wiring is dense, and it is difficult to remove it by polishing or the like.
【００１０】本発明においては、基板全体に配線が存在
するように図４に示すダミーパターン８を形成し、配線
の粗密を無くすことにより、絶縁膜表面の凹凸を低減さ
せる。In the present invention, the dummy pattern 8 shown in FIG. 4 is formed so that the wiring exists on the entire substrate, and the density of the wiring is eliminated to reduce the unevenness of the surface of the insulating film.
【００１１】[0011]
【作用】本発明においては、配線の間にダミーパターン
を形成することにより、配線基板表面に粗密な部分をな
くす。このことにより、配線上に絶縁層を塗布した場
合、表面の凹凸が低減される。In the present invention, the dummy pattern is formed between the wirings to eliminate the rough portion on the surface of the wiring board. As a result, when an insulating layer is applied on the wiring, surface irregularities are reduced.
【００１２】[0012]
【実施例】実施例１：図５に本発明で行った銅配線の作
成方法を示す。本方法では、（ａ）基板の凹凸を減らす
ため下地膜２としてポリイミドを塗布し、メッキの給電
層としてCr/Cu/Cr９をスパッタを用いて成膜した。
（ｂ）その上にレジスト１０を塗布し、パターンニング
し、表面のＣｒをエッチングした。（ｃ）次に電気メッ
キを用いて配線パターン３を形成した。（ｄ）同様な操
作を繰り返してスルーホール１１を形成した。（ｅ）最
後にレジスト剥離および給電層をエッチングすることに
より配線を形成した。EXAMPLES Example 1 FIG. 5 shows a method for producing copper wiring according to the present invention. In this method, (a) polyimide was applied as the base film 2 in order to reduce the unevenness of the substrate, and Cr / Cu / Cr9 was formed as a power supply layer for plating by sputtering.
(B) A resist 10 was applied thereon, patterned, and the surface Cr was etched. (C) Next, the wiring pattern 3 was formed by using electroplating. (D) The same operation was repeated to form the through hole 11. (E) Finally, the resist was peeled off and the power feeding layer was etched to form a wiring.
【００１３】配線パターン形成後のプロセスを図６に示
す。（ａ）配線を形成した基板で、図中右方の配線が粗
になっている。（ｂ）ダミー配線となる樹脂１２を塗布
し、（ｃ）アルミを蒸着し、ホト・エッチング法により
パターニングし、ダミーパターンとなる部分の上をアル
ミパターン１３で覆った。（ｄ）ドライエッチを用いて
ダミー配線８となる部分以外を除去し、（ｅ）最後にア
ルミをエッチングで除去した。以上のように配線および
ダミーパターンを形成した基板に絶縁層を形成した。実
施例として、下地膜２と絶縁膜４およびダミー配線とな
る樹脂１２として同一の材料を用いたがダミーパターン
のパターン形状、電気的特性、耐熱性等を考慮し、異な
った材料を用いることも可能である。The process after forming the wiring pattern is shown in FIG. (A) In the substrate on which the wiring is formed, the wiring on the right side in the figure is rough. (B) A resin 12 to be a dummy wiring was applied, (c) Aluminum was vapor-deposited and patterned by a photo-etching method, and a portion to be a dummy pattern was covered with an aluminum pattern 13. (D) A portion other than the portion to be the dummy wiring 8 was removed by dry etching, and (e) aluminum was finally removed by etching. An insulating layer was formed on the substrate on which the wiring and the dummy pattern were formed as described above. In the embodiment, the same material is used as the base film 2, the insulating film 4 and the resin 12 which will be the dummy wiring, but different materials may be used in consideration of the pattern shape of the dummy pattern, electrical characteristics, heat resistance and the like. It is possible.
【００１４】実施例２：銅配線の作成方法は、実施例１
（図５）に示す方法で行なう。配線形成後のプロセスを
図７に示す。配線形成後に感光性ポリイミド１４を塗布
し、露光・現像することにより、ダミーパターン８を形
成する。以上のように配線およびダミーパターンを形成
した基板に絶縁層を形成する。Example 2: A method for producing a copper wiring is described in Example 1.
The method shown in FIG. 5 is used. The process after wiring formation is shown in FIG. After the wiring is formed, the photosensitive polyimide 14 is applied, exposed and developed to form the dummy pattern 8. An insulating layer is formed on the substrate on which the wiring and the dummy pattern are formed as described above.
【００１５】ダミー配線の配置の例を図８に示す。図８
の（ａ）に示す配置は、配線が平行に並んでいるパター
ンであるが、所々配線パターンが存在していないためダ
ミーパターン（黒塗り）を設置した図である（請求項５
に示す線状のダミー）。また、図８の（ｂ）に示す配置
は、スタッドが立っているが、所々スタッドが存在しな
い配置である。そこで、基板内に均一になるようにダミ
ーパターン（黒塗り）を設置した図である（請求項６に
示す点状のダミー）。FIG. 8 shows an example of the layout of dummy wirings. Figure 8
The arrangement shown in (a) is a pattern in which the wirings are arranged in parallel, but since there are no wiring patterns in places, a dummy pattern (black coating) is installed (claim 5).
Linear dummy shown in). Further, in the arrangement shown in FIG. 8B, the studs are standing, but there are no studs in some places. Therefore, it is a diagram in which dummy patterns (black coating) are provided so as to be uniform in the substrate (dot-shaped dummy according to claim 6).
【００１６】以上のように実施例に示すダミーパターン
は、配線が粗の部分に配置し、配線密度が一定になるよ
うにした。As described above, the dummy pattern shown in the embodiment is arranged in a portion where the wiring is rough so that the wiring density is constant.
【００１７】[0017]
【発明の効果】図９（ａ）に段差基板の構造と測定位置
を示す。図９（ｂ）に示す配線間隔、表面凹凸は、図９
（ａ）の１５．および５．の部分である。図９（ｂ）に
配線間隔と表面凹凸の関係を示す。つまり、同じ20μm
の配線幅、20μmの配線高さにおいても配線間隔が大き
くなるにつれて表面凹凸が大きくなっている(配線間隔2
0μmのとき0.25μm、配線間隔60μmのとき1.75μm)。図
９（ｃ）左側に配線間隔が大きいパターンを示す。この
場合、配線間隔１８が60μmのとき表面段差２０は、1.7
5μmとなる。そこで、図９（ｃ）右側に示すようにダミ
ーパターン８を入れることにより表面段差２１は0.25μ
mになり、その平坦化効果は大きい。The structure of the stepped substrate and the measurement position are shown in FIG. 9 (a). The wiring intervals and surface irregularities shown in FIG.
15. of (a). And 5. Part of. FIG. 9B shows the relationship between the wiring interval and the surface unevenness. That is, the same 20 μm
Even with a wiring width of 20 μm and a wiring height of 20 μm, the surface unevenness increases as the wiring spacing increases (wiring spacing 2
(0.25 μm when 0 μm, 1.75 μm when wiring interval is 60 μm). A pattern with a large wiring interval is shown on the left side of FIG. In this case, when the wiring interval 18 is 60 μm, the surface step 20 is 1.7
It becomes 5 μm. Therefore, by inserting the dummy pattern 8 as shown on the right side of FIG.
m, and the flattening effect is great.
【００１８】以上説明したように、本発明によれば、配
線に使用されなかった部分にダミーパターンを設置し、
配線パターンとダミーパターンを形成することにより、
基板上の配線の粗密をなくす。これにより、高アスペク
ト比の配線に対する絶縁膜を平坦に形成できる効果があ
る。As described above, according to the present invention, a dummy pattern is provided in a portion not used for wiring,
By forming a wiring pattern and a dummy pattern,
Eliminates the density of wiring on the board. As a result, there is an effect that the insulating film for the wiring having a high aspect ratio can be formed flat.
【図１】本発明が解決しようとする問題点を示す図であ
る。FIG. 1 is a diagram showing a problem to be solved by the present invention.
【図２】配線基板作成において問題となる段差を示す図
である。FIG. 2 is a diagram showing a step which is a problem in producing a wiring board.
【図３】配線に粗密の部分が存在する基板における絶縁
膜の形状を示す図である。FIG. 3 is a diagram showing a shape of an insulating film on a substrate in which a wiring has a dense and dense portion.
【図４】ダミーパターンの効果を示す図である。FIG. 4 is a diagram showing an effect of a dummy pattern.
【図５】銅配線の作成方法を示す図である。FIG. 5 is a diagram showing a method for producing a copper wiring.
【図６】ダミーパターンの配置例を示す図である。FIG. 6 is a diagram showing an arrangement example of dummy patterns.
【図７】樹脂を用いたダミー配線の作成方法を示す図で
ある。FIG. 7 is a diagram showing a method of forming a dummy wiring using resin.
【図８】感光性樹脂を用いたダミー配線の作成方法を示
す図である。FIG. 8 is a diagram showing a method of forming dummy wirings using a photosensitive resin.
【図９】ダミーパターンの効果を示す図である。FIG. 9 is a diagram showing an effect of a dummy pattern.
1・・・基板、 2・・・下地膜、 3・・・配線パターン、 4・・・層間絶縁膜、 5・・・表面凹凸、 6・・・配線間の凹凸、 7・・・配線の粗密による凹凸、 8・・・ダミーパターン、 9・・・種膜(Cr/Cu/Cr)、 10・・・レジスト、 11・・・スルーホール、 12・・・ダミー配線となる樹脂、 13・・・アルミによるパターン、 14・・・感光性ポリイミド、 15・・・配線間隔、 16・・・配線幅、 17・・・配線高さ、 18・・・配線間隔60μm、 19・・・配線間隔20μm、 20・・・表面段差1.75μm、 21・・・表面段差0.25μm。 1 ... Substrate, 2 ... Base film, 3 ... Wiring pattern, 4 ... Interlayer insulating film, 5 ... Surface irregularities, 6 ... Concavities and convexities between wirings, 7 ... Wiring Unevenness due to density, 8 ... dummy pattern, 9 ... seed film (Cr / Cu / Cr), 10 ... resist, 11 ... through hole, 12 ... resin to be dummy wiring, 13 ... ..Aluminum pattern, 14 ... Photosensitive polyimide, 15 ... Wiring spacing, 16 ... Wiring width, 17 ... Wiring height, 18 ... Wiring spacing 60 μm, 19 ... Wiring spacing 20μm, 20 ・ ・ ・ Surface step 1.75μm, 21 ・ ・ ・ Surface step 0.25μm.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 樫村 隆司 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Kashimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock Engineering Co., Ltd.
Claims (7)
ターンを形成した後、絶縁層を形成する配線基板の製造
方法において、前記配線パターンの近傍に配線と関係の
ないダミーパターンを設置することを特徴とする配線基
板の製造方法。1. A method of manufacturing a wiring substrate, wherein a pattern of a power supply line, a signal line, etc. (hereinafter referred to as a wiring) is formed, and then an insulating layer is formed. In the method, a dummy pattern unrelated to the wiring is provided in the vicinity of the wiring pattern. A method for manufacturing a wiring board, which comprises installing the wiring board.
ンにより基板上のパターン密度が均一となるようにパタ
ーンを配置したことを特徴とする配線基板の製造方法。2. The method of manufacturing a wiring board according to claim 1, wherein the wiring and the dummy pattern are arranged such that the pattern density on the board is uniform.
脂を用いて形成することを特徴とする配線基板の製造方
法。3. The method of manufacturing a wiring board according to claim 1, wherein the dummy pattern is formed using resin.
光性樹脂を用いて形成することを特徴とする配線基板の
製造方法。4. The method of manufacturing a wiring board according to claim 1, wherein the dummy pattern is formed by using a photosensitive resin.
が、配線に類似した線状の形状を持つことを特徴とする
配線基板の製造方法。5. The method for manufacturing a wiring board according to claim 2, wherein the dummy pattern has a linear shape similar to wiring.
が、スタッドに類似した点状の形状を持つことを特徴と
する配線基板の製造方法。6. The method of manufacturing a wiring board according to claim 2, wherein the dummy pattern has a dot shape similar to a stud.
が、面状の形状を持つことを特徴とする配線基板の製造
方法。7. The method of manufacturing a wiring board according to claim 2, wherein the dummy pattern has a planar shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20743693A JPH0766552A (en) | 1993-08-23 | 1993-08-23 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20743693A JPH0766552A (en) | 1993-08-23 | 1993-08-23 | Wiring board manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0766552A true JPH0766552A (en) | 1995-03-10 |
Family
ID=16539742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20743693A Pending JPH0766552A (en) | 1993-08-23 | 1993-08-23 | Wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766552A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999021224A1 (en) * | 1997-10-17 | 1999-04-29 | Ibiden Co., Ltd. | Package substrate |
| WO2004006329A1 (en) * | 2002-07-05 | 2004-01-15 | Fujitsu Limited | Thin-film substrate having post via |
| EP1083779A4 (en) * | 1998-05-19 | 2004-08-25 | Ibiden Co Ltd | PRINTED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME |
| JP2005183740A (en) * | 2003-12-19 | 2005-07-07 | Mitsui Mining & Smelting Co Ltd | Printed wiring board and semiconductor device |
| EP1341231A3 (en) * | 2002-01-31 | 2006-07-19 | STMicroelectronics, Inc. | System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package |
| JP2008270768A (en) * | 2007-03-22 | 2008-11-06 | Ngk Spark Plug Co Ltd | Manufacturing method of multilayer wiring board |
| KR101067207B1 (en) * | 2009-04-16 | 2011-09-22 | 삼성전기주식회사 | Trench substrate and manufacturing method |
| KR101109323B1 (en) * | 2009-10-20 | 2012-01-31 | 삼성전기주식회사 | Manufacturing method of printed circuit board |
| JP2013128118A (en) * | 2011-12-19 | 2013-06-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
| KR101510625B1 (en) * | 2013-10-24 | 2015-04-10 | 주식회사 플렉스컴 | Method for manufacturing the Embedded FPCB |
| JP2015216293A (en) * | 2014-05-13 | 2015-12-03 | 日本特殊陶業株式会社 | Method of manufacturing wiring board and wiring board |
| JP2017122757A (en) * | 2016-01-04 | 2017-07-13 | 国立研究開発法人産業技術総合研究所 | Spot size converter |
-
1993
- 1993-08-23 JP JP20743693A patent/JPH0766552A/en active Pending
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999021224A1 (en) * | 1997-10-17 | 1999-04-29 | Ibiden Co., Ltd. | Package substrate |
| US6392898B1 (en) | 1997-10-17 | 2002-05-21 | Ibiden Co., Ltd. | Package substrate |
| US6411519B2 (en) | 1997-10-17 | 2002-06-25 | Ibiden Co., Ltd. | Package substrate |
| US6487088B2 (en) | 1997-10-17 | 2002-11-26 | Ibiden Co., Ltd. | Package substrate |
| US6490170B2 (en) | 1997-10-17 | 2002-12-03 | Ibiden Co., Ltd. | Package substrate |
| USRE41242E1 (en) | 1997-10-17 | 2010-04-20 | Ibiden Co., Ltd. | Package substrate |
| USRE41051E1 (en) | 1997-10-17 | 2009-12-22 | Ibiden Co., Ltd. | Package substrate |
| US7525190B2 (en) | 1998-05-19 | 2009-04-28 | Ibiden Co., Ltd. | Printed wiring board with wiring pattern having narrow width portion |
| US8629550B2 (en) | 1998-05-19 | 2014-01-14 | Ibiden Co., Ltd. | Printed wiring board with crossing wiring pattern |
| US7332816B2 (en) | 1998-05-19 | 2008-02-19 | Ibiden Co., Ltd. | Method of fabricating crossing wiring pattern on a printed circuit board |
| EP1670300A3 (en) * | 1998-05-19 | 2008-12-03 | Ibiden Co., Ltd. | Printed wiring board and manufacturing method of printed wiring board |
| EP1083779A4 (en) * | 1998-05-19 | 2004-08-25 | Ibiden Co Ltd | PRINTED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME |
| US8018046B2 (en) | 1998-05-19 | 2011-09-13 | Ibiden Co., Ltd. | Printed wiring board with notched conductive traces |
| EP1341231A3 (en) * | 2002-01-31 | 2006-07-19 | STMicroelectronics, Inc. | System and method for providing mechanical planarization of a sequential build up substrate for an integrated circuit package |
| WO2004006329A1 (en) * | 2002-07-05 | 2004-01-15 | Fujitsu Limited | Thin-film substrate having post via |
| JP2005183740A (en) * | 2003-12-19 | 2005-07-07 | Mitsui Mining & Smelting Co Ltd | Printed wiring board and semiconductor device |
| JP2008270768A (en) * | 2007-03-22 | 2008-11-06 | Ngk Spark Plug Co Ltd | Manufacturing method of multilayer wiring board |
| KR101067207B1 (en) * | 2009-04-16 | 2011-09-22 | 삼성전기주식회사 | Trench substrate and manufacturing method |
| KR101109323B1 (en) * | 2009-10-20 | 2012-01-31 | 삼성전기주식회사 | Manufacturing method of printed circuit board |
| JP2013128118A (en) * | 2011-12-19 | 2013-06-27 | Samsung Electro-Mechanics Co Ltd | Printed circuit board and method of manufacturing printed circuit board |
| KR101510625B1 (en) * | 2013-10-24 | 2015-04-10 | 주식회사 플렉스컴 | Method for manufacturing the Embedded FPCB |
| JP2015216293A (en) * | 2014-05-13 | 2015-12-03 | 日本特殊陶業株式会社 | Method of manufacturing wiring board and wiring board |
| US9699916B2 (en) | 2014-05-13 | 2017-07-04 | Ngk Spark Plug Co., Ltd. | Method of manufacturing wiring substrate, and wiring substrate |
| JP2017122757A (en) * | 2016-01-04 | 2017-07-13 | 国立研究開発法人産業技術総合研究所 | Spot size converter |
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