JPH0769887B2 - Information processing system - Google Patents

Description

Description: (a) Technical Field of the Invention The present invention relates to an information processing system which enables a central processing unit operating at high speed to access an input / output device operating at low speed.

(B) Background of technology In an information processing system, an input / output device such as a line control unit that controls information transmission to a communication line is, for example, half as much as a central processing unit and a main storage device that operate by a high-speed clock signal. It operates at a low speed like.

(C) Conventional Technology and Problems FIG. 1 is a diagram showing an example of a conventional information processing system for accessing an input / output device using an access instruction for one clock cycle.

In FIG. 1, a microprocessor MPU as a central processing unit that operates by a clock signal Φ sends data to, for example, a register in an input / output device IO that operates at a cycle length that is twice the cycle length of the clock signal of the microprocessor. When writing, the microprocessor first changes the cycle length of the clock signal to a low speed that is twice as long, and the address of the I / O device IO and the address of the register in it set in the program counter PC are written. The address signal a including the above is transmitted to the input / output device IO via the address bus AB. The address signal a is identified and received by the input / output device IO, and further, the data d transmitted from the accumulator built in the microprocessor MPU via the data bus DB is written in the register according to the address of the register. The above operation speeds are all determined by the cycle of the clock signal Φ changed corresponding to the input / output device.

As is clear from the above description, in the conventional information processing system, in order for the central processing unit to access the input / output device operating at a low speed, the central processing unit determines the speed of the clock signal Φ as the operating speed of the input / output device. I had to lower it. However, reducing the speed of the clock signal reduces the processing capability of the central processing unit.

(D) Object of the Invention An object of the present invention is to provide an input / output device that operates at a low speed without lowering the operation speed of the central processing unit when accessing the input / output device in the conventional information processing system as described above. It is to realize the means to make it accessible.

(E) Configuration of the Invention According to the present invention, there is provided an information processing system comprising: a central processing unit (MPU); and an input / output unit (IO) operated with a clock cycle length twice as long as the clock cycle length. The central processing unit sends a predetermined address signal and data d0 to the input / output device in the first clock cycle, and sends an address signal and data d1 different from the predetermined address signal in the second clock cycle and at the same time as the input / output device. It has a function of transmitting and receiving data between the two, the input / output device (IO) is provided with a selection unit (IOA) and a control unit (IOB), and the selection unit has address reception identification means (DCR, CA, LB). And selection signal transmitting means (LA, CB) are provided, and the address receiving / identifying means identifies and receives the address signal transmitted from the central processing unit in the first clock cycle, and the control unit receives the internal address (Ca). End of 2 clock cycles Has a function of blocking the reception of another address signal different from the predetermined address signal in the second clock cycle, and the selection signal transmitting means is in the operation ready state by the identification reception of the address signal by the address reception identification means. During the second clock cycle, the input / output device selection signal (CS) to the control unit and the input / output device write / read signal based on the input / output device selection signal and the write / read signal (rw) from the central processing unit. (Crw) is sent, and the control unit receives the internal address (Ca) from the address reception identification means of the selection unit.
And the simultaneous reception of the input / output device selection signal (CS) and the input / output device write / read signal (crw) from the selection signal transmitting means,
This is achieved by an information processing system having a function of transmitting and receiving the data d1 to and from the central processing unit.

(F) Action According to the present invention, the central processing unit causes the input / output device to send a predetermined address signal and data d0 at the first clock cycle.
When the address signal is transmitted, the address signal is identified and received by the address receiving and identifying means in the input / output device, and the internal address is transmitted to the control section based on the identification result until the end of the second clock cycle, and the data with the central processing unit is sent. Even if transmission / reception is not prepared and another address signal different from the predetermined address signal is transmitted from the central processing unit in the second clock cycle, the identification reception of this address signal is blocked.

On the other hand, the selection signal transmission means prepares for the transmission of the input / output device selection signal to the control unit by the identification reception of the address signal by the address reception identification means, and the selection signal transmission means is the second.
At the clock cycle, the input / output device selection signal and the input / output device write / read signal based on the input / output device selection signal and the write / read signal from the central processing unit are sent to the control unit.

On the other hand, the control section simultaneously receives the internal address from the address receiving / identifying means and the input / output device selection signal and the input / output device write / read signal from the selection signal sending means to write / read data from the central processing unit. The signal is validated, and the data d1 is transmitted / received to / from the central processing unit.

Thus, even if the processing speed of the central processing unit is twice as high as the processing speed of the input / output device, the central processing unit can send / receive data to / from the input / output device of low speed processing while maintaining the high speed processing. Becomes

Further, in the present invention, when the input / output device receives and identifies the address signal corresponding to its own device in the first clock cycle,
In the second clock cycle, the reception of any address signal is blocked, while the data d1 addressed to itself is received as valid in the second clock cycle and the data d0 in the first clock cycle is invalid and blocked from reception. Only one address is assigned to the output device, and the write / read signal and data from the central processing unit are valid only during the second clock cycle due to the function of the selection signal sending means, and the configuration of the input / output device and the central processing are performed. The input / output device can be easily controlled by the device.

(G) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a configuration of an information processing system including a microprocessor MPU as a central processing unit and an input / output device IO according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating various signal waveforms in FIG. Is. The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, the input / output device IO is a selection unit IOA and a control unit I.
OB and the decoder DCR in the selection unit IOA of the input / output device,
The control circuit CA and the latch circuit LB form an address reception identifying means, and the latch circuit LA and the control circuit CB form a selection signal sending means.

In this embodiment, an example of writing data from the microprocessor MPU to the input / output device will be described. That is, the microprocessor MPU constructs an access command for the input / output device in two clock cycles, and in the first clock cycle, the predetermined address signal a1 and data d0, and in the second clock cycle, an address and data d1 different from the predetermined address signal and data d1. Shall be sent.

On the other hand, in the selection section IOA of the input / output device IO, the decoder DCR, the control circuit CA and the latch circuit as the address reception identification means
The LB identifies and receives the predetermined address signal a1 in the first clock cycle, holds it, sends the internal address (Ca) until the end of the second clock cycle, and is sent in the second clock cycle. It has a function of blocking reception of another different address signal a2.

Further, the latch circuit LA and the control circuit CB as the selection signal sending means invalidate the reception of the data d0 even if the microprocessor MPU sends the data d0 in the first clock cycle, and receive the data d1 sent in the second clock cycle. In order to validate the input signal, the address receiving / identifying means identifies and receives the address signal to enter the operation ready state, and the input / output device selection signal and the input / output device selection signal from the microprocessor are sent to the control unit during the second clock cycle. Write / read signal
It has a function of transmitting an input / output device write / read signal crw based on rw.

2 and 3, the control unit IOB of the input / output device IO
Microprocessor MPU to write data d1 in
Stores a predetermined address a1 in the program counter PC and data d1 in the index register IX, and starts the execution of a 2-byte access instruction in two clock cycles.

In the first clock cycle t1, the microprocessor MPU
Sends a predetermined address signal a1 consisting of the address of the input / output device and the address of, for example, a register in the device from the program counter PC to the address bus AB. Address signal
a1 is a selection unit of the input / output device IO via the address bus AB
It is transmitted to the decoder DCR in the IOA and the latch circuit LB.

The decoder DCR converts the identified and received address signal a1 into an input / output device activation preparation signal s and sends it to the control circuit CA and the latch circuit LA. The control circuit CA that has received the input / output device activation preparation signal s causes the latch circuit LB to hold the address signal a1 transmitted from the address bus AB, and at the same time the decoder DC
The state of R is held for the second clock cycle t2. The latch circuit LB holds the address signal a1 transmitted via the address bus AB and transmits it to the control unit IOB as an internal address ca. On the other hand, the latch circuit LA does not output the input / output device selection signal cs until the second clock cycle t2 is started. It should be noted that other data d0 which is not necessary in this input / output device is transmitted via the data bus DB in the first clock cycle to the control unit IO.
Even if it is transmitted to B, the control unit IOB outputs the input / output device selection signal cs from the latch circuit LA and the input / output device description from the control circuit CB in the selection signal sending means during the first clock cycle t1. Since it does not receive the embedded read signal (crw), the data bus D
It does not receive other data d0 transmitted from B.

In the second clock cycle t2, the microprocessor MPU
When the other address signal a2 different from the predetermined address signal a1 is transmitted from the program counter PC to the address bus AB, the address signal a2 is the decoder of the selection unit IOA of the input / output device IO via the address bus AB. Although transmitted to the DCR and the latch circuit LB, the decoder DCR maintains the output state of the I / O device start preparation signal s during the second clock cycle t2 under the control of the control circuit CA. Has been blocked. The latch circuit LB is also
The address signal a1 transmitted from the address bus AB is held in the first clock cycle t1, and the address signal a2 transmitted via the address bus AB in the second clock cycle t2 is not held.

Therefore, the latch circuit LB continues to transmit the internal address ca to the control unit IOB based on the address signal a1 even during the second clock cycle t2. On the other hand, the latch circuit LA has the second clock cycle t2.
When the operation is started, the operation ready state is changed to the operation state, the input / output device selection signal cs is output, and the control unit IOB and control circuit CB
Communicate to.

Further, the control circuit CB outputs the input / output device selection signal from the latch circuit LA.
While transmitting cs, the write / read signal rw set to the write state transmitted from the microprocessor MPU is transmitted to the control unit IOB as the input / output device write / read signal crw.

In the latter half of the second clock cycle t2, the microprocessor MPU sends the data d1 from the index register IX to the data bus DB. The data d1 is transmitted to the control unit IOB via the data bus DB.

The control unit IOB then receives the internal address, the I / O device selection signal cs, and the I / O device write / read signal set to the write state.
Since crw is received, the data d1 transmitted from the data bus DB can be written in the register.

As is apparent from the above description, according to the present embodiment, in the process of the microprocessor MPU executing the access instruction in two clock cycles, the address a1 sent in the first clock cycle t1 and the address a1 sent in the second clock cycle t2 are sent. Data d1
Are transmitted to the input / output device IO, and data is written in the input / output device by the input / output device selection signal cs and the input / output device write / read signal crw transmitted to the control unit IOB in the second clock cycle t2. . Therefore, the input / output device IO operates at a speed as low as 1/2 of the clock signal Φ that operates the microprocessor MPU, and it is not necessary to reduce the operating speed of the microprocessor MPU to the same level as the input / output device IO.

It is to be noted that FIGS. 2 and 3 are merely embodiments of the present invention, and the application of the present invention is limited to the case of writing data from the microprocessor MPU as the central processing unit to the input / output unit IO. Even if it is applied to the case of reading data from the input / output device IO to the microprocessor, the effect of the present invention does not change.

(H) Effects of the Invention As described above, according to the present invention, in the information processing system, it becomes possible to access the input / output device operating at a low speed without reducing the operating speed of the central processing unit, and the processing capability of the information processing system is reduced. In addition, the configuration of the input / output device and the control from the central processing unit to the input / output device are simplified, and the efficiency of the connection processing can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of the configuration of an information processing system in which a conventional central processing unit accesses an input / output device at one clock cycle, and FIG. 2 is a diagram showing an information processing system according to a first embodiment of the present invention. , FIG. 3 is a diagram illustrating various signal waveforms in FIG. 2. In the figure, a, a1 and a2 are address signals, AB is an address bus, CA and CB are control circuits, ca is an internal address, crw is an input / output device write / read signal, cs is an input / output device selection signal, and DB.
Is a data bus, DCR is a decoder, IO is an input / output device, IOA is an input / output device selector, IOB is an input / output device controller, IX is an index register, LA and LB are latch circuits, and MPU is a central processing unit. , A PC is a program counter, rw is a write / read signal, s is an input / output device activation preparation signal, t1 is a first clock period, t2 is a second clock period, and Φ is a clock signal.

Claims (1)

[Claims] 1. An information processing system comprising a central processing unit (MPU) and an input / output device (IO) operated at a clock cycle length twice the clock cycle length thereof, wherein the central processing unit has a first clock cycle. Sends out a predetermined address signal and data d0 to the input / output device, and in the second clock cycle, an address signal and data different from the predetermined address signal
It has a function to send and receive data to and from the input / output device while sending d1, and the input / output device (IO) is the selection unit (IOA).
And a control unit (IOB), the selection unit is provided with address reception identification means (DCR, CA, LB) and selection signal transmission means (LA, CB), and the address reception identification means is provided by the central processing unit. The address signal sent in the first clock cycle is identified and received, the internal address (Ca) is sent to the control section until the end of the second clock cycle, and another address different from the predetermined address signal in the second clock cycle is sent. It has a function of blocking signal reception, and the selection signal transmission means becomes ready for operation by the identification reception of the address signal by the address reception identification means, and the input / output device selection signal (CS) to the control unit during the second clock cycle. And an input / output device write / read signal (crw) based on the input / output device selection signal and the write / read signal (rw) from the central processing unit, and the control unit internally operates the address receiving / identifying means of the selecting unit. A (Ca) and the input / output device selection signal (CS) and the input / output device write / read signal (crw) from the selection signal sending means can be simultaneously received, and data d1 can be transmitted / received to / from the central processing unit. An information processing system having a function of: