JPH0770012B2 - Tape recorder - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit suitable for obtaining a delay time corresponding to an interval between an erasing head and a recording head in a tape recorder.

[Conventional technology]

Erasing a portion of the recorded track and recording a new signal here, commonly referred to as punch-in punch-out, is already done. With an ordinary tape recorder that does not have a special circuit for punch-in and punch-out,
The erasing head current and the recording head bias signal are simultaneously raised and lowered. Therefore, at the time of punch-in, the original recording from the erasing start point by the erasing head to the recording head is not erased, and a new signal is recorded here, resulting in a double recording state. On the other hand, in the case of punch-out, it is excessively erased and a signal is lost.

In order to solve the above-mentioned problem, delaying the rising and falling of the recording bias by the interval between the erase head and the recording head is disclosed in, for example, Japanese Patent Application No.
-36776. According to this method,
It is possible to perform extremely good punch-in / punch-out control.

[Problems to be solved by the invention]

By the way, when the tape running speed is switched, the tape running time from the erasing head to the recording head changes, so the delay time at punch-in / punch-out must be switched. To achieve this, for example, a variable delay circuit using a counter may be used. However, the variable delay circuit using the counter is relatively expensive.

On the other hand, the tape running speed may be arbitrarily finely adjusted (pitch control). A method of performing punch-in / punch-out delay control in consideration of this pitch control has not been proposed yet.

The delay at punch-in / punch-out has been described above, but for other purposes as well, it is convenient if the delay time that varies inversely proportionally to the tape running speed can be easily obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a tape recorder which can obtain a recording delay having an inversely proportional relationship with the tape running speed with a simple circuit.

[Means for solving problems]

The present invention for achieving the above object includes a tape running device for running a magnetic tape from one of a pair of reels to the other, a recording head disposed in a running path of the magnetic tape, the recording head, and the recording head. An erasing head which is arranged on a running path of the magnetic tape between the reel and one of the reels, and which has a constant distance from the recording head; a recording signal supply circuit connected to the recording head; A recording bias signal supply circuit connected to a recording head, an erase signal supply circuit connected to the erase head, a recording control signal input terminal to which a recording control signal indicating an erase and recording period is supplied, and the storage control signal. It is connected between an input terminal and the control terminal of the recording signal supply circuit or the control terminal of the recording bias signal supply circuit, and is connected to the distance between the erasing head and the recording head. A delay circuit formed so as to give the recording control signal the above-mentioned delay, means for connecting the recording control signal input terminal and the control terminal of the erasing signal supply circuit, and speed for detecting the running speed of the magnetic tape. A tape recorder including a detection circuit, wherein the speed detection circuit is formed to generate a speed detection voltage having an inversely proportional relationship to a running speed of the magnetic tape, and the delay circuit is configured to generate the recording control signal. An edge detection circuit connected to an input terminal and formed to generate an edge detection pulse indicating a leading edge and a trailing edge of the recording control signal, and an edge detection indicating the leading edge obtained from the edge detection circuit. A ramp voltage generation circuit that generates first and second ramp voltages in response to a pulse and an edge detection pulse indicating the trailing edge, the speed detection circuit, and the ramp voltage generation circuit. Connected, comparing the velocity detected voltage and the first and second ramp voltage,
A comparator configured to convert its output voltage from a first level to a second level when the first and second ramp voltages reach the level of the speed detection voltage; and the first ramp voltage. To the output of the comparator indicating that the second ramp voltage has reached the level of the speed detection voltage in response to the output of the comparator indicating that the speed detection voltage has reached the level. A tape comprising: a flip-flop circuit which forms a delayed recording control signal in response to a recording non-permission state and supplies the delayed recording control signal to the control terminal of the recording signal supply circuit or the control terminal of the recording bias signal supply circuit. It is related to the recorder.

To describe the correspondence between the present invention and the embodiments, the recording signal supply circuit is the recording circuit 18 of FIG. 1 or the recording circuit 18 having the muting transistor 70 of FIG. 5, and the recording bias signal supply circuit is The bias oscillator 21, the voltage control amplifier 22, the capacitor 23, and the drive circuit 27 are included. The erase signal supply circuit is the bias oscillator 21, the voltage control amplifier 24, and the drive circuit 28.

[Operation and Effect of the Invention] According to the present invention, it is possible to easily give the recording control signal a delay that changes in inverse proportion to the running speed of the magnetic tape. That is, the variable delay time can be easily obtained by an analog circuit including a combination of the edge detection circuit, the ramp voltage generation circuit, the comparator, and the flip-flop circuit.

〔Example〕

Next, a multi-channel tape recorder according to an embodiment of the present invention will be described with reference to FIGS. The magnetic tape 1 having a plurality of tracks shown in FIG.
It is wound around 3 and travels in the direction indicated by arrow 4. The capstan 5, pinch roller 6,
A multi-channel recording / reproducing head 8 is arranged.

Motors 9 and 10 are coupled to the pair of reels 2 and 3, and a control drive circuit (not shown) is connected to the motors 9 and 10.

A capstan motor 11 is coupled to the capstan 5. In order to control this motor 11, the speed detection circuit 1
2. A servo circuit including a control circuit 13 is provided.
The speed detection circuit 12 includes a speed detection pulse generator 14 composed of a Hall element and the like, and a frequency-voltage conversion circuit 15 for obtaining a speed detection voltage V having an inversely proportional relationship with the output frequency F of the pulse generator 14. It consists of and. The pulse generator 14 generates a rectangular wave pulse at a frequency corresponding to the rotation speed of the motor 11. Frequency-voltage conversion circuit 15 is frequency (travel speed)
The speed detection voltage that changes in inverse proportion to the change of is output.
The control circuit 13 is connected to the frequency-voltage conversion circuit 15, compares the speed detection voltage with a reference voltage, and controls the motor 11 at a constant speed.

In this embodiment, a speed switching and variable control circuit 16 is connected to the control circuit 13. The control circuit 16 switches the speed of the motor 11 and performs fine adjustment (pitch control) by changing the reference voltage.

A recording circuit 18 and a recording / reproducing changeover switch 19 are provided between the recording signal input terminal and the recording / reproducing head 8.
The regeneration circuit 20 is connected to the head 8 via a changeover switch 19. The recording / reproducing head 8 is further provided with a voltage control amplifier.
Bias oscillator 21 is connected via 22 and capacitor 23.

A bias oscillator 21 is connected via a voltage control amplifier 24 to the erasing head 7 arranged so as to have a distance L with respect to the recording / reproducing head 8.

The recording control signal input terminal 25 is a drive circuit via a delay circuit 26.
It is connected to another drive circuit 28 without being connected to the delay circuit 26. The drive circuits 27 and 28 control and drive the respective voltage control amplifiers 22 and 24, and output the bias signal and the erase signal only during the period when the recording control signal or the delay signal is input.

The delay circuit 26 delays the recording control signal by the time required for the tape 1 to travel from the erasing head 7 to the recording / reproducing head 8. Since the tape recorder of this embodiment can change the speed, the delay time must be changed. For this purpose, the output line 29 of the frequency-voltage conversion circuit 15 is connected to the delay circuit 26.

FIG. 2 shows the frequency-voltage conversion circuit 15 of FIG. 1 in detail. The input terminal 30 of the frequency-voltage conversion circuit 15 has a first
This is a part connected to the pulse generator 14 in the figure, and receives a rectangular wave pulse. The repetition frequency of this rectangular wave pulse changes according to the running speed of the tape 1. At the output stage of the input terminal 30, a coupling capacitor 31, an integrating circuit 32, a coupling capacitor 33, an absolute value circuit 34, an averaging circuit 35, and an output terminal 36 are sequentially provided. The integrating circuit 32 includes an operational amplifier 37.
And a resistor 38, 39, 40 and a capacitor 41. The absolute value circuit 34 is a known circuit including an operational amplifier 42, resistors 43, 44, 45 and 46, and diodes 47 and 48. The averaging circuit 35 includes an operational amplifier 49,
This is a known circuit including resistors 50 and 51 and a capacitor 52. The frequency-voltage conversion circuit 15 is configured such that the speed detection voltage V decreases conversely when the frequency F increases in order to perform speed control. The output terminal 36 is connected to the control circuit 13 of FIG. 1 and also connected to the delay circuit 26 via the line 29.

As shown in FIG. 3, the delay circuit 26 of FIG.
3, edge detection circuit 54, first and second D flip-flops 55 and 56, ramp voltage generation circuit 57, comparator 58, resistor 59, and output terminal 60.

The input terminal 53 is a portion connected to the recording control signal input terminal 25 in FIG. _1, and as shown in FIG.
This is the part where the high level signal is input corresponding to t ₄ . The edge detection circuit 54 is a capacitor connected to the input terminal 53.
61, two diodes 62 and 63, an operational amplifier 64, and 4
A differential circuit consisting of two resistors 65, 66, 67, 68, and a capacitor 61 and a resistor 65 is used to obtain the differential pulse of FIG. 4 (B), and by performing full-wave rectification on this pulse, the differential pulse of FIG. ) Is formed so as to obtain the edge pulse. That is, the differential pulse is obtained in synchronization with both the leading edge t ₁ and the trailing edge t ₄ of the recording control signal of FIG. 4 (A).

The first D flip-flop 55 has a set terminal S and a reset terminal R, and the edge detection circuit 54 is connected to the set terminal S.
Are connected. The data input terminal D and the clock input terminal CP of the D flip-flop 55 are both connected to the ground.

The ramp voltage generating circuit 57 includes a capacitor 69 and two resistors 70 and 71.
And a diode 72. One end of the capacitor 69 is a resistor
It is connected to the Q output terminal of the D flip-flop 55 via 70, and the other end is connected to the ground. A discharging resistor 71 having a smaller value than the charging resistor 70 is connected in parallel to the resistor 70 via a diode 72. The capacitor 69 of the ramp voltage generating circuit 57 is charged while the Q output of the D flip-flop 55 is at a high level, as shown in FIG.
The ramp voltage of FIG. 4 (E) is generated.

The non-inverting input terminal of the comparator 58 is connected to one end of the capacitor 69, and the inverting input terminal is connected to the speed detection voltage line 29. The comparator 58 compares the ramp voltage obtained from the capacitor 69 with the speed detection voltage and, when the level of the ramp voltage reaches the level of the speed detection voltage, changes the output voltage level from the low level to the high level. It is configured. The output terminal of the comparator 58 is connected to the reset terminal R of the first D flip-flop 55. The reset terminal R is connected to the ground via the resistor 59.

The output terminal of the first D flip-flop 55 is connected to the clock input terminal CP of the second D flip-flop 56. The data input terminal D of the second D flip-flop 56 is connected to this output terminal, both the set terminal S and the reset terminal R are connected to ground, and the Q output terminal is connected to the delay output terminal 60.

(Operation) When the punch-in / punch-out operation is performed by the tape recorder of FIG. 1, the tape 1 is run, and when the tape position to be erased reaches the erase head 7, a recording control signal is input to the terminal. Since the recording control signal is applied to the drive circuit 28 without passing through the delay circuit, the voltage control amplifier 24 immediately operates and an erase current flows through the erase head 7 to start erase. On the other hand, the recording control signal delayed by the delay circuit 26 is added to the drive circuit 27, and the supply of the recording bias signal is started from the time when the tape 1 has traveled the distance L from the start of erasing, and the recording becomes possible.

In the delay circuit 26 of FIG. 3, when the recording control signal of FIG. 4 (A) is input to the input terminal 53, the trigger signal of FIG. 4 (C) is obtained from the edge detection circuit 54, which is the D flip-flop 55. Add to set terminal S. In response to the trigger input at t _1, the D flip-flop 55 enters the set state as shown in FIG. 4 (D), and the Q output becomes high level. As a result, the charging of the capacitor 69 starts via the resistor 70,
The voltage of the capacitor 69 rises with a slope as shown in FIG. The comparator 58 compares the ramp voltage shown in FIG. 4 (E) with the speed detection voltage V _1, and when the ramp voltage crosses the speed detection voltage V ₁ , the output of the comparator 58 changes from a low level to a high level. . The high level output of the comparator 58 is applied to the reset terminal R of the D flip-flop 55, and the D flip-flop 55 enters the reset state at t ₂ as shown in FIG. As a result, the capacitor 69
Is discharged through the resistor 71, the diode 72 and the low level Q output terminal. When the ramp voltage, which is one input of the comparator 58, becomes lower than the speed detection voltage V ₁ , the output of the comparator 58 returns to the low level again, and the D flip-flop 55 can be reset again.

At t ₂ , the first D flip-flop 55 is reset,
When the output terminal changes from the low level to the high level as shown in FIG. 4 (G), this edge becomes the clock input of the second D flip-flop 56, and the Q output terminal of the second D flip-flop 56 is shown in FIG. As shown in H), it is converted to a high level, and this is supplied to the drive circuit 27 of FIG. 1 as a delayed recording control signal. 1st D flip-flop at t ₄
When a trigger pulse is input to the set terminal S of 55, t _{1 to} t ₂
The same operation as occurs at t ₄ to t ₅ . Second until just before t ₅
Since the D flip-flop 56 is in the set state and is at the low level, the Q output becomes the low level in synchronization with the clock at the time point T ₅ .

As described above, the set period t ₁ of the first flip-flop 55.
~t _2, t ₃ ~t ₅ delay time corresponding to T is given to the recording control signal. When the running speed of the tape 1 in FIG. 1 becomes low,
On the contrary, the speed detection voltage becomes a high value V ₂ as shown by the broken line in FIG. 4 (E). As a result, the first and second D flip-flops 55, 56 and the comparator 58 operate as shown by the dotted line in FIG. 4, and the delay time becomes longer than that in the case of the solid line.

According to this embodiment, only the edge detection circuit 54, the two D flip-flops 55 and 56, the ramp voltage generation circuit 57, and the comparator 58 are provided to obtain a delay time having an inversely proportional relationship with the tape speed. This allows good punch-in and punch-out at various tape speeds.

[Modification]

The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible, for example.

(1) As shown in FIG. 5, a recording transistor 70 may be connected between the recording signal line and the ground, and the transistor 70 may be delayed to delay recording with respect to erasure. In the case of FIG. 5,
The recording bias may be applied at the same time as the erase current without delay.

(2) The D flip-flops 55 and 56 may be another circuit such as an RS flip-flop.

(3) When the tape speed changes significantly, the resistance 38 and / or the third resistance shown in FIG.
The value of resistor 70 in the figure may be switched and corrected to obtain a delay that corresponds exactly to tape speed. The error may be corrected by switching the value of the capacitor 69 shown in FIG. 3 according to the tape speed.

(4) The running speed of the tape 1 may be detected based on the rotation of the reels 2 and 3 or directly from the tape 1.

[Brief description of drawings]

1 is a block diagram showing a tape recorder according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the frequency-voltage conversion circuit of FIG. 1, and FIG. 3 is a circuit diagram showing the delay circuit of FIG. FIG. 4 is a voltage waveform diagram showing the states of points A to H in FIG. 3, and FIG. 5 is a circuit diagram showing a punch-in / punch-out control circuit of a modified example. 1 ... tape, 5 ... capstan, 7 ... erasing head, 8 ... recording / playing head, 11 ... capstan motor, 12 ... speed detection circuit, 26 ... delay circuit, 55,56 ...
D flip-flop, 57 …… Slope voltage generation circuit, 58 ……
comparator.

Claims (1)

[Claims] 1. A tape running device for running a magnetic tape from one of a pair of reels to the other, a recording head arranged in a running path of the magnetic tape, and between the recording head and the one reel. An erasing head disposed on the running path of the magnetic tape and having a constant distance from the recording head, a recording signal supply circuit connected to the recording head, and connected to the recording head. A recording bias signal supply circuit, an erasing signal supply circuit connected to the erasing head, a recording control signal input terminal to which a recording control signal indicating an erasing and recording period is supplied, the recording control signal input terminal, and the recording signal It is connected between a control terminal of a supply circuit or a control terminal of the recording bias signal supply circuit and has a delay corresponding to the distance between the erasing head and the recording head. A delay circuit formed to give a recording control signal, means for connecting the recording control signal input terminal and a control terminal of the erase signal supply circuit, and a speed detection circuit for detecting the running speed of the magnetic tape. A tape recorder provided with the speed detection circuit, wherein the speed detection circuit is formed to generate a speed detection voltage having an inversely proportional relationship to the running speed of the magnetic tape, and the delay circuit is connected to the recording control signal input terminal. An edge detection circuit formed to generate an edge detection pulse indicating a leading edge and a trailing edge of the recording control signal, and an edge detection pulse indicating the leading edge and the rear edge obtained from the edge detection circuit. A ramp voltage generation circuit that generates first and second ramp voltages in response to an edge detection pulse indicating a border, and is connected to the speed detection circuit and the ramp voltage generation circuit, The speed detection voltage is compared with the first and second ramp voltages, and when the first and second ramp voltages reach the level of the speed detection voltage, the output voltage is changed from the first level to the second level. And a comparator formed to switch to the level of the second ramp, and in response to an output of the comparator indicating that the first ramp voltage has reached the level of the speed detection voltage, the recording enabled state is set and the second ramp is generated. In response to the output of the comparator, which indicates that the voltage has reached the level of the speed detection voltage, a delayed recording control signal that is in a recording non-permission state is formed to supply the control terminal of the recording signal supply circuit or the recording bias signal supply. A tape recorder comprising a flip-flop circuit supplied to a control terminal of the circuit.