JPH0770544B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0770544B2 JPH0770544B2 JP61134114A JP13411486A JPH0770544B2 JP H0770544 B2 JPH0770544 B2 JP H0770544B2 JP 61134114 A JP61134114 A JP 61134114A JP 13411486 A JP13411486 A JP 13411486A JP H0770544 B2 JPH0770544 B2 JP H0770544B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- gate electrode
- insulating film
- forming
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関し、特に高集積度の
GaAs電界効果トランジスタのしきい値電圧のバラツキを
小さく形成する半導体装置の製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method of high integration.
The present invention relates to a method for manufacturing a semiconductor device in which variations in threshold voltage of a GaAs field effect transistor are reduced.
従来の技術 GaAsはSiに比べて電子移動度が５〜６倍大きく、高周波
特性に優れた半導体装置を得ることが可能である。特に
GaAsショットキ障壁型電界効果トランジスタ（以下MES
−FET）は超高周波あるいは超高速素子として優れた特
性を有し、MES−FETを用いた集積回路が超高速IC、マイ
クロ波ICとして期待され活発に開発が進められている。
しかしGaAs MES−FETプロセスはSiプロセスに比べて安
定しておらず、また基板自体のバラツキも大きく、これ
がGaAs ICの歩留が低い原因となっている。2. Description of the Related Art GaAs has an electron mobility 5 to 6 times higher than that of Si, and it is possible to obtain a semiconductor device having excellent high frequency characteristics. In particular
GaAs Schottky barrier field effect transistor (hereinafter MES
-FET) has excellent characteristics as an ultra-high frequency or ultra-high speed element, and integrated circuits using MES-FET are expected as ultra-high speed IC and microwave IC, and are being actively developed.
However, the GaAs MES-FET process is not as stable as the Si process, and there are large variations in the substrate itself, which causes the yield of GaAs ICs to be low.
GaAs ICの歩留向上のためにはプロセスの改良により、
しきい値電圧のバラツキを低減することが不可欠となっ
ている。To improve the yield of GaAs ICs, we will improve the process
It is essential to reduce the variation in threshold voltage.
第２図は、GaAs FETを形成する従来の製造方法を示すも
のである。GaAs基板11にイオン注入法で活性層12および
ソース・ドレイン高濃度層13を形成する（ａ）。その後
GaAs基板11全面にシリコン窒化膜14を形成し（ｂ）、次
にオーミック電極15を形成する（ｃ）。その後、フォト
レジスト16でゲート電極パターン17を形成し（ｄ）、リ
アクティブイオンエッチングでゲート電極パターン17開
口部のシリコン窒化膜14をエッチング除去し、GaAs基板
を露出させゲート電極開口部18を形成する（ｅ）。次に
前記ゲート電極開口部18にゲート電極19を形成しGaAs M
ES−FETを形成する（ｆ）。FIG. 2 shows a conventional manufacturing method for forming a GaAs FET. An active layer 12 and a source / drain high-concentration layer 13 are formed on a GaAs substrate 11 by an ion implantation method (a). afterwards
A silicon nitride film 14 is formed on the entire surface of the GaAs substrate 11 (b), and then an ohmic electrode 15 is formed (c). After that, the gate electrode pattern 17 is formed with the photoresist 16 (d), and the silicon nitride film 14 in the opening of the gate electrode pattern 17 is removed by reactive ion etching to expose the GaAs substrate and form the gate electrode opening 18. (E). Next, a gate electrode 19 is formed in the gate electrode opening 18 and GaAs M
An ES-FET is formed (f).
発明が解決しようとする問題点 第２図で説明したようなGaAs MES−FETの製造方法は、
ゲート電極開口部形成のためのシリコン窒化膜のエッチ
ングに異方性を得るためにエッチングガス圧力を低く例
えば10Pa程度としスパッタ性を有するリアクティブイオ
ンエッチングを用いている。しかし、リアクティブイオ
ンエッチングのバラツキや絶縁膜の膜厚や膜質がばらつ
いた場合、基板露出までのエッチング時間が異なりオー
バーエッチングされる部分が起こる。したがって第３図
に示すようにGaAs基板11がリアクティブイオンエッチン
グによりわずかではあるがエッチングされ、その結果例
えば活性層が薄いノーマリオフ型GaAs FETではわずかな
エッチングがしきい値電圧に大きな影響を与えこれがバ
ラツキの原因となり高集積化したGaAs ICでは歩留低下
の原因となっている。Problems to be Solved by the Invention The method of manufacturing a GaAs MES-FET as described in FIG.
In order to obtain anisotropy in the etching of the silicon nitride film for forming the gate electrode opening, reactive ion etching having a low sputtering gas pressure of, for example, about 10 Pa and having a sputter property is used. However, when there are variations in reactive ion etching and variations in the film thickness and film quality of the insulating film, the etching time until the substrate is exposed is different, and an overetched portion occurs. Therefore, as shown in FIG. 3, the GaAs substrate 11 is slightly etched by the reactive ion etching, and as a result, for example, in a normally-off type GaAs FET having a thin active layer, the slight etching greatly affects the threshold voltage. This is a cause of variation and is a cause of low yield in highly integrated GaAs ICs.
問題点を解決するための手段 前記問題点を解決するために本発明は、半導体基板に活
性層を形成する工程，前記半導体基板全面に絶縁膜を形
成する工程，オーミック電極を形成する工程，レジスト
によりゲート電極パターンを形成する工程，前記絶縁膜
をリアクティブイオンエッチング装置でエッチングガス
圧力を低くしエッチングし、前記ゲート電極開口部に前
記絶縁膜を残存させる工程，エッチングガス圧力を高く
リアクティブイオンエッチングし前記ゲート電極開口部
に残存する絶縁膜をエッチングし前記半導体基板を露出
させる工程，前記半導体基板の露出したゲート電極開口
部にゲート電極を形成する工程からなるものである。Means for Solving the Problems To solve the above problems, the present invention provides a step of forming an active layer on a semiconductor substrate, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of forming an ohmic electrode, a resist. A step of forming a gate electrode pattern by etching, a step of etching the insulating film with a reactive ion etching apparatus at a low etching gas pressure to leave the insulating film in the opening of the gate electrode, and a high etching gas pressure of the reactive ion. The process comprises the steps of etching the insulating film remaining in the gate electrode opening to expose the semiconductor substrate, and forming a gate electrode in the exposed gate electrode opening of the semiconductor substrate.
作用 本発明は上記した構成により、GaAs MES−FETのしきい
値電圧のバラツキを低減し、GaAs MES−FETを用いたGaA
s ICの歩留を向上することが可能となる。Action The present invention reduces the variation of the threshold voltage of the GaAs MES-FET by the above-mentioned configuration, and the GaA using the GaAs MES-FET is reduced.
s It is possible to improve the IC yield.
実施例 本発明の半導体装置の製造方法の一実施例を第１図に示
す。第１図において１はGaAs等の半導体基板、２は活性
層、３はソース・ドレイン高濃度層、４は絶縁膜、５は
オーミック電極、６はフォトレジスト、７はゲート電極
形成パターン、８は、エッチング凹部、９はゲート電極
開口部、10はゲート電極である。半導体基板１例えばGa
As基板にイオン注入法で活性層２およびソース・ドレイ
ン高濃度層３を形成する（ａ）。この時注入条件は活性
層２がSiイオンを30kevで５×1012cm-2注入し、ソース
・ドレイン高濃度層３はSiイオンを50kevで５×1013cm
-2注入する。その後820℃で20分間アルシン雰囲気中で
キャップレスアニールする。その後GaAs基板１全面に絶
縁膜４例えばシリコン窒化膜をプラズマCVD法で4000Å
形成する（ｂ）。次にリフトオフ法でオーミック電極５
例えばAuGa/Ni/Auを1300/400/1000Å形成する（ｃ）。
次にフォトレジスト６でゲート電極パターン７を形成す
る（ｄ）。その後、CF4ガスを用いガス圧力10Paでリア
クティブイオンエッチングしシリコン窒化膜４をGaAs基
板１が露出しない程度約3000Åぐらいエッチングして凹
部８を形成する（ｅ）。その後、凹部８の残こったシリ
コン窒化膜４をCF4ガス圧力を30Paとしてリアクティブ
イオンエッチングにより除去し、GaAs基板１を露出させ
ゲート電極開口部９を形成する（ｆ）。その後ゲート金
属板例えばTi/Pt/Auを1000/500/3000Å蒸着しリフトオ
フによりゲート電極10を形成しGaAs MES−FETを形成す
る。EXAMPLE FIG. 1 shows an example of a method of manufacturing a semiconductor device according to the present invention. In FIG. 1, 1 is a semiconductor substrate such as GaAs, 2 is an active layer, 3 is a high concentration source / drain layer, 4 is an insulating film, 5 is an ohmic electrode, 6 is a photoresist, 7 is a gate electrode formation pattern, and 8 is , An etching recess, 9 is a gate electrode opening, and 10 is a gate electrode. Semiconductor substrate 1 eg Ga
An active layer 2 and a source / drain high-concentration layer 3 are formed on an As substrate by an ion implantation method (a). At this time, the implantation condition is that the active layer 2 implants Si ions at 30 kev of 5 × 10 12 cm −2, and the source / drain high-concentration layer 3 implants Si ions at 50 kev of 5 × 10 13 cm 2.
-2 inject. After that, capless annealing is performed at 820 ° C. for 20 minutes in an arsine atmosphere. After that, an insulating film 4 such as a silicon nitride film is formed on the entire surface of the GaAs substrate 1 by plasma CVD at 4000 Å
Form (b). Next, the ohmic electrode 5 is formed by the lift-off method.
For example, AuGa / Ni / Au is formed at 1300/400 / 1000Å (c).
Next, the gate electrode pattern 7 is formed with the photoresist 6 (d). After that, reactive ion etching is performed with CF 4 gas at a gas pressure of 10 Pa to etch the silicon nitride film 4 by about 3000 Å to the extent that the GaAs substrate 1 is not exposed to form a recess 8 (e). Then, the silicon nitride film 4 remaining in the recess 8 is removed by reactive ion etching with CF 4 gas pressure of 30 Pa to expose the GaAs substrate 1 and form the gate electrode opening 9 (f). After that, a gate metal plate such as Ti / Pt / Au is vapor-deposited at 1000/500 / 3000Å, and the gate electrode 10 is formed by lift-off to form a GaAs MES-FET.
本発明の実施例では、ゲート電極開口部の形成にリアク
ティブイオンエッチングを用い、シリコン窒化膜の凹部
８形成には、エッチングガス（CF4）圧力を10Paとしス
パッタ性を強めたエッチングを行い、その後の基板露出
までのエッチングはエッチングガス圧力を30Paとしスパ
ッタ性を弱め基板のエッチングを抑制し、エッチングの
バラツキによるしきい値電圧のバラツキをおさえてい
る。第４図はCF4ガス圧力を変化させた時のシリコン窒
化膜およびGaAsのエッチングレートを示したものであ
る。これよりCF4ガス圧力が10Pa以下ではGaAsのエッチ
ングレートは大きいが25Pa以上ではほとんどエッチング
されないことがわかる。In the embodiment of the present invention, reactive ion etching is used for forming the gate electrode opening, and etching for enhancing the sputterability is performed for forming the concave portion 8 of the silicon nitride film with an etching gas (CF 4 ) pressure of 10 Pa. Subsequent etching until the substrate is exposed is performed by setting the etching gas pressure to 30 Pa to weaken the sputterability and suppress the etching of the substrate, and suppress the variation of the threshold voltage due to the variation of the etching. FIG. 4 shows the etching rates of the silicon nitride film and GaAs when the CF 4 gas pressure was changed. From this, it is understood that when the CF 4 gas pressure is 10 Pa or less, the GaAs etching rate is large, but when the CF 4 gas pressure is 25 Pa or more, the etching is hardly performed.
なお、本実施例では絶縁膜にシリコン窒化膜を用いた
が、これはシリコン酸化膜等のいかなる絶縁膜でもよ
い。またオーミック，ゲート金属も本実施例に限らず他
の金属でもよい。また本実施例ではGaAs基板を用いたが
他の半導体基板であってもよい。Although the silicon nitride film is used as the insulating film in this embodiment, it may be any insulating film such as a silicon oxide film. Also, the ohmic and gate metals are not limited to those in this embodiment, and other metals may be used. Although the GaAs substrate is used in this embodiment, other semiconductor substrates may be used.
発明の効果 本発明の半導体装置の製造方法は、サイドエッチングが
なくかつ半導体基板のエッチングもなく電極開口部が形
成できるため、FETのしきい値電圧のバラツキを低減
し、その結果GaAs ICの歩留を向上させることができ
る。EFFECTS OF THE INVENTION In the method for manufacturing a semiconductor device of the present invention, since the electrode opening can be formed without side etching and without etching the semiconductor substrate, the variation in the threshold voltage of the FET can be reduced, and as a result, the GaAs IC The retention can be improved.
第１図ａ〜ｇは本発明の一実施例の半導体装置の製造方
法の製造工程断面図、第２図ａ〜ｆは従来の製造工程断
面図、第３図は従来の方法における工程途中の断面図、
第４図はエッチングガス圧とエッチングレートの関係を
示すグラフである。 １……半導体基板、２……活性層、３……ソース・ドレ
イン高濃度層、４……絶縁膜、５……オーミック電極、
６……フォトレジスト、７……ゲート電極形成パター
ン、８……絶縁膜凹部、９……ゲート電極開口部、10…
…ゲート電極。1A to 1G are sectional views of a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIGS. 2A to 2F are sectional views of a conventional manufacturing process, and FIG. Cross section,
FIG. 4 is a graph showing the relationship between the etching gas pressure and the etching rate. 1 ... Semiconductor substrate, 2 ... Active layer, 3 ... Source / drain high-concentration layer, 4 ... Insulating film, 5 ... Ohmic electrode,
6 ... Photoresist, 7 ... Gate electrode formation pattern, 8 ... Insulating film recess, 9 ... Gate electrode opening, 10 ...
... gate electrode.
Claims (2)
半導体基板全面に絶縁膜を形成する工程，オーミック電
極を形成する工程，レジストによりゲート電極形成パタ
ーンを形成する工程，前記絶縁膜をリアクティブイオン
エッチング装置でエッチングガス圧力を低くしエッチン
グし、前記ゲート電極開口部に前記絶縁膜を残存させる
工程，エッチングガス圧力を高くリアクティブイオンエ
ッチングし前記ゲート電極開口部に残存する絶縁膜をエ
ッチングし前記半導体基板を露出させる工程，前記半導
体基板の露出したゲート電極開口部にゲート電極を形成
する工程を有することを特徴とする半導体装置の製造方
法。1. A step of forming an active layer on a semiconductor substrate, a step of forming an insulating film on the entire surface of the semiconductor substrate, a step of forming an ohmic electrode, a step of forming a gate electrode formation pattern with a resist, and a step of removing the insulating film. Etching with a low etching gas pressure using an active ion etching device to leave the insulating film in the gate electrode opening, reactive ion etching with a high etching gas pressure to etch the insulating film remaining in the gate electrode opening And a step of exposing the semiconductor substrate and a step of forming a gate electrode in the exposed gate electrode opening of the semiconductor substrate.
アクティブエッチングにおけるエッチングガス圧力を10
Pa以下とし、半導体基板を露出させるリアクティブイオ
ンエッチングにおけるエッチングガス圧力を25Pa以上と
することを特徴とする特許請求の範囲第１項記載の半導
体装置の製造方法。2. The etching gas pressure in reactive etching for leaving an insulating film in the gate electrode opening is 10
The method for producing a semiconductor device according to claim 1, wherein the pressure is set to Pa or less and the etching gas pressure in the reactive ion etching for exposing the semiconductor substrate is set to 25 Pa or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61134114A JPH0770544B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61134114A JPH0770544B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62291070A JPS62291070A (en) | 1987-12-17 |
| JPH0770544B2 true JPH0770544B2 (en) | 1995-07-31 |
Family
ID=15120787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61134114A Expired - Lifetime JPH0770544B2 (en) | 1986-06-10 | 1986-06-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770544B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248179A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| US7302376B2 (en) | 2002-08-15 | 2007-11-27 | International Business Machines Corporation | Device modeling for proximity effects |
-
1986
- 1986-06-10 JP JP61134114A patent/JPH0770544B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62291070A (en) | 1987-12-17 |
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