JPH0772208A - Easy output voltage measurement semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To obtain a semiconductor integrated circuit capable of easily measuring the DC characteristics of an output buffer. [Configuration] A multiplexer 12 is provided which selects one of the output signal of the internal circuit 10 and the power supply voltage VDD and outputs the selected signal to a subsequent output buffer 14. The output buffer 14 supplies an output signal to the output terminal 16. Source terminals of diode-connected FETs are connected to the output terminals 16-1 ... 16-n, respectively. Each FET 18-
The drain terminals of 1 ... 18-n are commonly connected to the maximum voltage terminal 20.
It is connected to the. When a high-level selection signal is supplied from the TEST terminal, the multiplexers 12-1 ... 12-
n selects the power supply voltage VDD and outputs this voltage to the output buffer 1
4-1 ... 14-n are supplied. Therefore, the signal with the highest output voltage of all the output buffers 14-1 ... 14-n is output to the maximum voltage terminal 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In particular, it relates to a semiconductor integrated circuit capable of easily measuring an output voltage.

[0002]

2. Description of the Related Art Conventionally, a completed semiconductor integrated circuit is tested by using a test device generally called an LSI tester. Not only the performance test of the semiconductor integrated circuit that has come out from the manufacturing line, but also the user can use this LSI tester to confirm the function of the semiconductor integrated circuit and to test the output voltage value, delay time, etc., if necessary. There is.

Among them, the output voltage is conventionally measured by measuring a DC voltage or a current in a state where a bias is applied to a semiconductor integrated circuit as an object to be measured.
This so-called direct current measuring method uses a direct current measuring device for directly measuring a direct current voltage. When a direct current measuring device is connected to each measuring terminal of a semiconductor integrated circuit to be subjected to direct current measurement and a bias is applied to this semiconductor integrated circuit. It is carried out by measuring the output voltage of each measurement terminal in. Here, the bias means to apply a current to the measured terminal according to actual use. As a result, in the actual use state, the output voltage of the (measured) terminal in the actual use is measured.

In such a conventional measuring method, a predetermined current under the measuring condition is applied for each pin of the output terminal,
The voltage value was measured. Therefore, since the measurement is performed for each pin, there is a problem that the measurement is troublesome and takes a long time. Therefore, a method of simultaneously measuring a plurality of measurement terminals by providing a tester for measuring the direct current to each of the terminals to be measured in the semiconductor integrated circuit is conceivable. However, in this case, there is a problem that the entire measuring device becomes large.

In order to solve the above problems, a conventional improved test method is disclosed in, for example, Japanese Patent Laid-Open No. 1-24087.
No. 3 publication. According to the method described here, the output voltage of the measuring terminal to which the bias is applied, that is, the output current is applied, is compared with a predetermined upper limit value or lower limit value. That is, in this method, the value of the output voltage of the terminal to be measured is not measured, but the magnitude is compared with a predetermined upper limit value or lower limit value. Therefore, in this method, it is possible to easily test that the output voltage of the measurement terminal is within the predetermined standard value range by using the comparator instead of the so-called ammeter.

[0006]

As described above, according to the above-mentioned conventional and improved test method, the output voltage is measured quickly by the comparator. However, there is no change in the point that measurement must be performed for each measurement terminal, and under the situation where the number of pins of semiconductor integrated circuits is increasing in recent years, there is a limit to the reduction of measurement time. It was

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor integrated circuit capable of quickly measuring that the output voltage values of all measurement terminals are within a predetermined voltage range. It is to be.

[0008]

In order to solve the above-mentioned problems, the first aspect of the present invention provides a plurality of output terminals for outputting an output signal to the outside and a highest voltage among the signals output to the output terminals. A maximum voltage terminal that outputs a signal of equal voltage,
An output buffer provided for each of the output terminals, which supplies an output signal to the output terminal, a high level setting means for forcibly setting the output signal of the output buffer to a high level, and output to the output terminals. Maximum voltage detecting means for detecting the highest voltage of the signals and outputting the voltage to the maximum voltage terminal.

In order to solve the above-mentioned problems, the second aspect of the present invention outputs a plurality of output terminals for outputting an output signal to the outside and a signal having a voltage equal to the lowest voltage of the signals output to the output terminals. A minimum voltage terminal, an output buffer provided for each output terminal and supplying an output signal to the output terminal, a low level setting means for forcibly setting the output signal of each output buffer to a low level, and each output Detect the lowest voltage among the signals output to the terminals,
And a minimum voltage detecting means for outputting the voltage to the minimum voltage terminal.

In order to solve the above problems, a third aspect of the present invention outputs a plurality of output terminals for outputting an output signal to the outside and a signal having a voltage equal to the highest voltage among the signals output to the output terminals. A maximum voltage terminal, an output buffer provided for each of the output terminals and supplying an output signal to the output terminal, and a second high level for forcibly setting the output signals of the output buffers to the high level in order. A semiconductor integrated circuit comprising: setting means; and maximum voltage detecting means for detecting the highest voltage of the signals output to the output terminals and outputting the voltage to the maximum voltage terminal. .

In order to solve the above problems, a fourth aspect of the present invention outputs a plurality of output terminals for outputting an output signal to the outside and a signal having a voltage equal to the lowest voltage among the signals output to the output terminals. Minimum voltage terminal, an output buffer provided for each of the output terminals and supplying an output signal to the output terminal, and second low level setting means for forcibly setting the output signals of the output buffers to the low level in order. And a minimum voltage detecting means for detecting the lowest voltage of the signals output to the output terminals and outputting the voltage to the minimum voltage terminal.

In order to solve the above-mentioned problems, the fifth and sixth aspects of the present invention are the same as the first and third aspects of the present invention, wherein the maximum voltage detecting means is a rectifier provided for each of the output terminals. In the semiconductor integrated circuit, the cathode of each of the rectifiers is connected to the maximum voltage terminal, and the anode of each of the rectifiers is connected to the output terminal.

In order to solve the above-mentioned problems, the seventh invention is the sixth invention, wherein the maximum voltage detecting means includes a capacitor connected between the maximum voltage terminal and ground. It is a featured semiconductor integrated circuit.

In order to solve the above-mentioned problems, the eighth and ninth aspects of the present invention are the same as those of the second or fourth aspect of the invention, wherein the minimum voltage detecting means is a rectifier provided for each of the output terminals. In the semiconductor integrated circuit, the anode of each of the rectifiers is connected to the minimum voltage terminal, and the cathode of each of the rectifiers is connected to the output terminal.

In order to solve the above problems, the tenth invention is the ninth invention, wherein the minimum voltage detecting means includes a capacitor connected between the minimum voltage terminal and ground. It is a featured semiconductor integrated circuit.

[0016]

The maximum voltage detecting means in the first aspect of the present invention detects a voltage equal to the maximum voltage signal among the signals output to the respective output terminals. Then, the detected voltage is output to the maximum voltage terminal. Therefore, the external measuring device connected to the maximum voltage terminal detects the highest voltage among the signals output to the output terminal.

The minimum voltage detecting means in the second aspect of the present invention detects the lowest voltage among the voltages output to all the output terminals. Then, the detected voltage is output to the minimum voltage. Therefore, the external measuring device connected to this minimum voltage terminal measures the lowest voltage of the signals output to each output terminal.

The second high level setting means in the third aspect of the present invention forcibly sets the output buffers connected to the respective output terminals in order to the high level. Then, the maximum voltage detecting means outputs the highest voltage among the signals output to the respective output terminals to the maximum voltage terminal. Therefore, if a voltage measuring device that has a maximum value hold circuit at the maximum voltage terminal and detects the maximum voltage during a predetermined period is connected, the measuring device measures the highest voltage among the signals output from each output terminal. To be done.

The second low level setting means in the fourth aspect of the invention forcibly sets the output of each output buffer to the low level in order. On the other hand, since the minimum voltage detecting means outputs the lowest voltage among the signals output to the output terminals to the minimum voltage terminal, the minimum voltage terminal may be connected to a voltage measuring device equipped with a minimum value holding circuit. For example, it is possible to detect the lowest voltage in each output buffer by measuring the minimum voltage in the cycle in which the output signals of all the output buffers are at the low level.

The maximum voltage detecting means in the fifth and sixth aspects of the present invention is constituted by a so-called diode network. Therefore, the largest voltage among the voltages applied to the anode of each rectifier appears at the maximum voltage terminal to which the cathode of each rectifier is commonly connected.

The maximum voltage detecting means in the seventh aspect of the present invention further includes a capacitor connected between the maximum voltage terminal and the ground. Therefore, even if the voltage measuring device connected to this maximum voltage terminal does not have a maximum value hold circuit, this maximum voltage terminal holds the maximum voltage in a predetermined cycle in which all output terminals are set to high level. Will be done.

The minimum voltage detecting means in the eighth and ninth aspects of the present invention is constituted by a so-called diode network. The smallest voltage among the voltages applied to the cathode of the diode network appears at the minimum voltage terminal to which the anodes of the diode network are commonly connected.

The minimum voltage detecting means in the tenth aspect of the present invention includes a capacitor connected between the minimum voltage terminal and the ground. Therefore, the signal having the smallest voltage among the output terminals output to the minimum voltage terminal is held in this capacitor. Therefore, even when a voltage measuring device having no minimum value hold circuit is connected to the minimum voltage terminal, the voltage of the minimum output signal in a predetermined cycle in which a low level is forcibly set at each output terminal is measured. obtain.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

Embodiment 1 A circuit diagram of a semiconductor integrated circuit according to Embodiment 1 is shown in FIG. As shown in FIG. 1, each output signal of the internal circuit 10 is connected to the output buffers 14-1 ... 14-n via the multiplexers 12-1 ... 12-n. The output signals of the output buffers 14-1 ... 14-n are supplied to the output terminals 16-1 ... 16-n, respectively. A feature of this embodiment is that the output signal of the internal circuit 10 is output via the multiplexer 12 to the output buffer 14
Is being supplied to. This multiplexer 12
-1 ... 12-n selects one of the output signal from the internal circuit 10 and the power supply voltage VDD to output the output buffer 1
Supply to 4. All multiplexers 12-1 ... 12-
The selection state of n is controlled by a selection signal from the outside. In the first embodiment, this selection signal is externally supplied through the TEST terminal. And this TEST
When the selection signal input through the terminal is low level, each multiplexer 12-1 ... 12-n selects the output signal from the internal circuit 10 and outputs the output buffer 14-1.
14-n. However, when this selection signal is at high level, each multiplexer 12-1 ... 12-n
Selects the power supply voltage VDD. That is, a high level signal is forcibly supplied to the subsequent output buffers 14-1 ... 14-n. As a result, according to the first embodiment, the output buffers 14-1 ... 1 according to the selection signal from the outside.
It is possible to output a high level signal to 4-n.

Further, the output buffer 14 in the present embodiment.
The source terminals of the FETs 18 are connected to the respective output terminals of -1 ... 14-n. This FET 18-1 ... 1
The drains of 8-n are commonly connected to the maximum voltage terminal 20. The gate terminals of these FETs 18-1 ... 18-n are respectively connected to the source terminals. That is, each FET 18-1 ... 18-n is so-called diode-connected, and as a result, each output buffer 14-1 ... 18-n.
The signal with the highest voltage among the output signals of 4-n is output to the maximum voltage terminal 20.

The semiconductor integrated circuit according to the first embodiment is TES
When a low level signal is applied to the T terminal,
The multiplexers 12-1 ... 12-n are internal circuits 10
Signal is selected and supplied to the corresponding output buffers 14-1 ... 14-n. Then, each signal is output to the outside through the output terminals 16-1 ... 16-n.

On the other hand, when a high level signal is applied to the TEST terminal, each multiplexer 12-1 ... 12
-N selects the power supply voltage VDD, and supplies a signal of this voltage to each output buffer 14-1 ... 14-n. Therefore,
A high level signal is forcibly output to each of the output terminals 16-1 ... 16-n.

A feature of this embodiment is that all the output signals of the semiconductor integrated circuit can be forcibly set to a high level by the selection signal from the outside as described above. Further, the present embodiment 1 is further characterized in that the diode-connected FETs 18-1 to 18-n are connected to the output terminals 16-1 to 16-n, respectively. With this configuration, a signal having the same voltage as the highest voltage signal among the signals output to the output terminals 16-1 ... 16-n appears at the maximum voltage terminal 20. Therefore, if a voltage measuring device is connected to the maximum voltage terminal 20 and the voltage is measured, the maximum voltage of all the output terminals 16-1 ... 16-n can be measured. Therefore, it is possible to confirm whether or not the signals at the output terminals 16-1 ... 16-n are equal to or less than the specified value of the predetermined upper limit by only once measuring the voltage appearing at the maximum voltage terminal 20.

In many cases, the upper limit value and the lower limit value of the output signal of the semiconductor integrated circuit are set as the standard. Therefore, according to the first embodiment, when the output signals of all the output terminals 16-1 ... 16-n are less than a predetermined upper limit value, the voltage of the maximum voltage terminal 20 is 1
It is possible only by measuring the degree.

As described above, according to the first embodiment, there is an effect that the test for the upper limit value of the output signal of the semiconductor integrated circuit is performed in an extremely short time. If an output voltage in a state where a load is actually connected is required, if a desired load is connected to each output terminal 16-1 ... 16-n, the output voltage in that state is the maximum voltage terminal 20. Will appear in. This has an effect that a test can be easily performed under an arbitrary load condition.

In the first embodiment, the multiplexer 12
-1 ... 12-n is provided with a high level setting means for forcibly outputting a high level signal, and each output terminal 1
It was possible to inspect whether the output signals output to 6-1 ... 16-n are below a predetermined upper limit value. However, by using the low level setting means for forcibly setting the output signal to the low level, the diode-connected FET 18 is used.
It is also possible to take out the signal having the lowest voltage among the signals output to the output terminals 16-1 ... 16-n by reversing the connection relationship of -1 ... 18-n. Thereby, it is possible to inspect that the signals output to the output terminals 16-1 ... 16-n are equal to or more than the lower limit value of the predetermined standard. In this case, it goes without saying that the maximum voltage terminal 20 becomes the minimum voltage terminal 20 'which outputs the signal of the minimum voltage among the signals output to the output terminals 16-1 ... 16-n. Even in such a case, it is similarly achieved that the effect of the above-described first embodiment is that it is possible to quickly determine whether or not the standard value is satisfied.

Second Embodiment FIG. 2 shows a circuit diagram of a semiconductor integrated circuit of the second embodiment. As shown in FIG. 2, in the semiconductor integrated circuit of the second embodiment, the multiplexers 32-1 ... For the output signals output from the internal circuit 30 as in the first embodiment.
32-n are provided. Then, the output buffer 34-1 is provided to each of the multiplexers 32-1 ... 32-n.
34-n are connected, and their output signals are output to the output terminals 36-1 ... 36-n.

The characteristic feature of the second embodiment is that the selection signals supplied to the multiplexers 32-1 to 32-n are not supplied from the outside but to the multiplexers 32-1 to 32-n. 38-n provided in each of the flip-flops 38-1 to 38-n. This flip-flop 38-1 ...
38-n are connected in series and constitute a shift register as a whole. That is, the output signal of the flip-flop 38-1 is supplied to the input terminal of the flip-flop 38-2, and the output signal of the flip-flop 38-2 is supplied to the input terminal of the flip-flop 38-3. A common clock signal is supplied from the oscillation circuit 40 to each of the flip-flops 38-1 ... 38-n. As a result, each of the flip-flops 38-1 ... 38-n receives the data held by the so-called other flip-flop in the previous stage in synchronization with the clock signal, and further receives the data in the subsequent flip-flop in synchronization with the clock signal. Is sent. The signal from the pattern generator 42 is supplied to the flip-flop 38-1 in the first stage. The pattern generator 42 outputs a signal that becomes high level for one clock period during a period of n times the period of the clock signal. The signal output from the pattern generator 42 propagates through each flip-flop 38,
It is propagated to the last flip-flop 38-n. Therefore, the high level signal output from the pattern generator 42 is output to each flip-flop 38 for each clock cycle.
-1 ... 38-n is propagated and finally held in the flip-flop 38-n. In the next clock cycle, the low-level signal is supplied to the flip-flop 38-n, so that the value of the signal held by the flip-flop 38-n becomes low level, but at the same time, a new high-level signal is output. It is output from the pattern generator 42 and held in the flip-flop 38-1. Thus, in the present embodiment, the flip-flops 38-1 ... 3
Any one of 8-n flip-flops 38 is configured to always hold a high level signal.
Therefore, the multiplexer 32-1 in the second embodiment ...
Only one of the 32-n selects the power supply voltage VDD.

In the first embodiment described above, all the multiplexers 12-1 ... 12 are selected by an external selection signal.
-N selects the power supply voltage VDD. However, in the case of such a configuration, all the output terminals 16-1 ... 16-n become high level, and a sudden change in the power supply current occurs. This often causes a momentary drop in the power supply voltage and the generation of noise, and may affect circuits other than the output buffer 14 that is the object of measurement. In the second embodiment, such noise is prevented by using only one multiplexer 32 which is forcibly set to the high level.

In the second embodiment, the pattern generator 42
The pattern signal output from the flip-flop 38
The time chart of FIG. 3 shows how the signals are propagated through -1 ... 38-n. As shown in the time chart of FIG. 3, when the TEST signal from the outside goes to high level, the clock generator 40 and the pattern generator 42 are enabled respectively. Then, as mentioned above,
The clock generator 40 starts to commonly supply the clock signal to the flip-flops 38-1 ... 38-n.
This clock signal is a signal as shown in FIG. Further, the pattern signal output from the pattern generator 42 is a signal which becomes a high level at a constant interval as shown in FIG. By supplying such a clock signal and a pattern signal to the flip-flops 38-1 ... 38-n, these flip-flops 38-1.
Only one of the flip-flops 38 outputs a high level signal. As a result, as shown in FIG. 3, in a certain clock cycle, the output terminal a (36-1)
To the output terminal b (36-2) in the next clock cycle. Then, in the next clock cycle, a high level signal is forcibly output to the output terminal c (36-3). In this way, the output signals of the output buffers 34-1 ... 34-n are sequentially set to the high level, and the signal having the highest voltage among those output signals is output to the maximum voltage terminal 46 via the diode network. To be done.

Similar to the first embodiment, the signal having the highest voltage is output to the maximum voltage terminal 46. However, what is more characteristic of the second embodiment is that the holding capacitor 48 is connected between the maximum voltage terminal 46 and the ground. This holding capacitor 48,
A maximum value hold circuit is formed from the above-mentioned FETs 44-1 ... 44-n. That is, the output buffers 34-1 ... 34-n are forcibly set to a high level in order at a predetermined cycle, but the highest voltage among those output signals is detected by the action of this diode network and the holding capacitor 48. To be done. This is a holding capacitor 48
This is achieved by holding the highest voltage of the signals supplied through the diode network. The highest voltage held by the holding capacitor 48 in this manner is measured from the outside via the maximum voltage terminal 46.

As described above, according to the second embodiment,
The output signals of the output buffers 34-1 ... 34-n are sequentially set to the high level, and the highest voltage among these output signals is held in the holding capacitor 48, and the held voltage is set to the maximum voltage terminal 46. It was output to the outside via.
Therefore, according to the second embodiment, by measuring the voltage of the signal output from the maximum voltage terminal 46, the signal output from each output buffer 34-1 ... 34-n is less than the predetermined maximum value. Can be easily inspected.
Further, all the output buffers 34-1 ... 34-n are not set to the high level at once but are forcibly set to the high level in order, and the highest voltage among them is held in the holding capacitor 48. Unlike Example 1, the risk of causing noise is reduced without causing a sudden change in the power supply current.

Although the signal having the maximum voltage is detected in the second embodiment, the diodes 44-1 ...
It is also suitable to reverse the direction of 44-n and detect the lowest voltage. In this case, the holding capacitor 48 holds the lowest voltage, and this lowest voltage is measured from the outside.
It is possible to easily measure whether or not 4-1 ... 34-n has an output equal to or higher than a predetermined lower limit value. When the lowest voltage is detected in this way, the flip-flop 32-1
32-n are configured to switch between the signal from the internal circuit 30 and the ground. Even in the case of such a configuration, the same operational effect as in the case of measuring the maximum voltage is obtained.

In the second embodiment, the holding capacitor 48 is used to hold the maximum voltage value, but it is also preferable to use the stray capacitance of the wiring as the holding capacitor. That is, if the cycle of the clock signal is set to be sufficiently short, the capacity required for the capacitor for holding the maximum voltage is reduced accordingly. Therefore, if the cycle of the clock signal is sufficiently shortened, it is often the case that the stray capacitance generated in the wiring from the maximum voltage terminal 46 can hold a sufficient voltage without the need to provide a circuit as a capacitor. This stray capacitance is output terminal 3
Although depending on the number of 6's, many of them are about several tens nF to several hundreds nF. Further, the holding capacitor 48 may be provided outside without being provided inside the integrated circuit device.

As described above, even if the holding capacitor 48 is not used and the stray capacitance of the wiring from the maximum voltage terminal 46 is used, or the capacitor is provided outside the maximum voltage terminal 46, the above-described second embodiment is used. The same action and effect are obtained.

[0042]

As described above, according to the present invention, it is possible to add 1 pin or 2 pins to the semiconductor integrated circuit.
It is possible to measure the maximum or minimum voltage at all output terminals.

That is, according to the present invention, it is possible to perform DC measurement on all output terminals at the same time.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first preferred embodiment of the present invention.

FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a second preferred embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the second embodiment. ．

[Explanation of symbols]

 10 internal circuit 12-1 ... 12-n multiplexer 14-1 ... 14-n output buffer 16-1 ... 16-n output terminal 18-1 ... 18-n FET 20 maximum voltage terminal

Claims (10)

[Claims] 1. A plurality of output terminals for outputting an output signal to the outside, a maximum voltage terminal for outputting a signal having a voltage equal to the highest voltage among the signals output to the output terminal, and each of the output terminals An output buffer which is provided and supplies an output signal to the output terminal, a high level setting means for forcibly setting the output signal of each output buffer to a high level, and the highest of the signals output to the output terminals And a maximum voltage detecting unit that detects a voltage and outputs the voltage to the maximum voltage terminal. 2. A plurality of output terminals for outputting an output signal to the outside, a minimum voltage terminal for outputting a signal having a voltage equal to the lowest voltage among the signals output to the output terminal, and each of the output terminals An output buffer provided to supply an output signal to the output terminal, a low level setting means for forcibly setting the output signal of each output buffer to a low level, and a lowest voltage of the signals output to the output terminals. A minimum voltage detecting means for detecting and outputting the voltage to the minimum voltage terminal. 3. A plurality of output terminals for outputting an output signal to the outside, a maximum voltage terminal for outputting a signal having a voltage equal to the highest voltage among the signals output to the output terminal, and each of the output terminals An output buffer provided to supply an output signal to the output terminal, a second high level setting means for forcibly setting the output signals of the output buffers to a high level in sequence, and output to the output terminals A maximum voltage detecting means for detecting the highest voltage of the signals and outputting the detected voltage to the maximum voltage terminal. 4. A plurality of output terminals for outputting an output signal to the outside, a minimum voltage terminal for outputting a signal having a voltage equal to the lowest voltage among the signals output to the output terminal, and each of the output terminals An output buffer provided to supply an output signal to the output terminal, a second low level setting means for forcibly setting the output signal of each output buffer to a low level in order, and a signal output to each output terminal A minimum voltage detecting means for detecting the lowest voltage and outputting the voltage to the minimum voltage terminal. 5. The semiconductor integrated circuit according to claim 1, wherein the maximum voltage detecting means includes a rectifier provided for each output terminal, and a cathode of each rectifier is connected to the maximum voltage terminal. A semiconductor integrated circuit, wherein an anode of each of the rectifiers is connected to the output terminal. 6. The semiconductor integrated circuit according to claim 3, wherein the maximum voltage detecting means includes a rectifier provided for each of the output terminals, and a cathode of each rectifier is connected to the maximum voltage terminal, A semiconductor integrated circuit, wherein an anode of each of the rectifiers is connected to the output terminal. 7. The semiconductor integrated circuit according to claim 6, wherein the maximum voltage detecting means includes a capacitor connected between the maximum voltage terminal and ground. 8. The semiconductor integrated circuit according to claim 2, wherein the minimum voltage detection unit includes a rectifier provided for each output terminal, and an anode of each rectifier is connected to the minimum voltage terminal, The cathode of each of the rectifiers is connected to the output terminal. 9. The semiconductor integrated circuit according to claim 4, wherein the minimum voltage detection unit includes a rectifier provided for each output terminal, and an anode of each rectifier is connected to the minimum voltage terminal, The cathode of each of the rectifiers is connected to the output terminal. 10. The semiconductor integrated circuit according to claim 9, wherein the minimum voltage detecting means includes a capacitor connected to the minimum voltage terminal and ground.