JPH077264A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH077264A JPH077264A JP14246693A JP14246693A JPH077264A JP H077264 A JPH077264 A JP H077264A JP 14246693 A JP14246693 A JP 14246693A JP 14246693 A JP14246693 A JP 14246693A JP H077264 A JPH077264 A JP H077264A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- resist
- plating
- forming
- surface mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000007747 plating Methods 0.000 claims abstract description 67
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims description 22
- 238000004070 electrodeposition Methods 0.000 claims description 20
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 239000003513 alkali Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 5
- 238000005553 drilling Methods 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 27
- 229910000679 solder Inorganic materials 0.000 description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 9
- 239000000243 solution Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 238000010019 resist printing Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は印刷配線板の製造方法に
関し、特に表面実装用高密度の配線回路を有するスルー
ホール印刷配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed wiring board, and more particularly to a method for manufacturing a through hole printed wiring board having a high density wiring circuit for surface mounting.
【０００２】[0002]
【従来の技術】一般に、スルーホール印刷配線板（以
下、Ｔ／Ｈ ＰＷＢと記す）の製造には、図６（ａ）〜
（ｄ），図７（ａ）〜（ｂ）および図８（ａ）〜
（ｄ），図９（ａ）〜（ｅ）に示す様に、テンティング
工法とパターンめっき工法が多く用いられており、テン
ティング工法によれば、まず、図６（ａ）に示す様に、
絶縁基板２上に銅めっき層を含む導体層１とスルーホー
ル１ａを形成した後、図６（ｂ）に示す様に感光性ドラ
イフィルム５ａをラミネートし、この上から図６（ｃ）
に示す様に、配線回路エッチングレジスト形成用マスク
フィルム４ｃを介して所定の配線回路のパターンを紫外
線で焼き付ける。次に、現像液で未露光部分の感光性ド
ライフィルム５ａを除去し、図６（ｄ）の配線回路部分
のエッチングレジスト６を得る。更に、図７（ａ）に示
す様に、露出した導体層１をエッチング除去した後、最
後に図７（ｂ）に示す様に、配線部分のエッチングレジ
スト６を剥離除去してＴ／Ｈ ＰＷＢを得る。2. Description of the Related Art In general, manufacturing of a through-hole printed wiring board (hereinafter referred to as T / H PWB) is carried out with reference to FIGS.
(D), FIG. 7 (a)-(b) and FIG. 8 (a)-
As shown in (d) and FIGS. 9 (a) to 9 (e), a tenting method and a pattern plating method are often used. According to the tenting method, first, as shown in FIG. 6 (a), ,
After forming the conductor layer 1 including the copper plating layer and the through hole 1a on the insulating substrate 2, the photosensitive dry film 5a is laminated as shown in FIG.
As shown in FIG. 5, a predetermined wiring circuit pattern is printed with ultraviolet rays through the wiring circuit etching resist forming mask film 4c. Next, the photosensitive dry film 5a in the unexposed portion is removed with a developing solution to obtain the etching resist 6 in the wiring circuit portion in FIG. 6D. Further, as shown in FIG. 7A, the exposed conductor layer 1 is removed by etching, and finally, as shown in FIG. 7B, the etching resist 6 on the wiring portion is peeled off to remove the T / H PWB. To get
【０００３】又、パターンめっき工法によれば、まず、
図８（ａ）に示す様に、絶縁基板２上に１次銅めっき層
１ｆを含む導体層１とスルーホール１ａを形成した後、
図８（ｂ）に示す様に、アルカリ現像型耐めっき性ドラ
イフィルム５ｂをラミネートし、この上から図８（ｃ）
に示す様にめっきレジスト形成用マスクフィルム４ｄを
介して所定のめっきレジストパターンを紫外線で焼き付
ける。次に、現像液で未露光部分のアルカリ現像型耐め
っき性ドライフィルム５ｂを除去し、図８（ｄ）に示す
様にめっきレジスト７を得る。更に、図９（ａ）に示す
様に、絶縁基板２上の所定の配線回路部及びスルーホー
ル内に銅めっき（電気めっき）を行い２次銅めっき層１
１を形成する。さらに、図９（ｂ）に示す様に、半田め
っきを行い、エッチングレジストとしての半田めっき層
１２を形成する。その後、図９（ｃ）に示す様に、めっ
きレジスト７を剥離除去した後、図９（ｄ）に示す様
に、露出した導体層１をエッチング除去した後、図９
（ｅ）に示すように、半田めっき層１２を溶解除去して
Ｔ／Ｈ ＰＷＢを得る。According to the pattern plating method, first,
As shown in FIG. 8A, after forming the conductor layer 1 including the primary copper plating layer 1f and the through hole 1a on the insulating substrate 2,
As shown in FIG. 8 (b), an alkali development type plating resistant dry film 5 b is laminated, and FIG.
A predetermined plating resist pattern is baked by ultraviolet rays through the plating resist forming mask film 4d as shown in FIG. Next, the alkali developing type plating resistant dry film 5b in the unexposed portion is removed with a developing solution to obtain a plating resist 7 as shown in FIG. 8 (d). Further, as shown in FIG. 9A, copper plating (electroplating) is performed on a predetermined wiring circuit portion and through holes on the insulating substrate 2 to form a secondary copper plating layer 1
1 is formed. Further, as shown in FIG. 9B, solder plating is performed to form a solder plating layer 12 as an etching resist. After that, as shown in FIG. 9C, the plating resist 7 is peeled and removed, and then the exposed conductor layer 1 is removed by etching as shown in FIG.
As shown in (e), the solder plating layer 12 is dissolved and removed to obtain T / H PWB.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、高密度
回路基板の場合、テンティング工法では絶縁基板全面に
スルーホール信頼性確保に必要なパネル銅めっきを行う
ため絶縁基板内のめっき厚の標準偏差は３μｍ以上であ
り、回路形成時におけるパターン間隙，仕上がり回路幅
寸法のばらつきが大きいという問題点がある。However, in the case of a high-density circuit board, in the tenting method, the standard deviation of the plating thickness in the insulating board is caused because the panel copper plating necessary for ensuring the through hole reliability is performed on the entire surface of the insulating board. The thickness is 3 μm or more, and there is a problem that variations in pattern gaps and finished circuit width dimensions during circuit formation are large.
【０００５】一方、パターンめっき工法においても２次
銅めっき時に所定の回路部のみの電気銅めっきを行うた
め個々の回路パターンの粗の影響により絶縁基板内のめ
っき厚の標準偏差は３μｍ以上であり、テンティング工
法と同様、パターン間隙，仕上がり回路幅寸法のばらつ
きが大きく所定の回路幅／間隙を得ることが困難である
という問題点がある。On the other hand, in the pattern plating method as well, since the electrolytic copper plating of only a predetermined circuit portion is performed during the secondary copper plating, the standard deviation of the plating thickness in the insulating substrate is 3 μm or more due to the influence of the roughness of each circuit pattern. As with the tenting method, there is a problem that it is difficult to obtain a predetermined circuit width / gap because the pattern gap and the finished circuit width dimension vary greatly.
【０００６】本発明の目的は、めっき厚や仕上がり回路
幅寸法のばらつきがなく表面実装用高密度の配線回路を
有する印刷配線板の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a printed wiring board having a high-density wiring circuit for surface mounting without variations in plating thickness and finished circuit width dimension.
【０００７】[0007]
【課題を解決するための手段】本発明の印刷配線板の製
造方法は、銅張積層板の所定の位置に穴あけしてスルー
ホールの穴と非スルーホールの穴を形成する工程と、前
記スルーホールの穴と前記非スルーホールの穴内に導電
性被膜を形成する工程と、前記スルーホールの穴内と前
記非スルーホールの穴内を含む前記銅張積層板の表面上
に電着塗装によりポジ型感光性電着レジストを形成する
工程と、このポジ型感光性電着レジスト面にスルーホー
ルと非スルーホール及びそのランド部と表面実装用パッ
ド部を除くポジパターンの配線回路部形成用マスクフィ
ルムを密着させ紫外線を照射する工程と、現像により露
光部の前記ポジ型感光性電着レジストを選択的に除去し
電着レジストを形成する工程と、アルカリ現像型耐めっ
き性ドライフィルムをラミネートし露光，現像を経て前
記スルーホール及びそのランド部と前記表面実装パッド
部を除いてめっきレジストを形成する工程と、前記ラン
ド部と前記表面実装用パッド部を酸性エッチング液で一
定量の銅をエッチングする工程と、前記スルーホールと
そのランド部と前記表面実装用パッド部に電気めっきを
施し所定の導体層厚を得る工程と、エッチングレジスト
としてめっき層を形成する工程と、前記めっきレジスト
を溶解除去する工程と、露出した銅部分をアルカリエッ
チング液で除去する工程と、更に存在する前記電着レジ
ストを除去する工程とを有する。A method of manufacturing a printed wiring board according to the present invention comprises a step of forming a through hole and a non-through hole at predetermined positions of a copper clad laminate, and the through hole. Forming a conductive coating in the holes and the non-through holes, and positive-type photosensitive by electro-deposition coating on the surface of the copper clad laminate including the through holes and the non-through holes. The process of forming the electro-deposition resist, and the positive-type photosensitive electro-deposition resist surface is closely adhered to the through-hole and non-through-hole, the land part and the mask film for forming the wiring circuit part of the positive pattern excluding the surface mounting pad part. And a step of irradiating ultraviolet rays, a step of selectively removing the positive photosensitive electrodeposition resist in the exposed portion by development to form an electrodeposition resist, and an alkali development type plating resistant dry film Laminating, through exposure and development, a plating resist is formed except the through hole and its land portion and the surface mounting pad portion; and a fixed amount of the land portion and the surface mounting pad portion with an acid etching solution. A step of etching copper, a step of electroplating the through hole, its land portion and the surface mounting pad portion to obtain a predetermined conductor layer thickness, a step of forming a plating layer as an etching resist, and the plating resist Is dissolved and removed, a step of removing the exposed copper portion with an alkaline etching solution, and a step of further removing the existing electrodeposition resist.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００９】図１（ａ）〜（ｄ），図２（ａ）〜
（ｄ），図３（ａ）〜（ｄ）および図４（ａ），（ｂ）
は本発明の第１の実施例の製造方法を説明する工程順に
示した断面図である。第１の実施例は、まず、図２
（ａ）に示す様に、導体厚９〜３５μｍの導体層１を有
する絶縁基板２にスルーホール１ａと非スルーホール１
ｂの穴あけを行った後、図１（ｂ）に示す様に絶縁基板
２の全ての穴内のみに０．１〜３．０μｍの膜厚を有す
る導電性被膜３を形成する。導電性被膜３としてはポリ
ピロール等の五員環誘導体で形成される導電性ポリマー
やパラジュームを核とするＰｄＳ等を用いることができ
る。1A to 1D and 2A to 2A.
(D), FIG. 3 (a)-(d) and FIG. 4 (a), (b)
3A to 3D are sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps. First, the first embodiment will be described with reference to FIG.
As shown in (a), a through hole 1 a and a non-through hole 1 are formed in an insulating substrate 2 having a conductor layer 1 having a conductor thickness of 9 to 35 μm.
After drilling b, a conductive coating film 3 having a film thickness of 0.1 to 3.0 μm is formed only in all the holes of the insulating substrate 2 as shown in FIG. As the conductive coating 3, a conductive polymer formed of a 5-membered ring derivative such as polypyrrole or PdS having palladium as a nucleus can be used.
【００１０】次に、図１（ｃ）に示す様に、スルーホー
ル１ａを含む絶縁基板２全面に電着塗装によりポジ型感
光性電着レジスト８をコーティングし乾燥を経て均一な
感光膜とする。さらに、図１（ｄ）に示す様に感光性電
着レジスト８面にポジ型のスルーホール１ａと非スルー
ホール１ｂとそのランド部及び表面実装用パッド部を除
く配線回路部形成用マスクフィルム４ａを密着し紫外線
９により露光する。次いで、図２（ａ）に示す様に、配
線回路部形成用マスクフィルム４ａを取り外し露光され
た部分のポジ型感光性電着レジスト８を１〜３ｗｔ％の
Ｎａ2 ＣＯ3 やＮａ2 ＳｉＯ3 等のアルカリ現像液で除
去し、電着レジスト残膜１０を得る。続いて、図２
（ｂ）に示すごとく、絶縁基板２表面全体にアルカリ現
像型耐めっき性ドライフィルム５ｂをラミネートし、図
２（ｃ）に示す様に、スルーホールとランド部及び表面
実装用パッド部めっき様マスクフィルム４ｂを介して露
光，現像した後、図２（ｄ）に示す様に、未露光部分の
アルカリ現像型耐めっき性ドライフィルム５ｂを除去
し、全てのスルーホール１ａとそのランド部及び表面実
装用パッド部以外にめっきレジスト７を形成する。さら
に、図３（ａ）に示す様に、ランド部表面を酸性のエッ
チング液で８〜２５μｍエッチング処理した後、図３
（ｂ）に示す様に、２次銅めっきとしてスルーホール１
ａとそのランド部及び表面実装用パッド部に１５〜２０
μｍの電気銅めっきを施し２次銅めっき層１１を形成す
る。これらの工程により、導体厚はトータルで１６〜３
０μｍに抑えることができ、また導体層厚のばらつきも
標準偏差で１．５μｍ以下にすることができる。Next, as shown in FIG. 1 (c), a positive type photosensitive electrodeposition resist 8 is coated on the entire surface of the insulating substrate 2 including the through holes 1a by electrodeposition coating and dried to form a uniform photosensitive film. . Further, as shown in FIG. 1D, a mask film 4a for forming a wiring circuit portion excluding the positive through hole 1a, the non-through hole 1b, the land portion and the surface mounting pad portion on the surface of the photosensitive electrodeposition resist 8 And are exposed to ultraviolet rays 9. Next, as shown in FIG. 2 (a), the mask film 4a for forming the wiring circuit portion is removed and the exposed positive photosensitive electrodeposition resist 8 is exposed to 1 to 3 wt% of Na 2 CO 3 or Na 2 SiO 3. The residual film 10 for electrodeposition resist is obtained by removing with an alkaline developer such as. Then, FIG.
As shown in FIG. 2B, an alkali development type plating resistant dry film 5b is laminated on the entire surface of the insulating substrate 2 and, as shown in FIG. After exposure and development through the film 4b, as shown in FIG. 2D, the alkali development type plating resistant dry film 5b in the unexposed portion is removed, and all the through holes 1a and their lands and surface mounting. The plating resist 7 is formed on the portion other than the pad portion. Furthermore, as shown in FIG. 3A, after the surface of the land portion is subjected to an etching treatment with an acidic etching solution for 8 to 25 μm,
As shown in (b), the through hole 1 is used as the secondary copper plating.
a to the land portion and the pad portion for surface mounting 15 to 20
Electrolytic copper plating of μm is applied to form a secondary copper plating layer 11. Through these steps, the total conductor thickness is 16 to 3
The thickness can be suppressed to 0 μm, and the variation in conductor layer thickness can be 1.5 μm or less in standard deviation.
【００１１】次に、図３（ｃ）に示す様に、スルーホー
ル１ａとそのランド部及び表面実装用パッド部のエッチ
ングレジストとして５〜２５μｍの半田めっきを施し半
田めっき層１２を形成する。その後、図３（ｄ）に示す
様に、めっきレジスト７を１〜３％のＮａ2 ＣＯ3 等の
溶液で除去した後、続いて、図４（ａ）に示す様に、露
出した銅部分をアルカリ性のエッチング液により除去
し、続いて、図４（ｂ）に示す様に、回路部の電着レジ
スト残膜１０を１〜４ｗｔ％のＮａＯＨまたは、ＫＯＨ
等の温水溶液で剥離除去し所定の配線回路１ｃを有する
Ｔ／Ｈ ＰＷＢを得る。Next, as shown in FIG. 3C, a solder plating layer 12 is formed by applying solder plating of 5 to 25 μm as an etching resist for the through hole 1a and its land portion and surface mounting pad portion. After that, as shown in FIG. 3D, the plating resist 7 is removed with a solution such as Na 2 CO 3 of 1 to 3%, and subsequently, as shown in FIG. Is removed by an alkaline etching solution, and subsequently, as shown in FIG. 4 (b), the electrodeposition resist residual film 10 in the circuit portion is covered with 1 to 4 wt% of NaOH or KOH.
The T / H PWB having a predetermined wiring circuit 1c is obtained by peeling and removing with a warm aqueous solution.
【００１２】図５は本発明の第２の実施例による印刷配
線板の断面図である。第２の実施例は、図５に示すよう
に、図４（ｂ）に示す第１の実施例のスルーホール１ａ
とそのランド部及び表面実装用パッド部のエッチングレ
ジストとして用いた半田めっき層１２に代えて１．５〜
５μｍのニッケルめっき層１３上に０．０５〜３μｍの
金めっき層１４を形成した例で、ニッケルめっき層１３
と金めっき層１４を用いることもできる。FIG. 5 is a sectional view of a printed wiring board according to the second embodiment of the present invention. In the second embodiment, as shown in FIG. 5, the through hole 1a of the first embodiment shown in FIG. 4B is used.
In place of the solder plating layer 12 used as the etching resist for the land portion and the pad portion for surface mounting, 1.5 to
In the example in which the gold plating layer 14 of 0.05 to 3 μm is formed on the nickel plating layer 13 of 5 μm, the nickel plating layer 13
The gold plating layer 14 can also be used.
【００１３】以上の様に、本実施例では、スルーホール
とそのランド部及び表面実装用パッド部のエッチングレ
ジストして、半田めっき及びニッケル＋金めっきを用い
ることができる為、表面実装用Ｔ／Ｈ ＰＷＢに対し、
従来工法でソルダーレジスト印刷後実施していたスルー
ホールとそのランド部及び表面実装用パッド部のみの無
電解半田めっき或は、無電解ニッケル＋金めっき工程が
不要となり、下記の効果が得られる。As described above, in this embodiment, solder plating and nickel + gold plating can be used as the etching resist for the through hole, the land portion thereof, and the surface mounting pad portion. For HPWB,
The electroless solder plating or electroless nickel + gold plating step of only the through hole and its land portion and the pad portion for surface mounting, which has been performed after the solder resist printing by the conventional method, is unnecessary, and the following effects are obtained.
【００１４】（１）従来工法でめっき時に起こるソルダ
ーレジスト膜の剥離不良がなくなる。(1) The peeling defect of the solder resist film that occurs during plating by the conventional method is eliminated.
【００１５】（２）めっき処理を電気めっき工程で実施
出来るため、従来の無電解めっき工法よりも３０〜５０
％コスト低減できる。(2) Since the plating treatment can be carried out in the electroplating step, it is 30 to 50 as compared with the conventional electroless plating method.
% Cost reduction.
【００１６】[0016]
【発明の効果】前述した様に本発明によれば、導体層の
一定量の銅をエッチング処理した後、電気銅めっきを施
し２次銅めっき層を形成し導体層厚のばらつきを最小に
押さえたので所定の回路パターン部における導体厚の標
準偏差が３μｍ以上から１．５μｍ以下に低減できるた
め、従来のテンティング工法及びパターンめっき工法よ
りも下記の効果がある。As described above, according to the present invention, after etching a certain amount of copper in the conductor layer, electrolytic copper plating is performed to form a secondary copper plating layer to minimize variations in the conductor layer thickness. Therefore, since the standard deviation of the conductor thickness in the predetermined circuit pattern portion can be reduced from 3 μm or more to 1.5 μm or less, the following effects are obtained as compared with the conventional tenting method and pattern plating method.
【００１７】（１）テンティング工法では形成困難であ
った微小ランドスルーホールの形成が容易にできる。(1) It is possible to easily form minute land through holes, which were difficult to form by the tenting method.
【００１８】（２）パターンめっき厚のばらつき低減に
より表面実装技術への対応が図れる。(2) It is possible to cope with surface mounting technology by reducing the variation in pattern plating thickness.
【００１９】（３）導体厚の標準偏差低減により、配線
幅＝７５μｍ，配線間隙＝１００μｍの回路密度の回路
不良率が２０％から３％に低減できる。(3) By reducing the standard deviation of the conductor thickness, the circuit defect rate with a circuit density of wiring width = 75 μm and wiring gap = 100 μm can be reduced from 20% to 3%.
【００２０】（４）従来工法でめっき次に起こるソルダ
ーレジスト膜の剥離不良がなくなる。(4) Plating by the conventional method The peeling defect of the solder resist film which occurs next is eliminated.
【００２１】（５）めっき処理を電気めっき工法で実施
出来るため、従来の無電解めっき工法よりも３０〜５０
％コスト低減できる。(5) Since the plating treatment can be carried out by the electroplating method, it is 30 to 50 as compared with the conventional electroless plating method.
% Cost reduction.
【００２２】さらに、本発明では、非スルーホールとな
る穴にはめっきを行わない為、従来の製造方法で回路形
成後行っていた二次穴明け工程が削除できる。Further, according to the present invention, since the holes which are not the through holes are not plated, the secondary drilling step which is carried out after the circuit is formed by the conventional manufacturing method can be eliminated.
【図１】（ａ）〜（ｄ）は本発明の第１の実施例を説明
する工程順に示した断面図である。FIG. 1A to FIG. 1D are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention.
【図２】（ａ）〜（ｄ）は本発明の第１の実施例を説明
する工程順に示した断面図である。2 (a) to 2 (d) are sectional views showing the first embodiment of the present invention in process order.
【図３】（ａ）〜（ｄ）は本発明の第１の実施例を説明
する工程順に示した断面図である。3 (a) to 3 (d) are sectional views showing the first embodiment of the present invention in the order of steps.
【図４】（ａ），（ｂ）は本発明の第１の実施例を説明
する工程順に示した断面図である。4A and 4B are cross-sectional views showing the first embodiment of the present invention in the order of steps.
【図５】本発明の第２の実施例による印刷配線板の断面
図である。FIG. 5 is a sectional view of a printed wiring board according to a second embodiment of the present invention.
【図６】（ａ）〜（ｄ）は従来のテンティング工法によ
る印刷配線板の製造方法の一例を説明する工程順に示し
た断面図である。6A to 6D are cross-sectional views showing the order of steps for explaining an example of a method for manufacturing a printed wiring board by a conventional tenting method.
【図７】（ａ），（ｂ）は従来のテンティング工法によ
る印刷配線板の製造方法の一例を説明する工程順に示し
た断面図である。7 (a) and 7 (b) are cross-sectional views showing the order of steps for explaining an example of a method for manufacturing a printed wiring board by a conventional tenting method.
【図８】（ａ）〜（ｄ）は従来のパターンめっき工法に
より印刷配線板の製造方法の一例を示す工程順に示した
断面図である。8A to 8D are cross-sectional views showing an example of a method of manufacturing a printed wiring board by a conventional pattern plating method in the order of steps.
【図９】（ａ）〜（ｅ）は従来のパターンめっき工法に
よる印刷配線板の製造方法の引例を示す工程順に示した
断面図である。9A to 9E are cross-sectional views showing, in the order of steps, a reference of a method for manufacturing a printed wiring board by a conventional pattern plating method.
１ 導体層 １ａ スルーホール １ｂ 非スルーホール １ｃ 配線回路 １ｄ スルーホールランド １ｅ 表面実装用パッド １ｆ １次銅めっき層 ２ 絶縁基板 ３ 導電性被膜 ４ａ 配線回路部形成用マスクフィルム ４ｂ スルーホールとランド部及び表面実装用パッド
部めっき用マスクフィルム ４ｃ 配線回路部エッチングレジスト形成用マスクフ
ィルム ４ｄ めっきレジスト形成用マスクフィルム ５ａ 感光性ドライフィルム ５ｂ アルカリ現像型耐めっき性ドライフィルム ６ 配線回路部分のエッチングレジスト ７ めっきレジスト ８ 感光性電着レジスト ９ 紫外線 １０ 電着レジスト残膜 １１ ２次銅めっき層 １２ 半田めっき層 １３ ニッケルめっき層 １４ 金めっき層DESCRIPTION OF SYMBOLS 1 conductor layer 1a through hole 1b non-through hole 1c wiring circuit 1d through hole land 1e surface mounting pad 1f primary copper plating layer 2 insulating substrate 3 conductive coating 4a wiring film forming mask film 4b through hole and land portion and Surface mounting pad masking film 4c Wiring circuit part etching resist forming mask film 4d Plating resist forming mask film 5a Photosensitive dry film 5b Alkali development type plating resistant dry film 6 Wiring circuit part etching resist 7 Plating resist 8 Photosensitive Electrodeposition Resist 9 Ultraviolet 10 Electrodeposition Resist Residual Film 11 Secondary Copper Plating Layer 12 Solder Plating Layer 13 Nickel Plating Layer 14 Gold Plating Layer
Claims (1)
ルーホールの穴と非スルーホールの穴を形成する工程
と、前記スルーホールの穴と前記非スルーホールの穴内
に導電性被膜を形成する工程と、前記スルーホールの穴
内と前記非スルーホールの穴内を含む前記銅張積層板の
表面上に電着塗装によりポジ型感光性電着レジストを形
成する工程と、このポジ型感光性電着レジスト面にスル
ーホールと非スルーホール及びそのランド部と表面実装
用パッド部を除くポジパターンの配線回路部形成用マス
クフィルムを密着させ紫外線を照射する工程と、現像に
より露光部の前記ポジ型感光性電着レジストを選択的に
除去し電着レジストを形成する工程と、アルカリ現像型
耐めっき性ドライフィルムをラミネートし露光，現像を
経て前記スルーホール及びそのランド部と前記表面実装
パッド部を除いてめっきレジストを形成する工程と、前
記ランド部と前記表面実装用パッド部を酸性エッチング
液で一定量の銅をエッチングする工程と、前記スルーホ
ールとそのランド部と前記表面実装用パッド部に電気め
っきを施し所定の導体層厚を得る工程と、エッチングレ
ジストとしてめっき層を形成する工程と、前記めっきレ
ジストを溶解除去する工程と、露出した銅部分をアルカ
リエッチング液で除去する工程と、更に存在する前記電
着レジストを除去する工程とを有することを特徴とする
印刷配線板の製造方法。1. A step of forming a through hole and a non-through hole by drilling holes at predetermined positions of a copper clad laminate, and a conductive coating film in the through hole and the non-through hole. A step of forming, a step of forming a positive photosensitive electrodeposition resist by electrodeposition coating on the surface of the copper clad laminate including the inside of the through hole and the inside of the non-through hole, and the positive photosensitive A step of irradiating with ultraviolet rays by bringing a mask film for forming a wiring circuit portion of a positive pattern excluding the through hole and the non-through hole and its land portion and the surface mounting pad portion into close contact with the electrodeposition resist surface, and developing Through the step of selectively removing the photo-sensitive electro-deposition resist to form the electro-deposition resist, and laminating an alkali development type plating resistant dry film, exposing and developing the film. And a step of forming a plating resist excluding the land portion and the surface mounting pad portion, a step of etching a fixed amount of copper in the land portion and the surface mounting pad portion with an acid etching solution, and the through hole A step of electroplating the land portion and the surface mounting pad portion to obtain a predetermined conductor layer thickness, a step of forming a plating layer as an etching resist, a step of dissolving and removing the plating resist, and an exposed copper portion And a step of removing the existing electrodeposition resist, and a method of manufacturing a printed wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14246693A JPH077264A (en) | 1993-06-15 | 1993-06-15 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14246693A JPH077264A (en) | 1993-06-15 | 1993-06-15 | Manufacture of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH077264A true JPH077264A (en) | 1995-01-10 |
Family
ID=15315976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14246693A Withdrawn JPH077264A (en) | 1993-06-15 | 1993-06-15 | Manufacture of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077264A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998007302A1 (en) * | 1996-08-09 | 1998-02-19 | Matsushita Electric Works, Ltd. | Method for plating independent conductor circuit |
| WO1998031204A1 (en) * | 1997-01-10 | 1998-07-16 | Ibiden Co., Ltd. | Printed wiring board and method of manufacturing the same |
| US6518513B1 (en) | 1997-06-06 | 2003-02-11 | Ibiden Co. Ltd. | Single-sided circuit board and method for manufacturing the same |
| JP2009088334A (en) * | 2007-10-01 | 2009-04-23 | Nippon Mektron Ltd | Printed circuit board manufacturing method |
-
1993
- 1993-06-15 JP JP14246693A patent/JPH077264A/en not_active Withdrawn
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998007302A1 (en) * | 1996-08-09 | 1998-02-19 | Matsushita Electric Works, Ltd. | Method for plating independent conductor circuit |
| GB2321908A (en) * | 1996-08-09 | 1998-08-12 | Matsushita Electric Works Ltd | Method for plating independent conductor circuit |
| GB2321908B (en) * | 1996-08-09 | 2000-08-30 | Matsushita Electric Works Ltd | Process of plating on isolated conductor circuit |
| WO1998031204A1 (en) * | 1997-01-10 | 1998-07-16 | Ibiden Co., Ltd. | Printed wiring board and method of manufacturing the same |
| US6284353B1 (en) | 1997-01-10 | 2001-09-04 | Ibiden Co., Ltd. | Printed wiring board and method of manufacturing the same |
| US6986917B2 (en) | 1997-01-10 | 2006-01-17 | Ibiden Co., Ltd. | Printed wiring board and method of manufacturing the same |
| US7594320B2 (en) | 1997-01-10 | 2009-09-29 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board |
| US7765692B2 (en) | 1997-01-10 | 2010-08-03 | Ibiden Co., Ltd. | Method of manufacturing printed wiring board |
| US6518513B1 (en) | 1997-06-06 | 2003-02-11 | Ibiden Co. Ltd. | Single-sided circuit board and method for manufacturing the same |
| US7721427B2 (en) | 1997-06-06 | 2010-05-25 | Ibiden Co., Ltd. | Method for manufacturing single sided substrate |
| JP2009088334A (en) * | 2007-10-01 | 2009-04-23 | Nippon Mektron Ltd | Printed circuit board manufacturing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000905 |