JPH0772949A - Pulse supply device - Google Patents

Abstract

(57) [Abstract] [Purpose] Time division multiplexing is performed even if the phase difference between the clock signals CK generated at the output terminals of the clock generators A and B is set to zero and the switch 1 switches the connection terminal from the terminal a to the terminal b. A pulse supply device capable of outputting a clock signal CK to be supplied to the device without distortion. A means for generating a clock signal of a required cycle based on a master clock signal of a predetermined cycle, and n of a frequency divider for dividing this clock signal into 1 / n (where n is an integer)
In a pulse supply device which is provided with a plurality of clock generators each including a binary counter, and which outputs a clock signal generated by one clock generator selected from these clock generators to the outside, the selected clock Each of the above means is provided with means for generating a pulse signal for resetting the counter of another clock generator each time the generator reaches a predetermined count value before counting n, and means for delaying the pulse signal. The phase difference between the clock signals generated by the clock generator is set to zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse supply device for supplying a clock signal having a required period to an external device.

[0002]

2. Description of the Related Art Conventionally, a time-division multiplexer for a public line, which modulates and multiplexes a plurality of signals to be transmitted with clock signals having different phases, always maintains a normal operation.
There is a case where a pulse supply device as shown in FIG. 3 is used. That is, this pulse supply device is for supplying one of the clock signals having different phases to the time division multiplexing device, and is different from the clock signal output by another pulse supply device (not shown). Clock signals CK having different phases are generated by a clock generator A and a clock generator B equivalent thereto, and are supplied to terminals a and b of the switch 1. In addition, the switch 1 normally connects the terminal c to the terminal a, and when the controller 2 detects an abnormality in the output clock signal of the clock generator A, switches the terminal c to the terminal b so that the terminal c Always outputs a normal clock signal to reduce the abnormal operation occurrence rate of the time division multiplexer due to the failure of the clock generator A.

Further, this pulse supply device and the other pulse supply devices need to synchronize the clock signals output from each other with each other and to shift the phases of these clock signals from each other. Therefore, as shown in FIG. Generator A is
An oscillator in which a phase-locked loop circuit (hereinafter referred to as PLL) A1 and a frequency divider A2 for dividing the output clock signal thereof into 1 / n (where n is an integer) are combined, and the clock generator B is Each of the oscillators has a combination of the PLLB1 and the frequency divider B2, and generates a desired clock signal CK based on the master clock signal MK supplied commonly to all the pulse supply devices. Therefore, PLLA1 and B
1 When the switching device 1 switches the connection terminal from the terminal a to the terminal b, the phases of the clock signals generated by the clock generators A and B are deviated from each other due to the difficulty of making the characteristics of each other the same. Clock signal CK generated at terminal c
May be distorted. Therefore, the conventional pulse supply device connects the reset circuit 3 between the output terminal of the frequency divider A2 and the reset terminal of the frequency divider B2, and the frequency divider A generates the clock signal CK in the reset circuit 3. By generating a pulse signal for resetting the n-ary counter inside the frequency divider B2 for each time, the phases of the clock signals CK generated at the output ends of the clock generators A and B are synchronized with each other, and the time division multiplexing apparatus. The distortion of the clock signal CK to be supplied to is prevented.

However, in such a pulse supply device, the reset circuit 3 generates the pulse signal after detecting the generation of the clock signal CK output from the frequency divider A2, and the frequency divider A2 outputs the clock signal CK. Since it is impossible to make the time required for the reset circuit 3 to generate a pulse signal from zero after generating the clock signal, the phases of the clock signals CK generated at the output terminals of the clock generators A and B are shifted from each other. Therefore, the distortion of the clock signal CK to be supplied to the time division multiplexer cannot be completely prevented.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional pulse supplying device as described above.
Even if the phase difference between the clock signals CK generated at the output ends of the clock generators A and B is set to zero and the switch 1 switches the connection terminal from the terminal a to the terminal b, the clock signal CK to be supplied to the time division multiplexer is supplied. An object of the present invention is to provide a pulse supply device capable of outputting without distortion.

[0006]

SUMMARY OF THE INVENTION To achieve the above object, a pulse supply device of the present invention has a means for generating a clock signal of a required cycle based on a master clock signal of a predetermined cycle, and divides this clock signal into 1 / n. A pulse supply device which is provided with a plurality of clock generators each having an n-ary counter, selects one of the clock generators, and outputs the clock signal generated by the selected clock generator to the outside. Means for generating a pulse signal for resetting the counter of another clock generator each time the selected clock generator reaches a predetermined count value before counting n, and means for delaying the pulse signal. And.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of the pulse supply device of the present invention. In the figure, the clock generator A includes a PLLA1 and a frequency divider A2, and the clock generator B includes a PLLB1 and a frequency divider B2. Further, the clock generators A and B, the switch 1 and the controller 2 are connected in the same manner as in the conventional pulse supply device shown in FIG. Further, the count value output terminal of the frequency divider A2 is connected to the reset terminal of the frequency divider B2 via the count judging device 4 and the delay circuit 5, and the clock signal CK to be supplied to the external device from the terminal c of the switching device 1. Is configured to output.

The pulse supply device configured as described above operates as follows. That is, in this pulse supply device, the n-ary counter inside the frequency divider A2 counts the number of pulses of the output clock signal of the PLLA1, and resets the count value to zero each time the count value becomes n, and also the predetermined pulse A signal is generated to generate a clock signal CK. In addition, the count value of the n-ary counter in the frequency divider A2 is (n-
A pulse signal for resetting the n-ary counter in the frequency divider B2 is generated every time 1). Further, when it takes τ [sec] from the count determination unit 4 to generate the pulse signal until the frequency divider A2 generates the pulse signal, the delay circuit 5 is used to output the output pulse signal of the count determination unit 4. τ [se
c] Delay.

Therefore, according to this pulse supply device, as shown in FIG.
Since it is difficult to make the characteristics of PLLA1 and B1 identical to each other as shown in FIG. 3, the timings at which the count values of the n-ary counters inside the frequency dividers A2 and B2 become zero are t ₀ [sec. ] Even if it takes t ₁ [sec] until the count judging unit 4 generates the reset pulse signal after the shift or the n-ary counter inside the frequency divider A2 becomes zero,
The delay circuit 5 has an n-ary counter (n-
Since the reset pulse signal is output after (t ₁ + τ) [sec] after counting 1), the phase difference between the output clock signals CK of the clock generators A and B can be made zero.

In the above-described embodiment, the count judging device 4 generates a pulse signal every time the count value of the n-ary counter in the counter A2 becomes (n-1), and the delay circuit 5 outputs the pulse signal to τ. Although it is delayed by [sec], the present invention is not limited to this, and the count judging device 4 generates a pulse signal each time the n-ary counter reaches a count value before counting n, and the clock generator A
If the delay amount of the delay circuit 5 is set to an arbitrary value so that the output pulse signal of the counting and judging device 4 is supplied to the counter B2 at the timing necessary to synchronize the phases of the output clock signals CK of B and B with each other. good.

Further, in the above-mentioned embodiment, the number of pulse supply devices is two.
Although one clock generator is provided, the present invention is not limited to this, and a plurality of clock generators are provided, and one clock generator that operates normally is selected from these clock generators. Every time the binary counter reaches the count value before counting n, a pulse signal for resetting the n-ary counter in another clock generator is generated by the count judging device, and the pulse signal is delayed by the delay circuit. The phase difference between the clock signals generated by the clock generators may be zero.

[0012]

As described above, the present invention selects one that operates normally from a plurality of clock generators, and the n-ary counter in the selected clock generator counts n before counting. Whenever a numerical value is reached, a pulse signal for resetting the n-ary counter in another clock generator is generated by the count judging device, and the pulse signal is delayed by the delay circuit, so that the count judging device outputs a predetermined count value. Even if it takes time from the detection to the output of the reset pulse signal, the time required for the delay circuit to output the reset pulse signal after the selected clock generator generates the predetermined clock signal Can be zero. Therefore, according to the present invention, since the phase difference between the clock signals generated by each of the plurality of clock generators can be made zero, the clock generated when switching from the selected clock generator to another clock generator. There is a remarkable effect in removing a signal distortion and providing a pulse supply device which can always supply a normal clock signal to an external device.

[0013]

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a pulse supply device of the present invention.

FIG. 2 is a diagram for explaining a pulse supply device of the present invention.

FIG. 3 is a configuration diagram showing a conventional pulse supply device.

[Explanation of symbols]

1 switching device, 2 controller, 4 counting judgment device, 5 delay circuit, A and B clock generator, A1 and B1 PL
L, A2 and B2 dividers.

Claims (1)

[Claims] 1. A means for generating a clock signal of a required cycle based on a master clock signal of a predetermined cycle, and an n-ary counter of a frequency divider for dividing this clock signal into 1 / n (where n is an integer). And a plurality of clock generators with
In a pulse supply device which outputs a clock signal generated by one clock generator selected from these clock generators to the outside, a predetermined count value before the selected clock generator counts n Each time, a means for generating a pulse signal for resetting the counter of another clock generator and a means for delaying the pulse signal are provided to detect the phase difference between the clock signals generated by the clock generators. A pulse supply device characterized by zero.