JPH0773095B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0773095B2 JPH0773095B2 JP60181096A JP18109685A JPH0773095B2 JP H0773095 B2 JPH0773095 B2 JP H0773095B2 JP 60181096 A JP60181096 A JP 60181096A JP 18109685 A JP18109685 A JP 18109685A JP H0773095 B2 JPH0773095 B2 JP H0773095B2
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- growth
- lspe
- heat treatment
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000000034 method Methods 0.000 title description 8
- 238000004519 manufacturing process Methods 0.000 title description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 20
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、非晶質シリコンおよび多結晶シリコンの横方
向固相エピタキシヤル成長（LSPE成長）を用いたSOI（S
emiConductor on Insulator）構造を有する半導体素子
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to SOI (SPE) using lateral solid phase epitaxial growth (LSPE growth) of amorphous silicon and polycrystalline silicon.
The present invention relates to a method for manufacturing a semiconductor device having an emiConductor on Insulator) structure.
（従来の技術） 第３図は例えば〔FED SOI/3D WORKSHOP〕,March,19-21
1985 P69-74の特にP74,Fig5〜８に示された従来の非晶
質シリコンのLSPE成長によるSOI構造の単結晶シリコン
の形成を示すもので、パターニングした絶縁膜（12）を
有するSi基板（11）上に堆積した非晶質シリコン（13）
に600℃程度の熱処理を行なうと、Si基板（11）を種結
晶として垂直方向固相エピタキシャル成長（VSPE成長）
（14）を行なった後、絶縁膜（12）上にLSPE成長（15）
を行なう。(Prior Art) FIG. 3 shows, for example, [FED SOI / 3D WORKSHOP], March, 19-21.
1985 P69-74, in particular P74, shows formation of single crystal silicon of SOI structure by conventional LSPE growth of amorphous silicon as shown in Figs. 11) Amorphous silicon deposited on (13)
Vertically solid phase epitaxial growth (VSPE growth) using the Si substrate (11) as a seed crystal when heat treatment is performed at about 600 ℃
After performing (14), LSPE growth (15) on the insulating film (12)
Do.
第２図はLSPE成長長さの熱処理時間依存性を示すグラフ
で、熱処理初期においてVSPE成長に要する遅れ時間後、
非晶質シリコンの多結晶化により単結晶成長できなくな
るまでLSPE成長を遂げる。なお、VSPE成長の遅れ時間
（26）は、LSPE成長よりVSPE成長が優先的に生じるため
におこる。また熱処理時間は5.5時間をこえると多結晶
化（27）されるので、この時間内にいかにLSPE成長させ
るかにある。すなわち、VSPE成長時間分を押えてLSPE成
長にその分当てるものである。Figure 2 is a graph showing the heat treatment time dependence of the LSPE growth length. After the delay time required for VSPE growth at the beginning of heat treatment,
LSPE growth is achieved until single crystal growth becomes impossible due to the polycrystallization of amorphous silicon. The delay time (26) of VSPE growth occurs because VSPE growth takes precedence over LSPE growth. If the heat treatment time exceeds 5.5 hours, it will be polycrystallized (27), so it depends on how to grow the LSPE within this time. That is, the VSPE growth time is suppressed and the LSPE growth is applied accordingly.
（発明が解決しようとする問題点） しかしながら、上記の製造方法ではLSPE成長長さは多結
晶化によって制限され最大５μ程度であり、５μm2以上
のSOI層の形成ができない問題点があった。(Problems to be Solved by the Invention) However, in the above-described manufacturing method, the LSPE growth length is limited to about 5 μ at maximum due to polycrystallization, and there is a problem that an SOI layer of 5 μm 2 or more cannot be formed.
この発明は従来技術が持っていた所定面積以上のSOI層
の形成ができない点を解決し、より多くの半導体素子の
形成が可能で、言い換えればSOI層面積を拡大する方法
を提供するものである。The present invention solves the problem that the conventional technology cannot form an SOI layer having a predetermined area or more, and enables the formation of a larger number of semiconductor elements. In other words, it provides a method for expanding the SOI layer area. .
（問題点を解決するための手段） この発明は前記問題点を解決するため、非晶質シリコン
のLSPE成長によりSOI構造を形成する際、非晶質シリコ
ン膜厚を絶縁膜上よりも薄くする工程を行なうものであ
る。(Means for Solving the Problems) In order to solve the above problems, the present invention makes the thickness of the amorphous silicon thinner than that on the insulating film when forming the SOI structure by LSPE growth of the amorphous silicon. It is a process.
（作用） この発明によれば、LSPE成長によるSOI層の形成方法に
おいて、パターニングした絶縁膜を有するSi基板上に堆
積した非晶質シリコンのうち、Si基板上の非晶質シリコ
ンの膜厚を薄くすることにより、VSPE成長についやされ
る時間を抑え、LSPE成長に移行する時間を早まらせて多
結晶化がおこらない処理時間内にLSPE成長を進行させる
ものである。(Operation) According to the present invention, in the method for forming an SOI layer by LSPE growth, among amorphous silicon deposited on a Si substrate having a patterned insulating film, the film thickness of the amorphous silicon on the Si substrate is By making it thin, the time taken for VSPE growth is suppressed, the time for transition to LSPE growth is accelerated, and LSPE growth proceeds within the processing time during which polycrystallization does not occur.
（実施例） 第１図（ａ）〜（ｄ）はこの発明のSOI層形成工程を示
すもので、まず、第１図（ａ）に示すようにSi（100）
基板（31）に500Å程度の熱酸化膜（32）を形成したの
ち、ホトリソグラフイおよびエツチング技術によりパタ
ーニングを行なう。その後、上記基板（31）をHCl:H
2O2：H2Oが1:1:6の割合の洗浄液にて化学洗浄を行な
い、超高真空内に導入し850℃で５分以上の高温加熱ク
リーニングを行ない洗浄表面を形成し、引続き電子ビー
ム蒸着により膜厚0.6μｍ以上の非晶質シリコン（33）
を表面に堆積する。さらに450℃で30分程度の熱処理を
行なって（ｂ）に示す非晶質シリコンの緻密化を行な
う。その後、（ｃ）に示すように種結晶上の非晶質シリ
コン（33）をホトリソエツチングにより薄くし、概ね熱
酸化膜（32）の膜厚の２倍以下、実施例では膜厚1000Å
とした。次にN2雰囲気中で600℃程度の熱処理を行な
い、LSPE成長させて（ｄ）に示すように単結晶化したSO
I領域（34）に従来の工程により半導体素子を形成す
る。(Example) FIGS. 1 (a) to 1 (d) show an SOI layer forming step of the present invention. First, as shown in FIG. 1 (a), Si (100)
After forming a thermal oxide film (32) of about 500Å on the substrate (31), patterning is performed by photolithography and etching techniques. Then, the substrate (31) is treated with HCl: H.
2 O 2 : H 2 O was chemically cleaned with a cleaning solution at a ratio of 1: 1: 6, introduced into an ultra-high vacuum and heated at 850 ° C. for 5 minutes or more to form a cleaned surface. Amorphous silicon with a film thickness of 0.6 μm or more by electron beam evaporation (33)
Are deposited on the surface. Further, heat treatment is performed at 450 ° C. for about 30 minutes to densify the amorphous silicon shown in (b). Thereafter, as shown in (c), the amorphous silicon (33) on the seed crystal is thinned by photolithography, and is approximately twice the film thickness of the thermal oxide film (32) or less than 1000 Å in the embodiment.
And Then, heat treatment is performed at about 600 ° C. in an N 2 atmosphere to grow LSPE, and the single crystallized SO as shown in FIG.
A semiconductor element is formed in the I region (34) by a conventional process.
（発明の効果） 以上詳細に説明したように本発明によれば、SOI構造を
形成する際、種結晶上の非晶質シリコン膜厚を薄くした
ので、熱処理初期の遅れ時間が短かくなり、非晶質シリ
コンの多結晶化によって制限されるまでにより長くLSPE
成長を行なうことができる。また本発明では非晶質シリ
コンの膜厚を6000Å〜1000Åと1/6に減少したので、第
２図の鎖線で示すように実線位置が平行移動すると考え
られるのでSOI層が５〜６μm2と44％の面積の拡大が図
れる。(Effects of the Invention) According to the present invention as described in detail above, since the amorphous silicon film thickness on the seed crystal is thinned when the SOI structure is formed, the delay time in the initial heat treatment becomes short, Longer LSPE until limited by polycrystallization of amorphous silicon
Can grow. Since the present invention reduced the thickness of the amorphous silicon 6000Å~1000Å and 1/6, since the solid line position as shown by the chain line in Figure 2 is considered to be translated SOI layer and 5 to 6 .mu.m 2 The area can be expanded by 44%.
第１図（ａ）〜（ｄ）は本発明によるSOI層形成工程
図、第２図はLSPE成長長さの熱処理時間依存性を示す特
性グラフ、第３図は従来による非晶質シリコンのLSPE成
長によるSOI構造の形成を示す図である。 （31）……Si基板、（32）……絶縁膜パターン、（33）
……非晶質シリコン、（34）……SOI層。1 (a) to 1 (d) are process diagrams for forming an SOI layer according to the present invention, FIG. 2 is a characteristic graph showing the heat treatment time dependence of the LSPE growth length, and FIG. 3 is a conventional amorphous silicon LSPE. It is a figure which shows formation of the SOI structure by growth. (31) …… Si substrate, (32) …… Insulating film pattern, (33)
…… Amorphous silicon, (34) …… SOI layer.
Claims (1)
と、 前記主表面上に選択的に絶縁膜を形成する工程と、 前記絶縁膜上及び前記主表面上に非晶質シリコン層を形
成する工程と、 前記主表面上に形成された前記非晶質シリコン層の膜厚
を前記絶縁膜上に形成された前記非晶質シリコン層の膜
厚より薄くする工程と、 その工程の後、熱処理により、前記非晶質シリコン層を
単結晶化する工程とを有することを特徴とする半導体装
置の製造方法。1. A step of preparing a semiconductor substrate having a main surface, a step of selectively forming an insulating film on the main surface, and an amorphous silicon layer formed on the insulating film and the main surface. And a step of making the thickness of the amorphous silicon layer formed on the main surface smaller than the thickness of the amorphous silicon layer formed on the insulating film, and after that step, A step of monocrystallizing the amorphous silicon layer by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60181096A JPH0773095B2 (en) | 1985-08-20 | 1985-08-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60181096A JPH0773095B2 (en) | 1985-08-20 | 1985-08-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6242510A JPS6242510A (en) | 1987-02-24 |
| JPH0773095B2 true JPH0773095B2 (en) | 1995-08-02 |
Family
ID=16094760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60181096A Expired - Lifetime JPH0773095B2 (en) | 1985-08-20 | 1985-08-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0773095B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2515323Y2 (en) * | 1990-07-04 | 1996-10-30 | 三菱重工業株式会社 | Crawler vehicle running unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58116721A (en) * | 1981-12-30 | 1983-07-12 | Fujitsu Ltd | Preparation of semiconductor device |
-
1985
- 1985-08-20 JP JP60181096A patent/JPH0773095B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6242510A (en) | 1987-02-24 |
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