JPS6242510A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device whose area of SOI structure is enlarged by a method wherein the thickness of an amorphous Si film on a seed crystal is reduced to shorten the delay time at the early period of heat treatment so that epitaxial growth is performed longer until it is limited with the polycrystalization of the amorphous Si. CONSTITUTION:After a thermal oxide film 32 has been formed on a Si substrate 31, patterning is performed photolithography or etching technique. After that, the substrate 32 is chemically washed with washing liquid with specified ratio of HCl, H2O2, H2O and is cleaned with high-temperature heating in super- vacuum, and amorphous Si 33 is deposited on the surface with electron beam evaporation. Further, heat-treatment is done at a specified temperature to miniaturize the amorphous Si. After that, the amorphous Si 33 on the seed crystal is thinned with photoetching so that the thickness is two times less than that of the thermal oxide film 32.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides an S
OI (Sem1conductor onIn
The present invention relates to a method of manufacturing a semiconductor device having a sulator structure.

(Prior art) Figure 3 shows, for example, [FED SOI/3D WORKSH
OP).

March, 19-21 1985 P69-74
In particular, the figure shows the formation of So fill single crystal silicon by conventional LSPE growth of amorphous silicon shown in P74゜Figs 5 to 8. When the amorphous silicon deposited on top is heat-treated at about 600℃, S
After vertical solid phase epitaxial growth (VSPE growth) (141) using the i-substrate (11) as a seed crystal, LSPE growth (19) is performed on the insulating film (14).

FIG. 2 is a graph showing the dependence of LSPE growth length on heat treatment time. After the delay time required for VSPE growth in the early stage of heat treatment, LSPE growth is achieved until single crystal growth becomes impossible due to polycrystalization of amorphous silicon. In addition, VSPE
Growth lag time (26) is LSPE growth) JVSP
This occurs because E-growth occurs preferentially. In addition, if the heat treatment time exceeds 5.5 hours, polycrystalization occurs (27), so
The problem lies in how to grow LSPE within this time. In other words, the time required for VSPE growth should be saved and that time should be used for LSPE growth.

(Problems to be Solved by the Invention) However, in the above manufacturing method, the LSPE growth length is limited by polycrystallization and is about 5 μm at maximum, and 5 μm
There was a problem that it was not possible to form 501 layers of 501 or more.

This invention has an area of 801
This method solves the problem of not being able to form a layer and enables the formation of more semiconductor elements, in other words, it provides a method for expanding the area of the SOI layer.

(Means for Solving the Problems) In order to solve the above problems, the present invention makes the thickness of the amorphous silicon film thinner than that on the insulating film when forming the Sol structure by LSPE growth of amorphous silicon. It is something that carries out a process.

(Function) According to the present invention, in the method for forming the 801 layer by LSPE growth, the film thickness of the amorphous silicon on the Si substrate, of the amorphous silicon deposited on the Si substrate having a patterned insulating film, By making the VSPE thinner, the time required for VSPE growth can be suppressed, and the transition time to LSPE growth can be accelerated, so that LSPE growth can proceed within a processing time in which polycrystalization does not occur.

(Example) Figure 3 (al to (dl) is the Sol calendar formation process of this invention. First, as shown in Figure 3 (al), 5i (1
00) Approximately 500 thermal oxide films (32) on the substrate (31)
After forming, patterning is performed using photolithography and etching techniques. After that, the above substrate (3
1) was chemically cleaned using a cleaning solution with a ratio of HCI: H20□:H2O of 1:1:6, introduced into an ultra-high vacuum, and subjected to high-temperature heating cleaning at 850°C for 5 minutes or more to form a cleaned surface. , followed by electron beam evaporation to reduce the film thickness to 0.
, 6 μm or more of amorphous silicon (33) is deposited on the surface. Furthermore, heat treatment was performed at 450℃ for about 30 minutes, and f
Amorphous silicon kj shown in bl is densified. After that, as shown in (c), the amorphous silicon (3
3) is thinned by photolithography and thermal oxidation 1
! ! Twice the film thickness of J (32), in the example the film thickness is 1
000 people. Next, a heat treatment is performed at about 600° C. in an N2 atmosphere, and a semiconductor element is formed in the SOr region (34), which is grown by LSPE and made into a single crystal as shown in fd), by a conventional process.

(Effects of the Invention) As described in detail above, according to the present invention, when forming the Sol structure, the thickness of the amorphous silicon film on the seed crystal is reduced, so the delay time at the initial stage of heat treatment is shortened. Longer lengths (L
SPE growth can be performed. In addition, in the present invention, the film thickness of the amorphous silicon is reduced to 1/6 from 6000 to 1000, so it is thought that the position of the solid line moves in parallel, as shown by the chain line in Figure 2, so the thickness of the 801 layer is 5 to 6 μm. The area can be expanded by 44%.

[Brief explanation of the drawing]

Fig. 1 (al to [dl are So1 layer formation process diagrams according to the present invention, Fig. 2 is a characteristic graph showing the LSPESPE growth heat treatment time dependence, Fig. 3 is a conventional amorphous silicon L
FIG. 3 is a diagram showing the formation of a Sol structure by SPE growth. (31) ・SI substrate, (32) ・Insulating film pattern,
(33)...Amorphous silicon, (34)...801
layer. 2) raw graph 2

Claims (1)

[Claims] A method for manufacturing a semiconductor element having an SOI structure, characterized in that when forming an SOI structure by epitaxial growth of amorphous silicon, a step is performed to make the thickness of the amorphous silicon film on the seed crystal thinner than that on the insulating film. A method for manufacturing a semiconductor device.