JPH0773286A - Image processor - Google Patents

Abstract

PURPOSE:To provide an image processor which can select a processing means, simplify the change of processing order, shorten the processing time, and supply a single piece of image data to plural processing means when the image processing operations are carried out in plural times. CONSTITUTION:An image processor consists of a frame memory 23 which stores temporarily the image data supplied from a CCD camera 3 and the image data processed by means of a post-processing card 7, an input selector which selects the image data acquired by the camera 3 synchronously with the image data fetching cycle of the camera 3 and selects the image data processed by the card 7 in a cycle shorter than the image data fetching cycle of the camera 3, and an output selector which takes the image data out of the memory 23 in a cycle shorter than the image data fetching cycle of the camera 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data obtained by picking up an image by an image input apparatus, and more particularly to an image capable of shortening the time when the image processing is performed a plurality of times. Supplying one image data to a plurality of image processing means, and a processing device and an image processing apparatus capable of easily selecting the processing means and changing the order thereof when the image processing is performed by a plurality of processing means separately Image processing apparatus.

[0002]

2. Description of the Related Art As is well known, in recent years, appearance inspections of products and the like have been performed by subjecting data obtained by a CCD camera to image processing by an image processing device instead of human eyes.

As shown in FIG. 8, the conventional image processing apparatus 100 has a memory 105a for temporarily storing image data obtained from the CCD camera 103, and a process such as calculation for the image data supplied from the memory 105a. The image processing unit 107 is configured to perform the image processing, and the memory 105b that temporarily stores the image-processed data.

The image processing apparatus 100 stores the image data obtained from the CCD camera 103 in the temporary memory 105a, and the CCD camera 103 is stored in the image processing unit 107.
The image data is supplied at the same speed as the image data is supplied from.

When image processing is performed a plurality of times using the image processing apparatus 100, for example, when image data is smoothed twice, first, the memory 105a to the image processing unit 107 are processed.
The image processing unit 107 performs the first smoothing, and stores the result in the memory 105b. Then, the image data is supplied from the memory 105b to the image processing unit 107, the image processing unit 107 performs the second smoothing, and the result is stored in the memory 105a.

Further, as shown in FIG. 9, the image processing unit 107
There is also known a pipeline type image processing apparatus 110 in which a plurality of image processing devices are provided in series and a plurality of processes are sequentially performed.

[0007]

However, in the image processing apparatus 100 shown in FIG. 8, when performing image processing a plurality of times, it is necessary to transmit and receive data between the memory 105 and the image processing unit 107 by the number of times. Therefore, there is a problem that the speed of image processing becomes slow.

Further, in the image processing apparatus 110 shown in FIG. 9, a plurality of image processing units 107 are serially provided and the image processing is performed in that order. Therefore, the image processing speed is higher than that of the image processing apparatus 100 in FIG. It becomes faster, but each image processing unit 10
7 has a predetermined processing function (for example, the image processing unit 107a smoothes, the image processing unit 107b removes isolated points,
If the order is changed, or if only the processing of the image processing units 107a and 107c is performed, the configuration of the image processing apparatus 110 has to be changed each time, which is troublesome. is there. Therefore, there is also a method in which each image processing unit 107 independently has hardware and rearranges the hardware, but there is a problem that not only the control of software becomes complicated but also the scale of hardware becomes large.

Further, the image processing apparatus 1 shown in FIGS.
00, 110 multiple visual inspections at once, for example,
When inspecting the outer diameter and the chip of the rubber ring, the two CCD cameras 103 for the outer diameter inspection and the chip inspection, and the two image processing devices 100 (or 110) for image-processing the image data obtained by them are used. It is necessary and there is a problem that the scale of the apparatus used for the visual inspection increases.

The present invention has been made in view of the above circumstances, and an object thereof is to easily select an image processing unit to be operated and change its order when image processing is performed a plurality of times by a plurality of image processing units. It is an object of the present invention to provide an image processing apparatus capable of reducing the time required for image processing, and further capable of supplying one image data to a plurality of image processing means at the same time.

[0011]

In order to achieve the above object, the present invention provides image data supplied from an image pickup means,
When the image data obtained by the image pickup means is stored when the image data obtained by the image pickup means is stored in the storage means, the storage means temporarily holds the image data subjected to the image processing by the image processing means, and the image data acquisition cycle of the image pickup means. When the image data is image data after being image-processed by the image processing means in synchronism with each other, when the image data is input from the image data input means and the storage means, the image data input means performs the image data in a cycle shorter than the image data acquisition cycle of the imaging means The image data output means performs the operation in a cycle shorter than the image data acquisition cycle of the imaging means.

Further, the image data input means has a plurality of selectable cycles for holding the image data in the storage means, and the image data output means has a plurality of selectable cycles for extracting the image data from the storage means. It is characterized by having.

Further, an image inputting means having a storage means for temporarily holding the image data obtained by the image pickup means,
Smoothing the image data supplied from this image input means,
In an image processing apparatus provided with an image processing means composed of a plurality of processing means for independently performing processing such as isolated point removal, thinning, and binarization, an operation of individually switching whether or not to operate each of the processing means Setting means, feedback switching means for switching whether or not the data image-processed by the processing means is fed back to the image input means, and the image data fed back to the image input means by the feedback switching means is left behind or again. It is characterized by comprising a selecting means for selecting whether to supply to the processing means.

Further, a plurality of image input means having a storage means for temporarily holding the image data obtained by the image pickup means, and a plurality of image processing means for performing image processing on the image data obtained by the image input means by a plurality of or one processing means. In the image processing device, the image data obtained by the image input means can be directly output to the corresponding image processing means, and the image data processed by the image processing means. And a direct connection image bus connected to each corresponding image input means so as to be directly outputable, and image data obtained by each image input means can be simultaneously output to each image processing means, and each image processing means A common image bus for connecting the image data image-processed by the image output means to a plurality of image input means at the same time; An output bus selection unit provided in each image input unit for selecting which of the direct connection image bus and the common image bus is used when image data is output from the image input unit to the image processing unit; A feedback output bus selection unit provided in the processing unit and selecting which of the direct image bus and the common image bus to use when outputting image data from the image processing unit to the image input unit. It has a feature.

[0015]

According to the above construction, when the image data input means holds the image data in the storage means for temporarily holding the image data, when the image data is obtained by the image pickup means, the image data fetching cycle of the image pickup means Done in sync with
When the image data is image-processed by the image processing means, the image data is taken in a cycle shorter than the image data acquisition cycle of the image pickup means. Then, the image data output means, when taking out the image data from the storage means, carries out a cycle shorter than the image data fetching cycle of the imaging means.

Further, the image data input means has a plurality of selectable cycles for holding the image data in the storage means, and the image data output means can select a plurality of cycles for taking out the image data from the storage means. To have.

Further, image input means having a storage means for temporarily holding the image data obtained by the image pickup means,
Smoothing the image data supplied from this image input means,
In an image processing apparatus having an image processing means including a plurality of processing means for independently performing processing such as isolated point removal, thinning, and binarization, whether or not each of the processing means is operated by the operation setting means Are individually switched, and whether or not the data subjected to the image processing by the processing means is fed back to the image input means is switched by the feedback switching means. Then, the selecting means selects whether the image data returned to the image input means by the feedback switching means is left as it is or is supplied again to the post-processing means.

Furthermore, a plurality of image input means having a storage means for temporarily holding the image data obtained by the image pickup means, and a plurality of image processing means for performing image processing on the image data obtained by the image input means by a plurality of or one processing means. In the image processing apparatus including the image processing means of, the direct connection image bus individually connects each image input means and the corresponding image processing means, and the common image bus connects each image input means and each image processing means. Connect with one bus. And
The output bus selection unit selects which of the direct connection image bus and the common image bus is used when outputting image data from the image input unit to the image processing unit, and the feedback output bus selection unit selects the image processing unit from the image processing unit. When outputting image data to the image input means, it is selected which of the direct connection image bus and the common image bus is used.

[0019]

1 is a block diagram showing an embodiment of an image processing apparatus of the present invention.

As shown in FIG. 1, the image processing apparatus 1 of this embodiment includes a plurality of image input cards 5 (image input means) for temporarily storing image data obtained by the CCD camera 3 (image pickup means), and an image. A plurality of post-processing cards 7 (image processing means) for image-processing the image data temporarily stored in the input card 5, an image input card 5, and a control computer 9 (not shown) for controlling the post-processing card 7. , An image input card bus 11 (directly connected image bus) for individually connecting each image input card 5 and each corresponding post-processing card 7
And a common image bus 13 that connects each image input card 5 and each post-processing card 7 by one bus.

The image input card 5 includes an A / D converter 15
A brightness correction unit 17, a projection calculation unit 19, a brightness histogram calculation unit 21, and a frame memory 23 (storage means).
A frame memory switching section 25 (selection means), a luminance conversion section 39, an output bus selection section 41 (output bus selection means), a feedback input selection section 43, a video RAM 45,
It consists of

The A / D converter 15 A / D converts the image data obtained by the CCD camera 3.

The brightness correction unit 17 corrects the brightness unevenness of the image data A / D converted by the A / D conversion unit 15.

The projection calculation unit 19 obtains the brightness addition value in each of the x and y directions as projection data based on the image data whose brightness has been corrected by the brightness correction unit 17.

The brightness histogram calculation section 21 obtains a brightness histogram based on the image data brightness-corrected by the brightness correction section 17.

The frame memory 23 temporarily holds the image data whose brightness has been corrected and the image data which has been image-processed by the post-processing card 7.

As shown in FIG. 2, the frame memory switching section 25 controls holding or taking out of image data to and from the frame memory 23, and when holding the image data in the frame memory 23, or
When the image data is fetched from the frame memory 23, the control register 27 for controlling which of the frame memories 23a and 23b is to be operated is synchronized with the image data output cycle of the CCD camera 3, and the total time is 1/30 (sec). An input address counter 29 that counts up the address so that it can be held for each pixel, or that counts up the address so that it can be held for all pixels at 1/2 of the image data output cycle of the CCD camera 3, that is, 1/60 (sec). (Image data input means) and an output address counter 31 (image data output means) that counts up the address so that all pixels can be taken out in 1/2 of the image data output cycle of the CCD camera 3, that is, 1/60 (sec). )
Is provided for each of the frame memories 23a and 23b, and which one of the input address counter 29 and the output address counter 31 is used is selected according to the instruction of the control register 27, and when the input address counter 29 is selected, An address counter selector 33 for selecting a cycle (counting up the addresses of all pixels at 1/30 or 1/60 (sec)) and each frame memory 23a,
Image data supplied from the brightness correction unit 17 according to an instruction of the control register 27, which is provided for each 23b, or
After selecting whether the image data is returned from the post-processing card 7, the input selector 35 (image data) which holds the image data in the frame memory 23 according to the counted up address of the input address counter 29 selected by the address counter selector 33. (Input means) and an output selector 37 (image data output means) for picking up image data according to the address counted up by the output address counter 31 after selecting the frame memory 23 for taking out data according to the instruction of the control register 27, and an input selector. 35, an address counter selector 33 and an output selector 37, and a control register bus 27B for outputting an instruction from the control register 27.

When supplying the image data stored in the frame memory 23 to the post-processing card 7, the brightness conversion section 39 performs brightness conversion based on a look-up table to perform binarization and brightness enhancement. .

The output bus selector 41 supplies the image input card bus 11 and the common image bus 1 when the image data whose brightness is converted by the brightness converter 39 is supplied to the post-processing card 7.
Which of the three is used is selected.

The return input selector 43 selects whether the image data to be returned from the post-processing card 7 to the image input card 5 is to be fetched from the image input card bus 11 or the common image bus 13.

The video RAM 45 stores the image data image-processed by the post-processing card 7 for screen display.

The post-processing card 7 has a take-in bus selection section 51.
A spatial filter section 53 (processing section), a division table section 55 (processing section), an inter-pixel calculation section 57 (processing section), a comparison calculation section 59 (processing section), and a logical filter section 61 (processing section). ), A post-processing module unit 63 (processing unit), an operation setting unit 65 (not shown, operation setting unit), an inter-pixel calculation feedback unit 67 (feedback switching unit),
The logic filter feedback unit 69 (feedback switching unit), the feedback bus selection unit 71 (feedback output bus selection unit), and the local CPU 73 (operation setting unit) are included.

The capture bus selection unit 51 selects whether to capture data supplied from the image input card bus 11 or the common image bus 13.

The spatial filter section 53 emphasizes vertical lines and horizontal lines in the image data supplied from the image input card 5.

The division table section 55 normalizes the bits of the image data increased by the vertical line emphasis and the horizontal line emphasis by the spatial filter section 53 and restores them to the original number of bits.

The inter-pixel calculation unit 57 includes a spatial filter unit 5
The image data in which the vertical lines are emphasized and the horizontal lines are emphasized by 3 are subjected to arithmetic operations such as four arithmetic operations and non-linear conversion.

The comparison operation section 59 compares the image pattern stored in advance with the image data obtained by the inter-pixel operation section 57 by performing operations such as four arithmetic operations.

The logical filter section 61 includes a comparison operation section 59.
Feature extraction such as removal of isolated points and thinning of the image data obtained by is performed.

The post-processing module unit 63 performs an integration process of the brightness of each pixel in an arbitrary closed region of the image data obtained by the logical filter unit 61, a labeling process for the image data obtained by the logical filter unit 61, and the like. Do it individually.

The operation setting section 65 includes the spatial filter section 53.
A division table unit 55, an inter-pixel operation unit 57, a comparison operation unit 59, a logic filter unit 61, and a post-processing module unit 63.
Control computer 9 (local CPU 73
Via the)), whether or not to operate each of the above components is set. It should be noted that when the setting is made such that the image data is not operated, the above-mentioned component section outputs the input image data as it is.

The inter-pixel calculation feedback section 67 is composed of the inter-pixel calculation section 5
It is switched whether or not the image data obtained by 7 is returned to the image input card 5.

The logic filter feedback section 69 switches whether or not the image data obtained by the logic filter section 61 is returned to the image input card 5.

The return bus selection unit 71 uses the image data obtained by the logic filter unit 61 and the like as the image input card 5.
When the image is returned to, the image input card bus 11 or the common image bus 13 is selected. Further, when supplying the image data after the image processing to the other post-processing card 7, the common image bus 13 is selected.

The local CPU 73 controls each component of the image input card 5 and each component of the post-processing card 7 according to an instruction from the control computer 9. Further, the control computer 9 takes in data obtained by each component in accordance with a command and outputs it to the control computer 9. A local CPU provided on the post-processing card 7
73 and each component of the image input card 5 are local CPs.
It is connected by the U bus 75.

The control computer 9 includes a display unit, an input unit, a calculation unit, and a memory (none of which is shown) for storing image data obtained by the image input card 5 and the post-processing card 7. The image input card 5 and the post-processing card 7 are connected by a control computer bus (not shown).

Next, the operation of this embodiment will be described.

<Double-speed Input / Output of Image Data, Feedback Pipeline Processing> First, the image processing operation using one image input card 5a and one post-processing card 7a is performed by the operation of the image input card 5a of FIG. The flow chart shown will be mainly described.

First, the spatial filter section 53 of the post-processing card 7a, the division table section 55, the inter-pixel calculation section 57,
The comparison operation unit 59 and the logic filter unit 61 are selected to operate or not to operate (step S).
T1). Here, it is assumed that all of them are operated, and each operation setting unit 65 sets the operation according to an instruction from the control computer 9 (via the local CPU 73).

Then, the object to be inspected is imaged by the CCD camera 3a to obtain image data for each pixel. When the image data is obtained, the A / D conversion unit 15 A / D-converts the obtained image data and supplies it to the brightness correction unit 17. The brightness correction unit 17 supplies the image data with the brightness unevenness corrected to the frame memory switching unit 25 (step ST3).

At this time, the projection calculation unit 19 and the brightness histogram calculation unit 21 use the brightness-corrected image data as a basis.
The brightness addition value in each of the x direction and the y direction is obtained as projection data, and a brightness histogram is calculated. The calculated projection data and brightness histogram are the local CP
It is supplied to the local CPU 73 via the U bus 75.
The projection data and the brightness histogram supplied to the local CPU 73 can be displayed on the display unit of the control computer 9 by an instruction from the control computer 9.

On the other hand, in the frame memory switching section 25,
The frame memory 23 that temporarily holds the image data is selected. Since nothing is stored in the frame memory 23 yet, it is temporarily held in the frame memory 23a in synchronization with the image data acquisition period of the CCD camera 3a (step ST5).

When the image data of all pixels are stored in the frame memory 23a, the frame memory switching section 25
The image data is taken out at a cycle of 1/2 of the image data taking-in cycle of the CCD camera 3a and supplied to the brightness conversion section 39 (step ST7).

The brightness conversion unit 39 performs brightness conversion on the supplied image data based on the look-up table, performs binarization processing and brightness enhancement, and supplies the image data to the output bus selection unit 41.

The output bus selection unit 41 selects a bus for supplying image data to the post-processing card 7a according to an instruction from the control computer 9 (via the local CPU 73). Here, either the image input card bus 11 or the common image bus 13 may be used, but the image input card bus 11 is used. Then, the image data subjected to the binarization processing and the brightness enhancement is output to the image input card 5a (step ST9).

On the other hand, in the post-processing card 7a, in accordance with an instruction from the control computer 9, the acquisition bus selection unit 51 selects whether the image input card bus 11 or the common image bus 13 is to receive data. Here, since the data is supplied from the image input card bus 11, the image input card bus 11 is selected. Then, when the image data is output to the image input card bus 11, the image data is simultaneously supplied to the two spatial filter units 53.

In the spatial filter unit 53, when the image data is supplied, the spatial filter unit 53a performs vertical line enhancement and the spatial filter unit 53b performs horizontal line enhancement. The vertical line-emphasized image and the horizontal line-emphasized image data are normalized by the division table unit 55, and the inter-pixel calculation unit 5
The image data is supplied to 7.

In the inter-pixel calculation section 57, the image data in which the vertical line emphasis and the horizontal line emphasis are carried out by the spatial filter section 53 mutually perform arithmetic operations such as four arithmetic operations and nonlinear conversion, and the inter-pixel operation feedback section 67 receives the image data. Supply.

Here, it is assumed that no instruction for returning the image data obtained by the inter-pixel calculation unit 57 to the image input card 5a is issued, and the inter-pixel calculation feedback unit 67 is supplied from the inter-pixel calculation unit 57. Image data comparison operation unit 5
Supply only to 9.

In the comparison calculation unit 59, the inter-pixel calculation feedback unit 6
The image data supplied from 7 and the image pattern stored in advance are compared by performing operations such as four arithmetic operations, and then the image data is supplied to the logical filter unit 61.

In the logical filter unit 61, the comparison operation unit 5
The image data supplied from 9 is subjected to feature extraction such as isolated point removal and thinning, and the image data is supplied to the post-processing module unit 63.

After that, the post-processing module unit 63 individually performs the integration process of the brightness of each pixel in the arbitrary closed region of the image data supplied from the logic filter unit 61, the labeling process, and the like. After completion of these processes, the result is temporarily held in the local CPU 73 and is supplied to the control computer 9 according to the instruction from the control computer 9.

Next, a specific operation of the frame memory switching section 25 will be described with reference to FIGS. 4 and 5 showing the image data holding operation and the flowchart of FIG. 6 showing the image data fetching operation.

First, when the image data is supplied from the brightness correction unit 17, the control register 27 sends the image data from the brightness correction unit 17 to the control register bus 27B in accordance with an instruction output from the control computer 9 via the local CPU 73. Is output to the frame memory 23a (FIG. 4, step ST11).

When a command for holding the image data in the frame memory 23a is output from the brightness correction unit 17 (steps ST13YES, ST15YSS), the input selector 3
5a enables the image data supplied from the brightness correction unit 17 to be held in the frame memory 23a (step ST17). At this time, the input selector 35b is in the open state.

Then, the address counter selector 33a
Is 1/3 of all pixels to the input address counter 29.
The count up of the address is started at the cycle held at 0 (sec) (step ST19).

Then, the input selector 35a holds the image data in the frame memory 23a in accordance with the address counted up by the input address counter 29 (step ST21).

When an instruction to hold the image data from the brightness correction section 17 in the frame memory 23b is output (steps ST13YES and ST15NO), the input selector 35b causes the image data supplied from the brightness correction section 17 to be output. Can be held in the frame memory 23b (step ST23). At this time, the input selector 35a is in the open state.

After that, the address counter selector 35a
Is 1/3 of all pixels to the input address counter 29.
The count up of the address is started in the cycle held at 0 (sec) (step ST25).

Then, the input selector 35a holds the image data in the frame memory 23a in accordance with the address counted up by the input address counter 29 (step ST27).

Further, when the image data is image-processed by the post-processing card 7a and returned, the control register 27
In accordance with an instruction output from the control computer 9 via the local CPU 73, the image data from the post-processing card 7a is transferred to the frame memory 23 on the control register bus 27B.
An instruction to hold the data in b is output (step ST1).
1).

When an instruction to retain the image data from the post-processing card 7a in the frame memory 23b is output (step ST13 NO, YES in step ST29 in FIG. 5), the input selector 35b causes the image data supplied from the brightness correction unit 17 to be output. It can be held in the frame memory 23b (step ST31). At this time, the input selector 35a is in the open state.

After that, the address counter selector 33b
Is 1/6 of all pixels to the input address counter 29.
The count up of the address is started in the cycle held at 0 (sec) (step ST33).

Then, the input selector 35b holds the image data in the frame memory 23b in accordance with the address counted up by the input address counter 29 (step ST35).

When an instruction to hold the image data from the post-processing card 7a in the frame memory 23a is output (NO in step ST29), the input selector 35a is
The image data supplied from the brightness correction unit 17 can be held in the frame memory 23a (step ST3).
7). At this time, the input selector 35b is in the open state.

Then, the address counter selector 33a
Is 1/6 of all pixels to the input address counter 29.
The count up of the address is started at the cycle held at 0 (sec) (step ST39).

Then, the input selector 35a holds the image data in the frame memory 23a in accordance with the address counted up by the input address counter 29 (step ST41).

When the output address counter 31 has finished counting up, the control register 27 causes the frame memory 2
An instruction to take out the image data held in 3a is output to the control register bus 27B (FIG. 6, step ST
51) The frame memory 23a on the control register bus 27B
When an instruction to extract the image data is output from the image selector (YES in step ST53), the output selector 37 converts the image data extracted from the frame memory 23a into the brightness conversion unit 39.
To be supplied (step ST55).

Then, the address counter selector 33a
Outputs 1/6 of all pixels to the output address counter 31.
Address count-up is started at a cycle of taking out at 0 (sec) (step ST57).

Then, the output selector 37 fetches the image data from the frame memory 23a according to the address counted up by the output address counter 31 (step ST59).

When an instruction to take out image data from the frame memory 23b is output to the control register bus 27B (step ST53NO), the output selector 37 becomes
The image data extracted from the frame memory 23b can be supplied to the brightness conversion unit 39 (step ST6).
1).

Then, the address counter selector 33b
Outputs 1/6 of all pixels to the output address counter 31.
The count up of the address is started at the cycle of taking out at 0 (sec) (step ST63).

Then, the output selector 37 fetches the image data from the frame memory 23b according to the address counted up by the output address counter 31 (step ST69).

As described above, when the image data supplied from the brightness correction unit 17 is held in the frame memory 23,
The image of the CCD camera 3a is held in synchronization with the image data fetching cycle of the CCD camera 3a, when the image data is fetched from the frame memory 23, and when the image data returned from the post-processing card 7a is held in the frame memory 23. Since the processing is performed at a half cycle of the data acquisition cycle, the time required for image processing can be shortened.

The control register 27 outputs an instruction to the control register bus 27B in accordance with an instruction output from the control computer 9 via the local CPU 73. However, the image processing step is to output the image data from the CCD camera 3a. When it is determined that the image data is supplied to the post-processing card 7a, image-processed by the post-processing card 7a, returned to the image input card 5a, and then supplied to the post-processing card 7a again, the control register 27 to the control register bus 27B in advance.
It is also possible to set the order of the instructions to be output to and the timing.

When the image data is taken out from the frame memory 23 and when the image data returned from the post-processing card 7a is held, the image data is taken out at a half cycle of the image data taking cycle of the CCD camera 3a. Alternatively, it is held, but not limited to this, but the CCD camera 3a
It may be set to ⅓, ¼, etc. of the image data acquisition period.

Further, a plurality of clocks for counting up the address may be set in advance in the input address counter 29 and the output address counter 31, and the image data may be held and retrieved by selecting from among them.

Next, the case where the image data obtained by the post-processing card 7a is returned to the image input card 5a will be described with reference to the flowchart of FIG.

First, it is selected which of the inter-pixel operation feedback section 67, the logic filter feedback section 69, or both of them returns the image data (step ST7).
1). Here, the image data is fed back by the inter-pixel calculation feedback unit 67.

At this time, in the inter-pixel operation feedback section 67, it is possible to supply the image data obtained by the inter-pixel operation section 57 to the feedback bus selection section 71 and at the same time to supply the image data to the comparison operation section 59 in the subsequent stage. (Step 7
3YES, ST77), in this case, the return of the image data to the image input card 5a and the subsequent image processing from the comparison calculation unit 59 are performed in parallel.

Here, the image data obtained by the inter-pixel calculation unit 57 is only supplied to the feedback bus selection unit 71 (NO in step ST73).

Then, the control computer 9 outputs to the inter-pixel operation feedback section 67 via the local CPU 73 a command for returning the image data obtained by the inter-pixel operation section 57 to the image input card 5a. The inter-pixel operation feedback unit 67 supplies the image data obtained by the inter-pixel operation unit 57 to the feedback bus selection unit 71 according to the instruction (step ST75).

When the image data is supplied to the return bus selection unit 71, the return bus selection unit 71 selects a bus for returning to the image input card 5a according to an instruction from the control computer 9 (step ST79). Here, either the image input card bus 11 or the common image bus 13 may be used, but the image input card bus 11 is selected. Then, the image data obtained by the inter-pixel calculation unit 57 is output to the image input card bus 11.

On the other hand, in the feedback input selection section 43 of the image input card 5a, the image input card bus 11 and the common image bus 1
It is selected which of the three (3) to fetch the image data (step ST81). Here, since the image data obtained by the inter-pixel calculation unit 57 is output to the image input card bus 11, the image input card bus 11 is selected. Then, the returned image data is temporarily held in the video RAM 45 and is supplied to the frame memory switching unit 25 (step ST83).

At this time, the image data temporarily stored in the video RAM 45 is supplied to the control computer 9 via the local CPU 73 by an instruction from the control computer 9 and can be displayed on the display section of the control computer 9. Therefore, the operator can know the progress of the image processing.

The image data obtained by the logic filter unit 61 can be returned to the image input card 5a by operating in the same manner as described above.

Next, a case where the image data fed back from the post-processing card 7a is supplied again to the post-processing card 7a for image processing will be described with reference to the timing of FIG.

First, the image data obtained by the CCD camera 3a and subjected to the brightness correction by the brightness correction unit 17 is held in the frame memory 23a in synchronization with the image data fetch cycle of the CCD camera 3a (input 1-1). On the other hand, the frame memory 23b is in the input waiting state during this period.

After the input is completed for all pixels, 1/2 of the image data acquisition period of the CCD camera 3a
The image data is taken out from the frame memory 23a and supplied to the post-processing card 7a in the time period of (output 1-1).

Then, the image data after the image processing by the post-processing card 7a is held in the frame memory 23b at a time period half the image data fetch period of the CCD camera 3a (input 1-2).

In the frame memory 23a, after the output 1-1 is completed, the next image data whose brightness is corrected by the brightness correction unit 17 is held in synchronization with the image data acquisition period of the CCD camera 3a (input 2-1). ).

In the frame memory 23b, after the input 1-2 is completed, the image data is taken out at a time period of 1/2 of the image data taking-in period of the CCD camera 3a and supplied to the post-processing card 7a (output 1-2 ).

Then, in the frame memory 23a, after the input 2-1 from the brightness correction unit 17 is completed, the image data is taken out from the frame memory 23a at a time cycle of 1/2 of the image data acquisition cycle of the CCD camera 3a. It is supplied to the post-processing card 7a (output 2-1).

After the image processing is completed by the post-processing card 7a, the image data is held in the frame memory 23b at a half cycle of the image data fetch cycle of the CCD camera 3a (input 2- 2). The frame memory 23b is in an input waiting state from the end of the output 2-1 to the start of the input 2-2.
After that, it operates at the same timing.

In this manner, whether or not each processing means (spatial filter units 53a and 53b, division table unit 55, inter-pixel operation unit 57, comparison operation unit 59, logical filter unit 61) is operated by each operation setting unit 65. With the above setting, the inter-pixel calculation feedback section 67 and the logic filter feedback section 69 allow the inter-pixel calculation section 57 and the logic filter section 6 to operate.
By setting the image data obtained in 1 to be returned to the image input card 5a, it becomes possible to easily select the processing means to be operated and change the order thereof.

In this embodiment, the spatial filter units 53a and 53b, the division table unit 55, the inter-pixel arithmetic unit 57, the comparison arithmetic unit 59, and the logical filter unit 6 are used as processing means.
However, the present invention is not limited to this, and other processing means may be provided.

Further, in the present embodiment, the inter-pixel operation feedback section 5
The image data is fed back to the image input card 5a by the 9 and the logical filter feedback unit 69, but not limited to this, the spatial filter unit 53, the division table unit 55, the comparison operation unit 5
The image input card 5a is provided with feedback switching means in the subsequent stage
You may make it return to.

Further, in the present embodiment, the image processing is performed by two lines in parallel such as vertical line enhancement by the spatial filter unit 53a and horizontal line enhancement by the spatial filter unit 53b, but the present invention is not limited to this. You may perform using an image processing line.

<Parallel Image Bus> Next, a plurality of post-processing cards 7a, 7b, 7c are connected to one image input card 5a, and one image data obtained by the image input card 5a is processed by the post-processing card 7a, The operation when image processing is performed by 7b and 7c will be described.

In the image input card 5a, as described above,
The image data obtained by the CCD camera 3a passes through the brightness correction unit 17 and the frame memory 23 and the brightness conversion unit 39.
Is supplied to and the brightness is converted.

On the other hand, the output bus selection section 41 selects a bus for supplying the luminance-converted image data to the post-processing cards 7a, 7b, 7c. In this case, the image data obtained by the image input card 5a is converted into three post-processing cards 7a, 7
The output bus selection unit 41 selects the common image bus 13 for image processing in parallel by b and 7c. And
The brightness-converted image data is output to the common image bus 13.

In each of the taking-in bus selecting sections 51 of the post-processing cards 7a, 7b, 7c, the common image bus 13 is selected. Image processing is performed in parallel on each of the post-processing cards 7a, 7b, 7c.

As described above, each image input card 5a, 7
b, 7c and the corresponding post-processing cards 7a, 7b,
Image input card bus 11 for individually connecting 7c,
Each image input card 5a, 5b, 5c and each post-processing card 7
Common image bus 1 that connects a, 7b, and 7c with one bus
Since the same image data can be simultaneously supplied from the image input card 5a to the plurality of post-processing cards 7a, 7b, 7c by means of 3, the post-processing cards 7a, 7b, 7c can perform the image processing on the same image data in parallel. It becomes possible to do it.

Further, each image input card 5a, 5b, 5c
By using each image input card bus 11, each image input card 5a, 5b, 5c and each corresponding post-processing card 7a, 7b, 7c can perform image processing independently.

At this time, each component of the post-processing cards 7b and 7c, which is subsequent to the take-in bus selecting section 51, is connected to the post-processing card 7
a (spatial filter unit 53, division table unit 5
5, the inter-pixel operation unit 57, the inter-pixel operation feedback unit 67, the comparison operation unit 59, the logic filter unit 61, the logic filter feedback unit 69, and the post-processing module unit 63) are the same if the order and configuration are changed. It is possible to perform different image processing on the image data in parallel.

Further, by providing a plurality of image input cards 5, the image data obtained by the CCD camera 3a can be supplied to the post-processing cards 7b and 7c, or the image data obtained by the CCD camera 3b can be supplied to the post-processing card. 7a,
7c can be supplied and various image processing steps can be combined.

In this embodiment, the common image bus 13 is used.
Is composed of two buses, a bus for outputting from the image input card 5a to the post-processing card 7a and a bus for returning from the post-processing card 7a to the image input card 5a, but the number of buses is limited to two. Instead, it is also possible to add or share the two buses by one bus.

[0117]

As described above, according to the present invention, when the image data supplied from the image pickup means is held in the storage means, the image data is held in synchronism with the image data fetching cycle of the image pickup means, and stored in the storage means. When taking out the image data and holding the image data after the image processing by the image means in the storing means, the period is shorter than the image data taking-in cycle of the image pickup means, so that the time required for the image processing is shortened. be able to.

Further, since the image data input / output means has a plurality of selectable periods for holding the image data and the image output means has a plurality of selectable periods for picking up the image data, the held image data It is possible to select a period for holding or taking out image data that matches the image data to be taken out, and it is possible to shorten the time required for image processing.

Further, the operation setting means sets whether or not each processing means is operated, and the feedback switching means can set the image data obtained by the processing means to be fed back to the image input means. It becomes possible to easily select the processing means to be performed and change the order thereof.

Furthermore, a direct connection image bus for individually connecting each image input unit and the corresponding image processing unit and a common image bus for connecting each image input unit and each image processing unit by one bus Since the same image data can be output from one image input unit to multiple image processing units at the same time, and further, the same image data can be output to one image processing unit from multiple image input units at the same time, it is possible to combine various processing steps. In addition, the time required for image processing can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing a configuration of a frame memory switching unit.

FIG. 3 is a flowchart showing an operation of the image input card.

FIG. 4 is a flowchart showing an operation when image data obtained by the post-processing card is returned to the image input card.

FIG. 5 is a timing chart showing an operation timing when the image data returned from the post-processing card is supplied again to the post-processing card to perform image processing.

FIG. 6 is a flowchart showing an image data holding operation of a frame memory switching unit.

FIG. 7 is a flowchart showing an image data holding operation of a frame memory switching unit.

FIG. 8 is a flowchart showing an image data fetching operation of a frame memory switching unit.

FIG. 9 is a configuration diagram showing a conventional image processing apparatus.

FIG. 10 is a configuration diagram showing another example of a conventional image processing apparatus.

[Explanation of symbols]

 1 image processing device 3 CCD camera (imaging means) 5 image input card (image input means) 7 post-processing card (image processing means) 11 image input card bus (direct connection image bus) 13 common image bus 15 A / D converter 17 Brightness correction section 19 Projection calculation section 21 Brightness histogram calculation section 23 Frame memory (storage means) 25 Frame memory switching section (selection means) 29 Input address counter (image data input means) 31 Output address counter (image data output means) 33 address Counter selector 35 Input selector (image data input means) 37 Output selector (image data output means) 39 Luminance conversion section 41 Output bus selection section (output bus selection means) 43 Feedback input selection section 45 Video RAM 51 Acquisition bus selection section 53 Space Filter unit (processing means) 55 Table unit (processing unit) 57 Inter-pixel calculation unit (processing unit) 59 Comparison calculation unit (processing unit) 61 Logical filter unit (processing unit) 63 Post-processing module unit (processing unit) 65 Operation setting unit (operation setting unit) 67 Inter-pixel operation feedback unit (feedback switching unit) 69 Logic filter feedback unit (feedback switching unit) 71 Feedback bus selection unit (feedback output bus selection unit) 73 Local CPU 75 Local CPU bus

Claims (4)

[Claims] 1. An image processing apparatus for image-processing image data obtained by an image-capturing means by image-processing means, wherein the image data supplied from the image-capturing means and the image data image-processed by the image-processing means are temporarily stored. When storing the image data in the storage unit and the image data obtained by the image capturing unit, the image processing is performed in synchronization with the image data capturing period of the image capturing unit, and the image processing is performed by the image processing unit. In the case of the subsequent image data, the image data inputting means performs the image data in a cycle shorter than the image data capturing cycle of the image capturing means, and when the image data is retrieved from the storage means, the image data capturing means in the image data capturing cycle of the image capturing means An image processing apparatus comprising: an image data output unit. 2. The image data input means has a plurality of selectable cycles for holding image data in the storage means, and the image data output means has a plurality of selectable cycles for extracting image data from the storage means. The image processing apparatus according to claim 1, which has. 3. An image input unit having a storage unit for temporarily holding image data obtained by the image pickup unit, and image data supplied from the image input unit is smoothed, isolated point removed, thinned, and binarized. In an image processing apparatus including an image processing unit including a plurality of processing units that independently perform processing such as the above, an operation setting unit that individually switches whether to operate each of the processing units, and an image processing by the processing unit. Feedback switching means for switching whether or not to feed back the received data to the image input means, and a selection for selecting whether to leave the image data fed back to the image input means by the feedback switching means or to supply it again to the post-processing means. An image processing apparatus comprising: 4. A plurality of image input means having a storage means for temporarily holding image data obtained by the image pickup means,
An image processing apparatus comprising a plurality of or a plurality of image processing means for performing image processing on the image data obtained by the image input means, wherein the image data obtained by each of the image input means corresponds to A direct connection image bus that can be directly output to the image processing means, and that is connected to each of the corresponding image input means so that the image data processed by the image processing means can be directly output. A common image bus capable of outputting the obtained image data to each of the image processing means at the same time and outputting the image data subjected to the image processing by the image processing means to a plurality of image input means at the same time; The direct connection image bus, which is provided in the image input means and outputs image data from the image input means to the image processing means, An output bus selection unit for selecting which bus of the communication image bus is used, and a direct connection image bus that is provided in each of the image processing units and outputs image data from the image processing unit to the image input unit. An image processing apparatus comprising: a feedback output bus selection unit that selects which of the buses to use.