JPH0774349A - MOS-FET with LLD structure - Google Patents

Abstract

(57) [Summary] [Object] To provide a MOS-FET that suppresses performance deterioration due to hot carriers and is unlikely to cause a short channel effect. [Configuration] The position where the impurity concentration in the depth direction is maximum is n
^The n ⁺ region (high impurity concentration region) 5 is formed deeper than the region (low impurity concentration region) 4 by 0.05 μm or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a MOS-FET,
Especially LDD (Lightly Doped Drain)
The present invention relates to a MOS-FET having a structure.

[0002]

2. Description of the Related Art Conventionally, a MOS-FE having an LDD structure
In T, the formation of the source / drain regions is performed in the low impurity concentration region (hereinafter, n ⁻ region) and the high impurity region (n ⁺ region).
Both were formed by implanting impurities to the same depth. For example, phosphorus was used as an impurity in the n ⁻ region under the conditions of an implantation energy of 30 KeV and a dose amount of 1 × 10 ¹³ cm ⁻² , and arsenic as an impurity in the n ⁺ region was 50 KeV at a dose of 5 × 10 ¹⁵ cm ⁻² . . In this case, the position where the impurity concentration is maximum is 0.037 μ in the case of phosphorus in the depth direction from the Si substrate surface.
m is about 0.032 μm in the case of arsenic, which does not change even after the heat treatment in the subsequent process.

[0003]

However, as shown in FIG. 4, in the conventional source / drain region, both the n ⁻ region 4 and the n ⁺ region 5 have been implanted with impurities to the same depth. In the transistor ON state, carriers move on the surface of the Si substrate (that is, in the vicinity of the gate oxide film 2 and the gate sidewall oxide film 3) and hot carriers easily enter the gate oxide film 2 and the gate sidewall oxide film 3. . In addition, 1 is a gate electrode.

[0004] n as the measure ^- to increase the implantation energy region n ^- a position in which the impurity is of greatest area S
A method of forming the i-substrate from the surface is also proposed.
For example, a method is employed in which the impurity implantation energy of the n ⁻ region is increased to about 70 KeV and the maximum concentration position is deepened to 0.09 μm. In this case, the hot carrier generation position moves to a deeper position of the Si substrate, so that the carriers are less likely to enter the gate oxide film and the gate sidewall oxide film, and the hot carrier breakdown voltage is improved. However, when the implantation energy of impurities is increased, the penetration into the n ⁻ region inside the channel becomes large, and the leakage current at the time of OFF increases, and the performance deterioration due to the short channel effect has been a problem.

The present invention is intended to solve the above problems, and an object thereof is a MOS-FET which suppresses performance deterioration due to hot carriers and is unlikely to cause a short channel effect.
Is to provide.

[0006]

In order to achieve the above object, it was devised to form an n ⁺ region in a deeper region of a semiconductor substrate than an n ⁻ concentration region. That is, according to the present invention, an L having a source / drain diffusion region including an n ⁻ concentration region and an n ⁺ region formed by implanting impurities into a semiconductor substrate is used.
In the DD-structure MOS-FET, a low concentration in which the position where the impurity concentration in the depth direction of the source / drain diffusion region is maximum is 0.05 μm or more deeper in the n ⁺ region than in the n ⁻ region. It has a source / drain diffusion region including an impurity region and a high-concentration impurity region.

It was also devised to implant impurities of opposite polarity into the n ⁻ region on the substrate surface side and outside the channel region. That is, the invention according to claim 2 is characterized in that, in the LDD-structured MOS-FET, an impurity region having characteristics opposite to those of the low-concentration impurity region is provided on the substrate surface side of the low-concentration impurity region and outside the channel region. To do.

It has also been devised to form an n ⁺ region in a semiconductor substrate region that is etched deeper than the n ⁻ region.
That is, the invention according to claim 3 is, in the MOS-FET having the LDD structure, 0.05 μm more than the n ⁻ region.
The semiconductor substrate region thus etched has an n ⁺ region formed by performing an impurity implantation step.

Further, it was devised to form a silicide layer on the n ⁺ region. That is, in the invention according to claim 4, in the MOS-FET having the LDD structure,
It is characterized in that a refractory metal silicide layer is provided on the ⁺ region.

[0010]

That is, by forming the n ⁺ region in the semiconductor substrate deeper than the n ⁻ region, the drain current flows in the substrate deep in the n ⁻ region. Therefore, the short channel effect is strong and the hot carrier breakdown voltage is improved. Further, by injecting impurities of opposite polarities into the substrate surface of the n ⁻ region and the outside of the channel region, it becomes difficult for the drain current to flow to the substrate surface, and therefore the hot carrier breakdown voltage is improved. Further, when the gate sidewall oxide film is formed by the etch back method, the surface of the semiconductor substrate can be continuously etched, so that n ⁻ can be formed without complicating the conventional process.
Regions and n ⁺ regions can be formed on the substrate at different depths. Further, it is possible to reduce the contact resistance between the wiring and the n ⁺ region by forming a silicide layer on the n ⁺ region top.

[Embodiment 1] The present invention will be described in more detail with reference to the embodiments shown in the drawings. FIG. 1 is a schematic explanatory diagram showing the overall configuration of a MOS-FET according to the present invention. The manufacturing method and function of the MOS-FET according to the present invention will be described below.

First, after forming the gate electrode 1 of polycrystalline Si, using the gate electrode 1 as a mask, phosphorus for forming the n ⁻ region 4 is implanted at an implantation angle of 7 degrees, an implantation energy of 20 KeV and a dose of 1 × 10 ¹³ cm ^−. Ion implantation is performed under condition ² . Next, the gate sidewall oxide film 3 is formed to a thickness of 0.15 μm. The gate sidewall oxide film 3 is formed by an etchback method after forming a silicon oxide film. After the oxide film is etched, the Si substrate is continuously exposed to 0.
Etch to 1 μm. Although the Si gate electrode is etched at the same time as the Si substrate is etched,
There is no problem if the thickness is 3000 Å or more. Then n ⁺ region 5
Arsenic implantation angle for forming a 7 degree, implantation energy
Implant under the conditions of 50 Kev and a dose of 5 × 10 ¹⁵ cm ^-2 . Further, in order to activate the impurities, a heat treatment is performed at 900 ° C. for 60 minutes to form an NMOS-FET having the structure shown in FIG. In the figure, the n ⁺ region 5 is formed 0.1 μm deeper than the n ⁻ region 4.

In this embodiment, the concentration of the p-type substrate is 2 ×
In the case of 10 ¹⁷ cm ^-3 , even if the gate electrode size is 0.3 μm, the p-type substrate and the n ⁻ region 4 form a shallow junction, so that the short channel effect does not affect the device characteristics. Further, n ⁺ regions 5 the n ^- since it is formed at 0.1μm deeper than the region 4, n ^- drain current of the region 4 flows through the deep portion of the substrate, so that the hot carrier breakdown voltage can be ensured over 3.3V.

[Embodiment 2] FIG. 2 shows a MOS-type device according to the present invention.
It is a schematic explanatory drawing which shows the whole structure of FET. The manufacturing method and function will be described below. Similar to the first embodiment, the gate sidewall oxide film 3 is formed to a thickness of 0.2 μm after the n ⁻ region is implanted with impurities (FIG. 2A). The gate side wall oxide film 3 is thickened to 0.2 μm in order to secure the n ⁺ / n ⁻ region spacing of the source / drain regions of 0.4 μm or more. If the n ⁺ / n ^- spacing is 0.4 μm or less, punch-through will occur between n ⁺ / n ⁻ even if the n ⁻ region 4 is a shallow junction. However, the gate side wall oxide film 3 is formed by implanting an impurity of opposite polarity into the n ⁺ region 5 to form a punch-through stopper.
It is possible to make the thickness of 0.15 μm or less.

[0015] Next, the gate sidewall oxide film 3 as a mask, n ^- implanting impurity opposite polar impurities region, n ^-
The resistance of the substrate surface side of the region 4 and the outside of the channel region is increased. As the implantation conditions, phosphorus is implanted under the conditions of an angle of 7 degrees, an energy of 30 KeV, and a dose of 2 × 10 ¹³ cm ^-2 in order to form an n ⁻ region. Further, in order to form the high resistance region 6, boron is used at an angle of 7 degrees, an energy of 15 KeV and a dose of 1 × 10 ¹³
Inject under the condition of cm ^-2 . Arsenic is then added at 200 KeV, 6 × 10 ¹⁵ cm ^-2
To form an n ⁺ region 5 in the deep portion of the substrate [FIG.
(B)].

In the present embodiment, the resistance of the n ⁻ region 4 on the substrate surface side and the outside of the channel region is increased by implanting impurities having characteristics opposite to those of the n ⁻ region 4, thereby making it difficult for a drain current to flow on the substrate surface. As a result, the hot carrier breakdown voltage is improved. Further, by using the impurity implantation conditions of the present embodiment, the maximum impurity concentration position is formed in the n ⁺ region 5 in the deeper portion of the substrate by 0.05 μm or more than in the n ⁻ region 4. Therefore, the drain current flows deeper in the n ⁻ region 4, and the hot carrier breakdown voltage is improved.

In this embodiment, since the impurity concentration on the substrate surface of the n ⁺ region 5 is low, contact resistance with the wiring may increase contact resistance. In this case, a high-melting-point metal such as titanium is formed on the contact formation region at a thickness of 2000 Å (angstrom) or more, and then silicided to form the n ⁺ region 5
It is possible to reduce the resistance of the high resistance region. Figure 2 (c)
3 is an example of a silicide structure according to the present invention, FIG. 3 is an example in which only the contact holes according to the present invention are silicidized, 7 is a refractory silicide layer, and 8 is an interlayer insulating film.

[0018]

As described above, according to the present invention,
By forming the n ⁺ region in the semiconductor substrate deeper than the n ⁻ region, the drain current flows in the substrate deep in the n ⁻ region even if the p-type substrate and the n ⁻ region are shallow junctions. Therefore, it is possible to provide a MOS-FET having a strong short channel effect and an excellent hot carrier breakdown voltage. Further, by implanting impurities of opposite polarities on the substrate surface of the n ⁻ region and the outside of the channel region, it becomes difficult for a drain current to flow on the substrate surface, and therefore, a MOS-FET excellent in hot carrier breakdown voltage.
Can be provided. In addition, since the surface of the semiconductor substrate can be continuously etched when the gate sidewall oxide film is formed by the etch back method, the n ⁻ region and the n ⁺ region can be deeply formed on the substrate without complicating the conventional process. MOS with excellent hot carrier breakdown voltage
-A FET can be provided. Further, it is possible to reduce the contact resistance between the wiring and the n ⁺ region by forming a silicide layer on the n ⁺ region top, excellent small and hot carrier breakdown voltage of the contact resistance by combining with the other embodiments A MOS-FET can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an example of an LDD structure MOS-FET according to the present invention.

2 (a), (b) and (c) are cross-sectional views showing a manufacturing process of an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an example in which only the contact hole is silicidized.

FIG. 4 is a cross-sectional view showing an LDD structure MOS-FET according to a conventional technique.

[Explanation of symbols]

1 gate electrode 2 gate oxide film 3 gate sidewall oxide film 4 n ⁻ region (low impurity concentration region) 5 n ⁺ region (high impurity concentration region) 6 high resistance region 7 high melting point silicide layer 8 interlayer insulating film

Claims (4)

[Claims] 1. A MOS-F of LDD structure having a source / drain diffusion region composed of a low impurity concentration region and a high impurity concentration region formed by implanting impurities into a semiconductor substrate.
In ET, a low impurity concentration region in which the position where the impurity concentration in the depth direction of the source / drain diffusion region is maximum is 0.05 μm or more deeper in the high impurity concentration region than in the low impurity concentration region, and A LD-structured MOS-FET having a source / drain diffusion region composed of a high impurity concentration region. 2. The LDD structure according to claim 1, wherein an impurity region having a characteristic opposite to that of the low impurity concentration region is provided on a substrate surface side and a channel region outside of the low impurity concentration region. MOS-FET. 3. The MOS-FET according to claim 1, further comprising a high impurity concentration region formed by performing an impurity implantation step in a semiconductor substrate region etched by 0.05 μm or more than the low impurity concentration substance region. LD-structured MOS-FET characterized by: 4. The MOS-F according to claim 1, wherein a refractory metal silicide layer is provided above the high impurity concentration region, and the MOS-F has an LDD structure.
ET.