JPH077497A - Bidirectional repeater circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To operate normally against noise and chattering. [Structure] Receiving comparator 2 that receives an AMI signal
To turn on the gate G ₁ to trigger a D- flip-flop 7 at the leading edge of the output pulse. Triggers to maintain the gate circuit G ₂ turns off the D- flip-flop 6 in the front edge of the wrap around it outputs pulses to the receiving comparator 4 after a predetermined time delay. The D-flip-flop 7 of the output pulse of the receiving converter 2 is reset to turn off the OR gate G ₁ to restore the initial state. Also, at the trailing edge of the output pulse of the receiving comparator 4
Reset the flip-flop 6 to turn off the OR gate and restore the initial state. Therefore, even if noise or chattering occurs, the gate circuit G ₁ ,
It is possible to restore G ₂ to the initial state, eliminate the malfunction of the gate circuits G ₁ and G ₂ , and operate stably as a repeater.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional repeater circuit for baseband signals when bidirectional data transmission is performed.

[0002]

2. Description of the Related Art FIG. 5 is a schematic configuration diagram of a general bus system network system, for example, when it is applied to an air conditioning control system. One outdoor unit 51 and a plurality of indoor units 52 are connected to one transmission line L,
A central control terminal 53 for controlling each indoor unit 52 is connected on the transmission line L. The maximum number of connected terminals and the maximum transmission distance of the network system shown in FIG. 5 are mainly determined by hardware. For example, the maximum number of connected terminals is defined by the transmission level, the transmission path, and the input / output impedance of the terminals, but if the number of connected terminals is further expanded under these restrictions, a repeater or a bridge is required.

FIG. 6 shows a network system in which a repeater 50 is used. The network 1 and the network 2 as shown in FIG. 5 are connected by the repeater 50, and the transmission signal of the transmission line L is bidirectionally transmitted by this repeater 50. To be sent to. Generally, a repeater simply amplifies a transmission signal and can be realized with simple hardware and low cost. However, depending on the specifications of the transmission signal, the repeater may not be configured with only an amplifier for amplifying the level.

In a network system such as a home bus system, with a 50% AMI waveform as shown in FIG. 7A, the level is alternately inverted in the (+) and (-) directions when digital "0". However, when the idle portion and the digital signal are "1" (thick line portion in FIG. 7A), the transmission line is open (high impedance state). Although the waveform shown in FIG. 7A is an ideal waveform,
As shown in (b), in the high impedance state, only the load resistance discharges the electric charge in the transmission line (transmission line), so that the signal waveform is distorted. That is, the distorted waveform as shown in FIG. 7B becomes the signal waveform on the actual transmission line.

A conventional block diagram of a repeater 60 of a communication system using such a bipolar signal waveform is shown in FIG. As shown in FIG. 9, the repeater 60 is configured by using two transceiver units 61 having the same configuration in the opposite direction, and the transceiver unit 6 of the repeater 60 is used.
1 is a receiving circuit for receiving the AMI signal from the first network, comparator circuits 62 and 63 for converting the AMI signal into a unipolar signal, and again a unipolar signal into a bipolar signal. And a transmission circuit 64 for converting and transmitting to the second network.
A repeater 60 is configured by a minimum configuration hardware by combining two sets of the transceiver units 61. The transceiver unit 61 on the upper side transmits a transmission signal from the network 1 to the network 2 and the transceiver unit 61 on the lower side. Thus, the transmission signal from the network 2 is transmitted to the network 1.

In the conventional repeater 60 shown in FIG. 9, the transceiver units 61 are simply combined bidirectionally, and no measures are taken to prevent signal sneaking. Therefore, when an AMI signal as shown in FIG. 8A is input to the repeater 60, the output of one transceiver unit 61 goes around to the input side of the other transceiver unit 61, and the repeater 60 as shown in FIG. 8B.
The signal waveform that has passed through becomes completely different from the original signal waveform, and there is a problem that it does not function as a repeater.

As an idea for solving this problem, a bidirectional repeater circuit as described in JP-A-1-93229 has been devised (FIG. 10). This is a stable operation with a clean signal waveform without noise, chattering, or bounce. The above-mentioned JP-A-1
The bidirectional repeater circuit shown in FIG. 10 of Japanese Patent Application Laid-Open No.-93229 discloses a receiving comparator 31 that receives a bipolar signal of the transmission path A and converts it into a unipolar signal, and a unipolar signal of the bipolar signal. A driver 32 for converting the signal to a transmission path B and transmitting it to the transmission path B, a reception comparator 33 for receiving a bipolar signal of the transmission path B and converting it into a unipolar signal, and a unipolar signal for the bipolar signal. monostable circuit 35 for controlling the transmission driver 34 to be transmitted to the transmission path a converter, an OR gate G _1, G ₂ prohibiting wraparound signals between closing of these gate G _1, G ₂ gates, It is composed of 36 etc. The repeater 30 shown in FIG. 10 drives the monostable circuits 35 and 36 by the input AMI signal,
The OR gates G ₁ and G ₂ corresponding to the transmission path on the partner side are turned off, and only one of the directions is enabled at any time, and the respective signals are waveform-shaped. Here, the output pulse width of the monostable circuits 35 and 36 is set to be longer than the pulse width of the AMI code. The output pulse widths of the monostable circuits 35 and 36 are set by the external resistor R ₁ and the capacitor C ₁ .

Next, the operation of the repeater 30 shown in FIG. 10 in the normal case will be described with reference to FIG. 11A to 11H show waveforms at points A to 10 in FIG. First, a bipolar signal as shown in FIG. 11A is input from the transmission path A to the receiving comparator 31 and converted into a unipolar signal, and the unipolar signal is transmitted from the transmitting driver 32 after a certain time delay. It is converted into a polar signal and transmitted on the transmission path B. Before time t ₁ , both monostable circuits 35 and 36 are reset, and their Q outputs (points) are at L level (see FIG. 11).
(G) and (h)), and the OR gates G ₁ and G ₂ are both in the ON state (open state). At time t ₁ , when the AMI signal is input from the transmission line A and rises to the H level at point A (see FIG. 11A), the receiving comparator 31
11C becomes L level as shown in FIG. 11C, and the output point of the OR gate G ₁ also becomes L level (see FIG. 11E). When the output of the OR gate G ₁ falls, the A input of the monostable circuit 36 falls, the monostable circuit 36 is triggered, and the resistance R ₁ changes from the Q output (point).
And outputs H level for a time determined by the capacitor C ₁ . This period is T shown in FIG. 11 (h). When the Q output of the monostable circuit 36 becomes the H level, the other monostable circuit 35 is reset to maintain the Q output (point) at the L level (see FIG. 11 (g)) and the OR gate G ₂ This OR gate G ₂ with one input of H level
Is turned off (closed state) (see FIG. 11 (f)) to prevent the transmission driver 32 from sneaking in from the reception converter 33.

At time t ₂ , the signal from the transmission line A is transmitted by the transmission driver 32 (see FIG. 11).
(See (b)), at time t ₂ when point B becomes H level, the output point of receiving comparator 33 becomes L level as shown in FIG. 11 (d), and a signal is sent to driver 34, but OR gate G _{Since 2} is off, OR gate G
This change is not output from ₂ (see FIG. 11 (f)). In other words, the OR gate G ₂ is closed to prevent sneaking from the receiving comparator 33.

Next, at time t ₃ , when the AMI signal becomes L level, the output point of the receiving comparator 31
Also, the output point of the OR gate G ₁ becomes H level (see FIGS. 11C and 11E). However, since the pulse width of the monostable circuit 36 is longer than the pulse width of the AMI signal,
Time t _{4 when} the Q output of the monostable circuit 36 is timed up
The OR gate G ₂ is in the off state until then.

At time t ₄ , the transmission driver 32
Output becomes L level (see FIG. 11B), and the output point of the receiving comparator 33 becomes H level (see FIG. 11D), but the Q signal (point) of the monostable circuit 36 Since the H level period continues, the OR gate G ₂ remains off. Also at time t ₅ the pulse to the next negative direction of the AMI signal from the transmission path A is input, the same operation is performed at time t _1. The time at _{t 6,} the transmission path AMI signal receiving comparator 33 from B
In this case, as in the above case, the monostable circuit 35 is driven and the OR gate G ₁ is turned off to prevent sneaking and prevent the AMI signal from the transmission line B from being transmitted to the transmission line A. I am trying to send it.

By thus making the pulse width of the Q output of the monostable circuits 35 and 36 longer than the pulse width of the AMI signal, the signals from the reception comparators 33 and 34 that have sneak up are OR gates G ₁ and G. are those that are blocked by _2, and is capable of transmitting Therefore to the transmission path B from the transmission line a, also a signal to the transmission line a in only one direction from the transmission path B waveform shaping to.

[0013]

The above case is the case of a clean signal waveform without noise, chattering, or bounce, and in this case, it operates normally as a repeater. However, malfunction may occur due to noise or chattering, and as a result, a normal signal waveform may not be obtained.

A case where noise is generated on the transmission path will be described with reference to FIGS. As shown in (a) of FIG. 12, the original AMI signal is input from the transmission line A at time t ₃ , but as shown in FIG. 12 (b), noise on the transmission line B occurs at time t _1. When N is generated, this noise N is received by the receiving comparator 33, and the output point of the receiving comparator 33 becomes L level (FIG. 12).
(See (d)). When the point becomes L level, OR gate G
The output (point) of ₂ becomes L level (see FIG. 12F), and the monostable circuit 35 is triggered. Therefore, the Q output (point) of the monostable circuit 35 also becomes the H level as shown in FIG. 12 (g), and the (T) H level is output during the time period including the resistor R ₁ and the capacitor C ₁ . Since the Q output of the monostable circuit 35 becomes H level, the OR gate G
₁ is turned off (closed) (see FIG. 12 (e)).
At time t ₃ , the AMI signal from the transmission line A is input, and the output (point) of the reception comparator 31 becomes L level as shown in FIG. 12C, but one input (point) of the OR gate G ₁ ) Is at the H level, the OR gate G ₁ is in the off state, and the gate is closed.
The point signal cannot be output from the OR gate G ₁ (see FIGS. 12B and 12E). That is, the noise N on the transmission line B drives the monostable circuit 35, and its Q signal (
Point) for a certain period (T) H level, and during that period (T)
Since the OR gate G ₁ is closed, the AMI signal from the transmission line A cannot be output to the transmission driver 32.

After the output of the monostable circuit 35 has timed out (see FIG. 12 (g)), when the AMI signal from the transmission line A at time t ₄ is received to turn off the OR gate G ₁ , Monostable circuit 36 via OR gate G ₁
Is driven (see FIG. 12 (h)) to turn off the OR gate G ₂ . Therefore, after the time t ₄ , the signal from the transmission line A is output to the transmission line B, but the first data is not output due to the noise N generated in the transmission line B (FIG. 12).
(See (b)). In addition, time t _2, the noise N generated in the transmission path B is when wrapping around the receiving comparator 31 with a delay of a predetermined time, AMI signal is input to the timer time of the monostable circuit 35 from the time t ₂ In case of noise N
However, in the case of FIG. 12, the noise N and the AMI signal that have sneak up overlap each other.

Further, even when chattering occurs, there is a problem that the transmission signal cannot be normally transmitted due to a malfunction similar to the case where the noise N occurs.

The present invention has been made to solve the above-mentioned conventional drawbacks, and an object of the present invention is to provide a bidirectional repeater circuit which operates normally against noise, chattering and the like. .

[0018]

Therefore, the bidirectional repeater circuit according to claim 1 has a bidirectional repeater circuit 1 provided on a transmission line between the networks, and the AMI between the two networks is provided via the bidirectional repeater circuit 1. In a data communication system adapted to transmit signals bidirectionally, a first receiving circuit 2 for receiving an AMI signal from one network, converting it into a unipolar signal and outputting the same, and this first receiving circuit A first gate circuit G ₁ that receives the output of 2 and a first transmission circuit 3 that transmits the unipolar signal of the output of the _first gate circuit G _{1 to} the other network as an AMI signal of a bipolar signal. When, a second receiving circuit 4 for converting receives an AMI signal from the other networks to unipolar signal, a second gate circuit G ₂ receiving an output of the second receiving circuit 4 Unipolar signal at the output of the second gate circuit G ₂ and the second transmission circuit 5 to be transmitted to one of the network as a AMI signal of the double polarity of the signal, the first or second receiving circuit 2 and 4 At the leading edge of the output pulse of the receiving circuit 2 that has received the AMI signal first, the gate circuit G ₁ on the transmission path side is turned from the off state to the on state, and at the trailing edge of the output pulse, the gate circuit G ₁ is turned off The gate circuit G ₁ is returned to the initial state, and is delayed for a certain period during the ON state of the gate circuit G ₁ and then circulates to the other receiving circuit 4 via the transmitting circuit 3 and is output by the receiving circuit 4 to the other gate circuit. It is characterized by including control means 7 and 6 for maintaining G ₂ in the off state and returning it to the initial state.

In the bidirectional repeater circuit according to the second aspect of the invention, the bidirectional repeater circuit 1 is provided on the transmission path between the networks, and the AMI signal between both networks is bidirectionally transmitted through the bidirectional repeater circuit 1. In the data communication system configured to do so, the AMI from one network
A first receiving circuit 2 that receives a signal, converts the signal into a unipolar signal and outputs the signal, a first gate circuit G ₁ that receives an output of the first receiving circuit 2 at one input terminal, and a first gate circuit G ₁ 1 of the gate circuit G ₁ outputs a unipolar signal to a bipolar signal of AM
A first transmitting circuit 3 for transmitting to the other network as an I signal, and a second receiving circuit 4 for receiving an AMI signal from the other network, converting it into a unipolar signal, and outputting it.
And a second gate circuit G ₂ that receives the output of the second receiving circuit 4 at one input end, and the second gate circuit G ₂
A second transmission circuit 5 for transmitting the unipolar signal of the output of 1 to one of the networks as an AMI signal of a bipolar signal,
The outputs of the receiving circuits 2 and 4 are input to the D input terminals, respectively, and triggered by the leading edge of the output pulse of the receiving circuits 2 and 4, and the inverted outputs of the receiving circuits 2 and 4 are used as outputs to output the gate circuits G ₁ and G. together by applying ₂ of the other input terminal to the oN state the gate circuit G _1, G ₂ from the off state, the gate circuit is reset at the trailing edge of the output pulse G _1, G ₂
And the two D-flip-flops 7 and 6 for turning off the switch to the initial state and receiving the AMI signal first by the first or second receiving circuit 2, 4.
The output of the one D-flip-flop 7 triggered by the leading edge of the output pulse of turns the gate circuit G ₁ on the transmission line side from the off state to the on state and is reset by the trailing edge of the output pulse. D-flip-flop 7
The gate circuit G ₁ is turned off to return to the initial state by the output of, and after a certain time is delayed during the on state of the gate circuit G ₁ , the signal is diverted to the other receiving circuit 4 via the transmitting circuit 3 and the receiving circuit 4 is received. The other D-flip-flop 6 triggered by the leading edge of the output pulse of the circuit 4 keeps the other gate circuit G ₂ in the off state and resets the D-flip-flop 6 at the trailing edge of the output pulse. It is characterized in that the gate circuit G ₂ is maintained in the off state and returned to the initial state.

[0020]

According to the bidirectional repeater circuit of the first aspect,
At the leading edge of the output pulse of the receiving circuit 2 that has previously received the AMI signal by the first or second receiving circuit 2, 4, the gate circuit G ₁ on the transmission path side is turned from the off state to the on state, and the output pulse is At the trailing edge, the gate circuit G ₁ is turned off to return to the initial state, and after a certain time delay during the on state of the gate circuit G ₁ , the transmission circuit 3 and the other receiving circuit 4 are delayed. The other gate circuit G ₂ is kept off by the output pulse of the receiving circuit 4 and is returned to the initial state.
Therefore, even if noise or chattering occurs, the gate circuits G ₁ and G ₂ are returned to the initial state at the trailing edge of the pulse, so that malfunctions of the gate circuits G ₁ and G ₂ are eliminated and the repeater operates stably. be able to.

According to the two-way repeater circuit of the second aspect, the one of the above-mentioned ones triggered at the leading edge of the output pulse of the receiving circuit 2 which has previously received the AMI signal in the first or second receiving circuit 2, 4. The output of the D-flip-flop 7 causes the gate circuit G ₁ on the transmission line side to be turned on, and the output of the D-flip-flop 7 reset at the trailing edge of the output pulse causes the gate circuit G ₁ to be turned on. ₁
Is turned off to return to the initial state, and after delaying for a certain period of time during the on state of the gate circuit G ₁ , it goes around to the other receiving circuit 4 via the transmitting circuit 3 and the leading edge of the output pulse of the receiving circuit 4 The other D-flip-flop 6 triggered by the above keeps the other gate circuit G ₂ in the off state, and resets the D-flip-flop 6 at the trailing edge of the output pulse to turn off the gate circuit G ₂ . Is maintained to return to the initial state. Therefore, even if noise or chattering occurs, the gate circuits G ₁ and G ₂ are returned to the initial state at the trailing edge of the pulse, so that malfunctions of the gate circuits G ₁ and G ₂ are eliminated and the repeater operates stably. be able to.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the bidirectional repeater circuit of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a block circuit diagram of the bidirectional repeater circuit 1.
The bidirectional repeater circuit 1 is provided between the transmission paths A and B and bidirectionally amplifies and transmits a transmission signal (AMI signal).

In FIG. 1, the bidirectional repeater circuit 1 is
Receiving comparator (first receiving circuit) that receives a bipolar AMI signal from the transmission path A and converts it into a unipolar signal
2, an OR gate (first gate circuit) G ₁ that receives the output from the receiving comparator 2, and a unipolar signal from the OR gate G ₁ is converted into a bipolar signal and transmitted to the transmission path B. Transmission driver (first transmission circuit)
3 and 3 are provided. Further, contrary to the above, a receiving comparator (second receiving circuit) 4 for converting a bipolar signal from the transmission path B into a unipolar signal, an OR gate (second gate circuit) G ₂ , and a unipolar signal. A transmission driver (second transmission circuit) 5 for converting a signal into a bipolar signal and transmitting the signal to the transmission path A is provided, and the transmission signal is bidirectionally amplified and transmitted.

Further, D-flip-flops 6 and 7 as control means and inverter gates G ₃ and G ₄ are provided, and a falling signal from the receiving comparator 2 causes a D-flip-flop circuit via the inverter gate G _3. Trigger on P7 to capture the D input signal,
The OR gate G ₁ is turned on (open state) at the output of B (B means Bar). Further, the signal sneak from the transmission driver 3 is received by the reception comparator 4, and the signal triggers the D-flip-flop 6 via the inverter gate G ₄ to output the OR gate G ₂ at its QB output. The circuit is maintained in the off state (closed state) as it is to prevent sneaking when the signal from the transmission path A is being transmitted to the transmission path B.

The operation when the transmission waveform is normal will be described below with reference to the timing chart of FIG. The waveforms A to A shown in FIGS. 2A to 2J are the waveforms A to A in FIG. First, in the initial state before time t ₁ , each point is at the H level. Then, a case of amplifying a multipolar transmission signal from the transmission line A to the transmission line B as shown in FIG. 2A will be described.

Before time t ₁ shown in FIG. 2, D-
Both the QB output (point) of the flip-flop 7 and the QB output (point) of the D-flip-flop 6 are at the H level,
The OR gates G ₁ and G ₂ are both closed. When a pulse in the positive direction of the AMI signal is input to the reception comparator 2 at time t ₁ , its output (point) is as shown in FIG.
As shown in (c), it falls and the inverter gate G ₃
Output rises and is input to the clock terminal CK of the D-flip-flop 7 to trigger the D-flip-flop 7. Since the point of the D input of the D-flip-flop 7 at that time (the output of the receiving comparator 4) is at the H level (see FIG. 2D), the D-flip-flop 7
QB output becomes the L level of its inverted output (Fig. 2
(E) refer), the other input of the OR gate _{G 1} (point) off state of the OR gate _{G 1} becomes L level (closed)
To the on state (open state). Therefore, the output (point) of the OR gate G _{1 is the same as} the output of the reception comparator 2 and is input to the transmission driver 3 (see FIG. 2 (g)).

The output of the transmitting driver 3 (B point) is outputted with a delay period of time, the positive going pulse is output at time t ₂ (see Figure 2 (b)). The output in the plus direction at time t ₂ wraps around and is input to the other receiving comparator 4, and its output (point) falls to the L level (see FIG. 2D). The output of the inverter gate G ₄ falls due to the fall of this signal, and D-
Trigger flip-flop 6 and set its QB output to H
To level. In this case at time t _2, D-the level of the D input of the flip-flop 6 (point) is a L level (see FIG. 2 (c)), QB output of the inverting (becomes H level from its Q output, an OR gate maintaining the G ₂ as it is to the off state (closed state) (see FIG. 2 (f)). Thus, when applied trigger the D- flip-flop 6 by time t _2, the outputs an inverted level of the point, the OR gate G ₂
Is maintained in the OFF state to prevent the signal from the reception comparator 4 that has been received from the transmission line B (see FIG. 2).
(See (h)).

Next, at time t ₃ , when the pulse from the transmission line A falls, the point rises to the H level (see FIG. 2 (c)), and the point D rises through the inverter gate G _3.
-Reset terminal resB at the point of flip-flop 7
(B means Bar) is set to L level (see FIG. 2 (j)), and the D-flip-flop 7 is reset. When the D-flip-flop 7 is reset, its QB output becomes H level and the point becomes H level (FIG. 2 (e)).
), The OR gate G ₁ is turned off (closed).

Then, at a time t ₄ when the signal (pulse) from the transmission path A which is output with a delay falls (see FIG. 2).
(See (b)), the output (point) of the receiving comparator 4 falls (see FIG. 2D), and the output of the inverter gate G ₄ falls due to this fall, so that D-
The flip-flop 6 is reset (see point (i) in FIG. 2). When the D-flip-flop 6 is reset, its QB output (point) becomes H level, and the OR gate G ₂
Is maintained in the off state (see FIG. 2 (f)). This time t
After ₄ , the levels at the points-in the bidirectional repeater circuit 1 become H level and the state returns to the initial state to wait for the next signal (pulse) after time t ₅ .

At time t ₅ , when the pulse of the AMI signal falls in the negative direction, the output (point) of the receiving comparator 2 also falls, so that after time t ₅ , the same operation as that after time t ₁ is performed. , The signal from the transmission line A is transmitted by the transmission driver 3 to the transmission line B with a delay of a predetermined time.

Thus, the AMI from the transmission line A or B
In the initial state of waiting for a signal, the OR gates G ₁ and G ₂ provided in the respective transmission lines in the bidirectional repeater circuit 1 are turned off (closed state), and A
The OR gate G ₁ on the side (transmission path A) that receives and receives the MI signal is triggered by the D-flip-flop 7 at the leading edge of the pulse of the AMI signal and turned on (open) by its QB output. , The D-flip-flop 6 is triggered at the leading edge of the delayed pulse of the signal and its QB output keeps the other OR gate G ₂ in the OFF state as it is to prevent the sneak. Further, the D-flip-flop 7 is reset at the trailing edge of the input pulse, and the OR gate G ₁ is returned to the off state by its QB output. Also, the D-flip-flop 6 is reset at the trailing edge of the delayed output pulse, and the OR gate G is output at the QB output.
The off state of No. ₂ is maintained as it is. In addition, transmission line B
When the AMI signal is input from, the D-flip-flop 6 is triggered at the leading edge of the input pulse and the OR gate G ₂ is turned on by its QB output. The action is taken.

Next, the case where noise is generated on the transmission path will be described with reference to the timing chart of FIG. As shown in FIG. 3B, when a single pulse noise N is generated on the transmission path B at time t ₁ , the noise N is received by the reception comparator 4, and at time t ₁ , the reception comparator 4 is received. Output (point) falls to the L level as shown in FIG. 3 (d). When the level of the point falls, the output of the inverter gate G ₄ falls and D-
Trigger flip-flop 6. When the D-flip-flop 6 is triggered, the D input (point) at the time t ₁ is at the H level (see FIG. 3C), so the QB output (point) of the D-flip-flop 6 is at the L level of its inverted output. Level (see FIG. 3 (f)). When the point becomes the L level, the OR gate G ₂ is turned on (opened).

Next, the time t at the time when the noise N falls
₂ , the output (point) of the receiving comparator 4 rises as shown in FIG. 3 (d), so that the output of the inverter gate G ₄ is lowered and the D-flip-flop 6
The reset terminal resB of is set to L level (see FIG. 3 (i)
Reset), the D-flip-flop 6 is reset. D-
When the flip-flop 6 is reset, its QB
The output point becomes the H level (see FIG. 3 (f)), and the OR gate G ₂ is turned off (closed) to restore the initial state. Therefore, even if the noise N is generated, the levels 1 to ₃ shown in FIG. 1 from the time t ₂ to the time t ₃ are returned to the H level state, that is, the initial state as shown in FIG. Waiting for the transmission signal,
The influence of the noise N can be ignored. Note that the case of FIG. 3 shows a case where the AMI signal from the transmission line A is input after the above-described noise N has occurred on the transmission line B at time t.
₃ shows the case where the signal from the transmission line A is input. Further, here, with the input of the noise N, the time t ₁
Since the OR gate G ₂ is in the ON state at
This is a case where the noise N is output from the transmission driver 5 and the noise N is sneak into the reception comparator 2 to be received. The sneak noise N (hatched portion in FIG. 3A) and the transmission line A It is the portion where the AMI signal from the signal overlaps. It should be noted that after the noise N sneaking in, A from the transmission line A
When the MI signal is input, it is the same as in the case of chattering described later, so the description will be given later.

Now, at time t ₃ , the AM from the transmission line A
Although so that the I signal is received by the receiving comparator 2, at time t _3, since the state is returned to the initial state in ~ point as described above, i.e. the OR gate G _1, G _2, respectively When the AMI signal from the transmission path A is received, the operation is performed in the same manner as in the case of FIG. 2, and the signal is transmitted from the transmission driver 3 to the transmission path B. It is supposed to do. Therefore, at time t ₃ , the OR gate G ₁ is turned on, and data is sent to the transmission line B at time t ₄ delayed by a predetermined time (see FIG. 3B). Therefore, even when the noise N is generated, the AMI signal can be transmitted by operating the OR gate G ₁ normally without causing malfunction.

Next, the case where chattering occurs will be described with reference to the timing chart of FIG. Figure 4
Waveforms A to A shown in (a) to (j) are waveforms at points A to A in FIG. Also, when chattering occurs at the last part of the AMI signal from the transmission line A when the AMI signal is transmitted from the transmission line A to the transmission line B and then from the transmission line B to the transmission line A. is there. When chattering occurs at time t ₁ , the output point of the reception comparator 2 becomes L level as shown in FIG. 4C, which causes the output of the inverter gate G ₃ to become H level and D- Trigger flip-flop 7.
At this time, since the bidirectional repeater circuit 1 is in the initial state, the point level is H level, and therefore the QB output of the D-flip-flop 7 becomes L level. Therefore, the point becomes L level, and the OR gate G ₁ is turned on (opened). Therefore, the output (point) of the OR gate G ₁
Outputs the signal at the L level, that is, the point as it is, as shown in FIG.

When the level at the point A falls at time t ₂ , the output point of the receiving comparator 2 is shown in FIG.
, The output of the inverter gate G ₃ becomes L level, and the D-flip-flop 7
Is reset (see point (j) in FIG. 4). When D- flip-flop 7 is reset, the QB output becomes H level, one input terminal of the OR gate G ₁ (point) is turned off (closed) to the OR gate G ₁ as H level (Fig. 4 ( See e)). That is, the initial state is restored. Therefore, before the time t ₃ when the signal from the transmission line A is input, each part of the bidirectional repeater circuit 1 returns to the initial state and waits for the input of the AMI signal. When the AMI signal is input from the transmission line A at time t ₃ , the point becomes L level and the point becomes L level, respectively, and the OR gate G ₁ is turned on. That is, the signal from the transmission line A is transmitted from the transmission driver 3 to the transmission line B via the OR gate G ₁ .

Next, at time t ₄ , the chattering pulse generated on the transmission line A spills over to the receiving comparator 4, the output point of the receiving comparator 4 is set to L level, and the output of the inverter gate G ₄ is set to H level. D-
Trigger flip-flop 6. Since the D input (point) of the D-flip-flop 6 is L level (see FIG. 4C), the QB output is set to H level and the level of one input terminal (point) of the OR gate G ₂ is set to H level. Then, the OR gate G ₂ is maintained in the OFF state as it is (see FIG. 4F). Therefore, since the OR gate G ₂ is in the OFF state, the passage of the pulse generated by the chattering is blocked and the sneak into the reception comparator 2 is prohibited.

[0038] At time _{t 5,} B point fallen by point rise (see FIG. 4 (d)), through the inverter gate _{G 4} resets the D- flip-flop 6 (see FIG. 4 (i)). When the D-flip-flop 6 is reset, its QB output becomes H level,
The off state of the OR gate G ₂ is maintained (see FIG. 4 (f)).

[0039] Next wraps around it at time t ₆ when the signal rises (see FIG. 4 (b)), similarly to the above falling points of the output of the receiving comparator 4 (Fig. 4
(See (d)), the D-flip-flop 6 is triggered via the inverter gate G ₄ . When the D-flip-flop 6 is driven, since the D input (point) is at the L level (see FIG. 4D), its QB output (point) becomes the H level, and the OR gate G ₂ is maintained in the OFF state, The signal from the receiving comparator 4 that has sneak in is blocked by the OR gate G ₂ .

At time t ₇ , the point A falls and the output point of the receiving converter 2 rises (see FIG. 4).
(See (c)), the output of the inverter gate G ₃ becomes L level, and the D-flip-flop 7 is reset (FIG. 4).
(See (j)). When the D-flip-flop 7 is reset, its QB output becomes H level (see FIG. 4 (e)), and the point is set at H level to turn off the OR gate G ₁ (closed state).

[0041] At time t ₈ chattering occurs after the signal, falling points of the output of the receive Konbareta 2 (see FIG. 4 (c)), trigger the D- flip-flop 7. In the time t _8, the D- flip-flop 7 in D of the output of the input receiving comparator 4 is point because L level, the D- flip-flop 7 Q
B output becomes H level, and the point becomes H level (see FIG.
(See (e)), the OR gate G ₁ is maintained in the OFF state.

Therefore, since the OR gate G ₁ is maintained in the OFF state, passage of the pulse after the time t ₈ is blocked by the OR gate G ₁ . Thus the pulse at time _{t 8} ~ time _{t 9} shown in FIG. 4 (a), an OR gate G
Since it is not output from ₁ , as shown in FIG.
It does not appear on the dots.

When the pulse at the point A falls at time t ₉ , the output point of the receiving comparator 2 is changed to that shown in FIG.
As shown in (c), it rises and the inverter gate G ₃
The D-flip-flop 7 is reset via the
(See (j)). When the D-flip-flop 7 is reset, its QB output becomes H level, and the point is set at H level to keep the OR gate G ₁ in the OFF state as it is (see FIGS. 4 (e) and 4 (g)).

[0044] Referring now falls point B stands at time _{t 10} of the wrapped around it signals, in terms of the output of the receiving comparator 4 rises (see FIG. 4 (d)), through the inverter gate _{G 4} D-flip Resets the loop 6 (see FIG. 4 (j)). When the D-flip-flop 6 is reset, its QB output becomes H level, and the point is maintained at H level as it is to continuously maintain the off state of the OR gate G ₂ (see FIG. 4 (f)). Thus, at time t ₁₀ and subsequent even if chattering on the transmission path A, each level-point is returned to the initial state, will wait for the reception of AMI signal from the transmission line B.

[0045] At time t _11, if the AMI signal is input from the transmission line B, Fig. 4 as shown in (b) falls B point falling, falling points of the output of the receiving comparator 4 (Fig. 4 (See (d)), inverter gate G
Trigger the D-flip-flop 6 via ₄ .
At this time, since the level of the D input (point) of the D-flip-flop 6 is the H level (see FIG. 4C), the inverted L level is output as the QB output, and the point becomes the L level (see FIG. 4 (f). )), The OR gate G ₂ is switched from the OFF state to the ON state, and a signal is output from the output (point) of the OR gate G ₂ . The signal to the transmission path A via a transmission driver 5 at time t ₁₂ delayed a predetermined time is to be transmitted (see Figure 4 (a)). Therefore, even if chattering occurs in the transmission line A, even if the AMI signal is input from the transmission line B next time, the AMI signal can be output to the transmission line A delayed for a certain time without causing the OR gate G ₂ to malfunction. Can be performed (time t in FIGS. 4A and 4B)
₁₁ See ~t _12). Thereafter, as in the case of FIG. 2, the AMI signal from the transmission line B is transmitted to the transmission line A.

[0046]

According to the bidirectional repeater circuit of the first aspect, the gate circuit on the transmission line side is provided at the leading edge of the output pulse of the receiving circuit which has received the AMI signal first by the first or second receiving circuit. The gate circuit is switched from the off state to the on state, the gate circuit is turned off at the trailing edge of the output pulse to return to the initial state, and the transmitter circuit is delayed for a certain period during the on state of the gate circuit. After that, the other gate circuit is circulated to the other receiving circuit and the other gate circuit is maintained in the off state by the output pulse of the receiving circuit to return to the initial state. Therefore, even if noise or chattering occurs, the gate circuit is returned to the initial state at the trailing edge of the pulse, so that malfunction of the gate circuit can be eliminated and the repeater can operate stably.

According to another aspect of the bidirectional repeater circuit of the present invention, one of the D-flip-flops is triggered by the leading edge of the output pulse of the receiving circuit which has previously received the AMI signal by the first or second receiving circuit. The gate circuit on the transmission line side from the off state to the on state by the output of the output circuit, and the gate circuit is turned off by the output of the D-flip-flop reset at the trailing edge of the output pulse to return to the initial state. Then, after delaying for a certain period of time during the ON state of the gate circuit, it wraps around to the other receiving circuit via the transmitting circuit, and the other gate is driven by the other D-flip-flop triggered at the leading edge of the output pulse of the receiving circuit. The circuit is kept off and the D
-The flip-flop is reset to maintain the off state of the gate circuit and return to the initial state. Therefore, even if noise or chattering occurs, the gate circuit is returned to the initial state at the trailing edge of the pulse, so that malfunction of the gate circuit can be eliminated and the repeater can operate stably.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of a bidirectional repeater circuit of the present invention.

FIG. 2 is a timing chart when the waveform of the embodiment of the present invention is normal.

FIG. 3 is a timing chart when noise is generated according to the embodiment of this invention.

FIG. 4 is a timing chart when chattering occurs in the embodiment of the present invention.

FIG. 5 is a schematic configuration diagram showing a general air conditioning network.

FIG. 6 is a schematic configuration diagram when a system is expanded using a repeater.

FIG. 7A is a diagram showing an ideal AMI waveform.
(B) is a figure which shows the signal waveform in an actual transmission line.

8A is a diagram showing an input waveform of the repeater shown in FIG. 9. FIG. FIG. 10B is a diagram showing an output waveform of the repeater shown in FIG. 9.

FIG. 9 is a block diagram showing a basic configuration of a conventional repeater.

FIG. 10 is a block circuit diagram of another conventional bidirectional repeater circuit.

11 is a timing chart in the case of a normal waveform in FIG.

12 is a diagram showing a timing chart when noise is generated in the circuit of FIG.

[Explanation of symbols]

1 bidirectional repeater circuit 2 reception comparator 3 transmission driver 4 reception comparator 5 transmission driver 6 D-flip-flop 7 D-flip-flop G ₁ OR gate G ₂ OR gate G ₃ inverter gate G ₄ inverter gate

Claims (2)

[Claims] 1. Data in which a bidirectional repeater circuit (1) is provided on a transmission line between the networks, and an AMI signal between both networks is bidirectionally transmitted through the bidirectional repeater circuit (1). In a communication system, a first receiving circuit (2) that receives an AMI signal from one network, converts it into a unipolar signal, and outputs it, and a first receiving circuit (2) that receives the output of this first receiving circuit (2). a gate circuit (G _1), a first transmission circuit for transmitting the unipolar signal at the output of the first gate circuit (G ₁₎ as AMI signals double polarity of the signal to the other network (3) , A second receiving circuit (4) for receiving the AMI signal from the other network, converting it into a unipolar signal, and outputting the same, and
Of the second gate circuit (G
₂ ), a second transmission circuit (5) for transmitting the unipolar signal output from the _second gate circuit (G ₂ ) to one of the networks as an AMI signal of a bipolar signal, and the first or the above. At the leading edge of the output pulse of the receiving circuit (2) that has previously received the AMI signal in the second receiving circuit (2) (4), the gate circuit (G ₁ ) on the transmission line side is changed from the off state to the on state. , The gate circuit (G ₁ ) is turned off at the trailing edge of the output pulse to return to the initial state, and the transmitter circuit (3) is delayed for a certain period of time during the on state of the gate circuit (G ₁ ). And control means (7) (6) for returning to the initial state by keeping the other gate circuit (G ₂ ) in the off state by the output pulse of the other receiving circuit (4) after passing through the other. Two-way repeat characterized by having Circuit. 2. Data in which a bidirectional repeater circuit (1) is provided on a transmission line between the networks, and an AMI signal between both networks is bidirectionally transmitted through the bidirectional repeater circuit (1). In a communication system, a first receiving circuit (2) for receiving an AMI signal from one network, converting it to a unipolar signal and outputting the same, and an output of the first receiving circuit (2) for one input The first gate circuit (G ₁ ) received at the end and the first gate circuit (G _1
1 ) A first transmission circuit (3) for transmitting the unipolar signal of the output of ₁ ) as an AMI signal of a bipolar signal to the other network, and receiving the AMI signal from the other network and converting it to a unipolar signal. A second receiving circuit (4) for converting and outputting, a second gate circuit (G ₂ ) for receiving the output of the second receiving circuit (4) at one input terminal, and this second gate circuit The outputs of the second transmission circuit (5) for transmitting the unipolar signal of the output of (G ₂ ) to one network as the AMI signal of the bipolar signal and the outputs of the both reception circuits (2) and (4) are D Input to each input terminal and receive circuit (2)
Triggered by the leading edge of the output pulse of (4), the inverted output of the receiving circuit (2) (4) is used as an output and the other input end of the gate circuit (G ₁ ) (G ₂ ) is applied to the gate circuit (G ₁ ). Two D's that turn G ₁ ) (G ₂ ) from the off state to the on state and reset the gate circuits (G ₁ ) (G ₂ ) to the off state by resetting at the trailing edge of the output pulse. -Comprising flip-flops (7) (6),
In the first or second receiving circuit (2) (4), A
The one D-flip-flop (7) triggered by the leading edge of the output pulse of the receiving circuit (2) receiving the MI signal.
Of the gate circuit (G ₁ ) on the side of the transmission line from the OFF state to the ON state by the output of the above-mentioned output circuit, and the gate circuit (G ₁ ) is output by the output of the D-flip-flop (7) reset at the trailing edge of the output pulse. ) Is turned off to return to the initial state, the gate circuit (G ₁ ) is delayed for a certain period of time during the on state, and then circulates to the other receiving circuit (4) through the transmitting circuit (3). The other D-flip-flop (6) triggered at the leading edge of the output pulse of (4) keeps the other gate circuit (G ₂ ) in the off state, and the D-flip-flop at the trailing edge of the output pulse. A bidirectional repeater circuit, wherein (6) is reset to maintain the off state of the gate circuit (G ₂ ) and return to the initial state.