JPH077701A - Parity signal generation circuit for plasma display - Google Patents

Abstract

(57) [Abstract] [Purpose] A video signal (horizontal frequency of about 15
(KHz) video signal is displayed, and when a video signal input and a sync signal are input separately, it is an object of the present invention to provide a parity signal generation circuit that generates a parity signal from the input sync signal. To do. [Structure] A monostable multivibrator 3 which outputs a signal having a pulse width corresponding to a time constant connected to a timing CR pin in synchronization with a horizontal synchronizing signal of a video signal input, and an input from the monostable multivibrator 3 are provided. Data input,
And a D-type flip-flop 7 which latches a vertical synchronizing signal of a video signal input and outputs a parity signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly to a parity signal generating circuit.

[0002]

2. Description of the Related Art A plasma display panel used in a plasma display device has been developed with a vertical display line number of about 480. On the other hand, a normally used NTSC television signal is A horizontal frequency of about 15 KHz and a field frequency of about 60 Hz are used, and the number of scanning lines in one field is 26.
It is 2.5. Therefore, when a normal NTSC television signal is displayed on the plasma display panel as it is, it is displayed only on about half of the vertical direction of the screen. Therefore, the parity signal is input to the plasma display display device and the same video signal input is performed. The scanning lines are written in different display lines of the plasma display panel so that they can be displayed on the entire screen of the plasma display panel. A conventional parity signal generation circuit uses a sync separation IC to extract a sync signal from a composite signal input and perform signal processing to generate the sync signal.

[0003]

Therefore, when the video signal is input after being separated into the primary color signal (RGB signal) and the synchronizing signal, the same circuit cannot be used because the conventional circuit is for the composite signal. However, the video signals that can be input were limited. The present invention provides a parity signal generation circuit capable of generating a parity signal from an input synchronization signal when the video signal input and the synchronization signal are input separately, and expands the types of input video signals. The purpose is to do.

[0004]

A parity signal generating circuit for a plasma display according to a first invention of the present application is a pulse synchronizing with a horizontal synchronizing signal of a video signal input and connected to a timing CR pin according to a time constant. A monostable multivibrator that outputs a signal of a width, and a D-type flip-flop that receives the input from the monostable multivibrator as a data input and latches and outputs the vertical sync signal of the video signal input are provided. To do. A parity signal generating circuit for a plasma display according to a second invention of the present application is the same as a first D-type flip-flop which connects one of output pins to an input pin and latches and outputs a vertical synchronizing signal of a video signal input. A signal having a pulse width corresponding to a time constant connected to a switching device in which each output pin of the first D-type flip-flop is connected to an input side and a horizontal sync signal of a video signal input and connected to a timing CR pin. From a monostable multivibrator that outputs the data, and a second D-type flip-flop that receives the input from the same monostable multi-vibrator as a data input and latches and outputs the latched output signal from the first D-type flip-flop. According to the latch output signal from the second D-type flip-flop, the switching device switches the signal on the input side and outputs the signal. .

[0005]

In the first structure of the present invention, the D-type flip-flop latches and outputs the data input generated from the horizontal synchronizing signal by the vertical synchronizing signal of the video signal input. A pulse signal that is inverted between the even field and the odd field due to the phase difference with the signal is output from the D-type flip-flop. In the second configuration of the present invention, one of the output pins is connected to the input pin in the first D-type flip-flop so that it is latched and output by the vertical synchronizing signal of the video signal input, and each latch output is switched. The control circuit composed of the monostable multivibrator and the second D-type flip-flop selects one of them according to the phase difference between the horizontal synchronizing signal and the vertical synchronizing signal and outputs the selected one from the switching device. Therefore, it is possible to output a pulse signal that alternately selects and inverts a predetermined polarity for the even field and the odd field. Therefore, if the pulse signal is input as a parity signal to the plasma display display together with the video signal input, the video signal input can be displayed on the entire screen of the plasma display panel.

[0006]

1 is a block diagram showing a first embodiment of a parity signal generating circuit for a plasma display according to the present invention, and FIGS. 2 (A) and 2 (B) show the operation of the embodiment of FIG. FIG. 3 is a timing diagram to be described, and the embodiment of FIG. 1 will be described below with reference to FIGS. 2 (A) and 2 (B). The vertical sync signal waveform of the video signal input to the plasma display device is input to the inverter 6 via the input terminal 1, and the horizontal sync signal waveform of the video signal is input to the monostable multivibrator 3 via the input terminal 2. ing. The inverter 6 inverts the polarities of the input vertical synchronizing signal and the waveform, outputs the waveform as a waveform, and inputs it to the D-type flip-flop 7 as a latch signal.

The timing CR pin of the monostable multivibrator 3 is connected to the timing adjusting capacitor 4 and the variable resistor 5, and the monostable multivibrator 3 synchronizes with the input horizontal synchronizing signal to obtain the timing. A signal waveform having a pulse width corresponding to the time constant of the capacitor 4 and the variable resistor 5 connected to the CR pin for output is output and input to the D-type flip-flop 7 as a data input. The values of the capacitor 4 and the variable resistor 5 are selected and determined, and the variable resistor 5 is adjusted to change the pulse width like a waveform, and D
The flip-flop 7 latches and outputs the H level portion of the waveform at the rising edge of the waveform. Therefore, an L level pulse signal having a waveform is output from the Q bar output terminal of the D flip-flop 7.

FIG. 2 is a diagram showing the timing when a synchronizing signal of an interlaced video signal is input,
The figure (A) shows an even field, and the figure (B) shows an odd field. The even field is as described above, and the odd field is described below. The phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal with respect to the waveform is a waveform in the even field and a waveform 'in the odd field. Monostable multivibrator 3
Then, similarly to the above, a signal waveform 'having a pulse width corresponding to the time constants of the capacitor 4 and the variable resistor 5 connected to the timing CR pin is output and input to the D-type flip-flop 7 as a data input. Since the D-type flip-flop 7 latches the L-level portion of the waveform 'at the rising edge of the waveform, the H-level pulse signal of the waveform' is output from the Q-bar output terminal of the D-type flip-flop 7.

Therefore, since the waveform is output in the even field and the waveform 'is output in the odd field,
It is possible to output a parity signal whose polarity is inverted for each field. When a normal NTSC TV signal interlaced video signal using a horizontal frequency of about 15 KHz and a field frequency of about 60 Hz is input to a plasma display display device for display, the parity signal is input to the plasma display display device together with the video signal input. If input, the video signal input can be displayed on the entire screen of the plasma display panel.

FIG. 3 is a block diagram showing a second embodiment of the parity signal generating circuit of the plasma display of the present invention, and FIGS. 4A and 4B explain the operation of the embodiment of FIG. 3 is a timing diagram of the embodiment shown in FIG. 4 and will be described below with reference to FIGS. 4 (A) and 4 (B). In the figure, the same components as those shown in FIG. 1 are designated by the same symbols. The vertical synchronizing signal of the video signal input to the plasma display device is input to the inverter 13 of the parity signal generating unit 12 via the input terminal 11, and the horizontal synchronizing signal of the same video signal of the control unit 16 is input via the input terminal 2. Input to the monostable multivibrator 3.

The inverter 6 inverts the polarity of the input vertical synchronizing signal, outputs it as a waveform, and inputs it to the D-type flip-flop 14 as a latch signal. The D-type flip-flop 14 connects the Q-bar output pin to the input pin and latches and outputs the signal with the vertical synchronizing signal. The D-type flip-flop 14 outputs from each output pin, Q output and Q-bar output pin. Respectively output a waveform and a waveform, and connect each output to the input side of the switch 15. The waveforms and the waveforms are pulse signals whose polarities are mutually inverted, and the polarities of the waveforms may be switched depending on the timing during circuit operation.

Therefore, the control unit 16 selects and outputs a pulse signal having a predetermined polarity.
The operation will be described below. The timing CR pin of the monostable multivibrator 3 is connected to the timing adjustment capacitor 4 and the variable resistor 5, and the monostable multivibrator 3 synchronizes with the input horizontal synchronizing signal and waveform for timing. A signal and a waveform having a pulse width corresponding to the time constant of the capacitor 4 and the variable resistor 5 connected to the CR pin are output and input to the data input pin of the D-type flip-flop 7. On the other hand, the Q output of the D-type flip-flop 14 is branched and the pulse signal waveform is input to the D-type flip-flop 7 as a latch input.

When the video signal input is an interlace system, there are two cases of the phase relationship of the horizontal sync signal with respect to the vertical sync signal. Therefore, with respect to the latch input waveform, the waveform and the phase relationship of are as shown in FIG. And (B)
As shown in, two cases occur. For example, the values of the capacitor 4 and the variable resistor 5 are selected and determined, and the variable resistor 5 is adjusted to change the pulse width of the waveform to form a waveform. In FIG. The level portion is latched and output at the rising edge of the waveform, and in the case of FIG. 4B as well, the pulse width of the waveform'is changed to form the waveform ', and the waveform is output by the D-type flip-flop 7.
The H level part of is latched and output at the rising edge of the waveform. Therefore, in the case of FIG. 4A, the L level signal shown in the waveform is obtained from the Q output of the D-type flip-flop 7, and in the case of FIG. 4B, the H level signal shown in the waveform '. can get.

When the Q output of the D-type flip-flop 7, the waveform or the waveform 'is input to the control terminal of the switching device 15 and the waveform is input to the switching device 15, the switching device 1
When the waveform is selected from 5 and output as a waveform, and the waveform 'is input to the switch 15, the waveform is selected from the switch 15 and output as the waveform'. Therefore,
As shown in FIG. 4 (A), when the L level portion of the waveform is latched by the waveform, an H level signal is output from the switch 15, and as shown in FIG.
When the level part is latched by the waveform, the switch 15
When the video signal input is an interlace signal, the L level signal is output from the
Moreover, it is possible to output a reversed parity signal.

When a normal NTSC television signal interlaced video signal using a horizontal frequency of about 15 KHz and a field frequency of about 60 Hz is input to a plasma display device for display, the parity signal is input together with the video signal on the plasma display. When input to the display device, the video signal input can be displayed on the entire screen of the plasma display panel. Horizontal frequency about 1
When displaying a non-interlaced video signal of a personal computer using 5 KHz and a field frequency of about 60 Hz, select a waveform (waveform) to be inverted for each field from the switcher 15 based on the phase relationship between the horizontal sync signal and the vertical sync signal. Then, the video signal input is displayed as a parity signal together with the video signal input to the plasma display display device, so that the video signal input can be displayed on the entire screen of the plasma display panel.

[0016]

As described above, according to the present invention,
Horizontal frequency about 15KHz, field frequency about 60Hz
In the case of displaying the video signal of, when the video signal input and the synchronization signal are input separately, it is possible to provide a parity signal generation circuit that generates a parity signal based on the input synchronization signal, If input to the plasma display display together with the video signal input, the video signal input can be displayed on the entire screen of the plasma display panel, and the types of video signals that can be input can be expanded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a parity signal generating circuit of a plasma display according to the present invention.

2A and 2B are timing diagrams illustrating the operation of the embodiment of FIG.

FIG. 3 is a block diagram showing a second embodiment of the parity signal generating circuit of the plasma display of the present invention.

4A and 4B are timing diagrams illustrating the operation of the embodiment of FIG.

[Explanation of symbols]

 1 Input Terminal 2 Input Terminal 3 Monostable Multivibrator 4 Capacitor 5 Resistor 6 Inverter 7 D-Type Flip-Flop 11 Input Terminal 12 Parity Signal Generator 13 Inverter 14 D-Type Flip-Flop 15 Switcher 16 Controller

Claims (2)

[Claims] 1. Synchronizing with a horizontal synchronizing signal of a video signal input,
A monostable multivibrator that outputs a pulse width signal corresponding to the time constant connected to the timing CR pin and the input from the monostable multivibrator are used as data inputs, and latched by the vertical sync signal of the video signal input. A parity signal generation circuit for a plasma display, which is composed of an output D flip-flop. 2. A first D-type flip-flop that connects one of the output pins to the input pin and latches and outputs the vertical synchronizing signal of the video signal input, and an output of each of the first D-type flip-flop. A switch with a pin connected to the input side, a monostable multivibrator that outputs a pulse width signal according to the time constant connected to the timing CR pin in synchronization with the horizontal sync signal of the video signal input, A second D-type flip-flop which receives the input from the stable multivibrator as a data input, and latches and outputs the data with the latch output signal from the first D-type flip-flop. The parity signal generating circuit of the plasma display, wherein the switching device switches and outputs the signal on the input side according to the latch output signal.