JPH06311384A - Changeover circuit for pdp display control signal - Google Patents

Abstract

(57) [Abstract] [Purpose] Horizontal sync signal frequency is relatively low (15 KHz
Etc.) The PDP display control signal when the video signal is displayed on the PDP is switched to an appropriate circuit side. A switching circuit 4 for switching between a first display control signal S3 generated from an interlaced vertical synchronization signal and a second display control signal S5 generated from a non-interlaced vertical synchronization signal, and a first input. The S3 is input to the end D1, the output signal of the first output end Q1 is input to the second input end D2, and the second output end Q2, the third input end D3, and the third output end Q3, respectively. And a flip-flop circuit 5 using a vertical synchronizing signal as a clock signal, the output signals of the first and second output terminals, and the signal of the output terminal is input to the third input terminal. Exclusive OR gate 6
And a switching circuit 4 according to a signal from the third output terminal.
To select the desired display control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention provides a proper PDP display control signal when a video signal having a relatively low horizontal synchronizing signal frequency (15 KHz, etc.) is displayed on a PDP (plasma display panel). Of the PDP display control signal switching circuit.

[0002]

2. Description of the Related Art In recent years, research into commercialization of image display devices using PDPs has been actively conducted. Commercialization of this PDP is also being actively considered in a multi-scan monitor that uses a plurality of types of video signals having different signal formats such as horizontal frequency as an input source. In this multi-scan monitor, when the horizontal frequency is a low video signal such as 15 KHz, the horizontal line of the PDP is set to 2 because of the characteristics of the PDP.
It is necessary to scan as one set. This is because the vertical size becomes about half of the normal size without scanning in this way. Therefore, the PDP display control signal must be such that the above scanning can be performed when the horizontal frequency is low. By the way, the display control signal can be generated from the vertical synchronizing signal, but the generating means differs depending on whether the video signal, that is, the vertical synchronizing signal is of the interlace system or the non-interlace system.
Therefore, it is necessary to have a function of providing a generation circuit for each system and automatically switching the obtained display control signals according to this system. It can be said that this function is a peculiar property of PDP display.

[0003]

Therefore, when the horizontal frequency is low (15 KHz, etc.) and the video signals of both the interlace system and the non-interlace system are displayed on the PDP, it is a problem to have the above function. . An object of the present invention is to provide a PDP display control signal switching circuit as one method for solving this problem.

[0004]

The present invention provides a display control signal for a PDP, which is a first display control signal generated from an interlaced vertical synchronization signal and a first display control signal generated from a non-interlaced vertical synchronization signal. A switching circuit for switching between the second display control signal and a first input terminal to which the first display control signal is input and which corresponds to the first input terminal.
The output signal of the output terminal of the second input terminal is input to the second input terminal, and the second output terminal corresponding to the second input terminal, the third input terminal, and the third output corresponding to the third input terminal. A flip-flop circuit provided with each end and using the vertical synchronizing signal as a clock signal, and the output signals of the first and second output ends are input, and the signal of the output end is input to the third input end. And an exclusive OR gate for switching the switching circuit according to the output signal from the third output terminal, and when the vertical synchronizing signal is an interlace type signal, the first display control signal is selected, and the non-interlace type is selected. In the case of the above signal, a PDP display control signal switching circuit for selecting the second display control signal is provided.

[0005]

According to the vertical synchronizing signal separated from the composite video signal, the first display control signal and the second display control signal generated separately are sent to the switching circuit. on the other hand,
A switching signal compatible with an interlace system and a non-interlace system by a circuit including a flip-flop to which a vertical synchronizing signal of a predetermined polarity, a first display control signal, a signal fed back from the output side, etc., and an exclusive OR gate are input. Is obtained. This switching signal switches the switching circuit to select a desired display control signal.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PDP display control signal switching circuit according to the present invention will be described below with reference to the drawings. 1 is a block diagram of an essential part showing an embodiment of a PDP display control signal switching circuit according to the present invention, and FIG. 2 is a principle waveform diagram of the coded portions in FIGS. Shows the case where the video signal (vertical synchronizing signal) is the interlace system, and FIG. In FIG. 1, S1
Is a composite video signal, 1 is a circuit for separating the vertical synchronizing signal S2 from the video signal S1, and a first display control signal generating circuit for generating a first display control signal S3 used in the case of the interlace system ( Specifically, it is an IC, and is hereinafter referred to as a "first display control signal generation circuit") 2 is for inverting the polarity of the vertical synchronization signal S2 output from the first display control signal generation circuit. The inverter 3 is a second display control signal generation circuit that generates a second display control signal for the non-interlaced mode,
Reference numeral 4 is a switching circuit, 5 is a flip-flop provided with 3 input / output terminals and a clock signal input terminal, 6 is an exclusive OR gate, and 7 is a PDP (plasma display panel).

Next, the operation of the present invention will be described separately for the case where the video signal S1 is of the interlace system and the case of the non-interlace system. (1) Interlace system Vertical sync signal when video signal S1 is interlace system
S2, the output of the inverter 2 and the first display control signal S3 are shown in FIG.
It becomes like (A), (B), (B), and (C). The principle waveform diagrams (a) and (b) are determined by the first display control signal generation circuit 1 which is an IC. Then, the first display control signal S3 is input to the first input terminal (D1) of the flip-flop 5, and the inverted vertical synchronizing signal from the inverter 2 is also input as a clock signal. As a result, due to the principle operation of the flip-flop 5, the signal shown in (d) is output to the first output terminal (Q1) corresponding to the first input terminal (D1). Since the output of the first output terminal (Q1) is the input signal of the second input terminal (D2), the second input terminal (D2)
The signal shown in (e) is output to the second output terminal (Q2) corresponding to 2).

Since the input signals of the exclusive OR gate 6 are the Q1 output (d) and the Q2 output (e), the output of the exclusive OR gate 6 is "high (H) as shown in FIG. ) ” Since the output (f) of the exclusive OR gate 6 is used as the input signal of the third input end (D3) of the flip-flop 5, the third output end (Q3) corresponding to the third input end (D3) ), A "high (H)" signal as shown in FIG. This Q3 output becomes the switching signal S4 in the case of the interlace system. When the switching signal S4 is "high (H)", the switching circuit 4 is set to the a side, and as a result, the first display control signal S3 is selected and sent to the PDP 7. As a result, the required display control is performed.

(2) Non-interlaced system When the video signal S1 is a non-interlaced system, the vertical synchronizing signal S2 and the output of the inverter 2 are (a) and (b) in FIG. 2 (B).
Although the same as in the case of the interlace system as shown in FIG. 3, the first display control signal S3 is a signal fixed at the "high (H)" level as shown in FIG. This is determined by the first display control signal generation circuit 1 which is an IC as described above. With the same clock signal (b) as in the case of the interlace system, the Q1 to Q3 outputs of the flip-flop 5 and the D2 input when the D1 input is "high (H)" constant,
D3 input and the like are exclusive OR with the flip-flop 5 described above.
From the principle operation of the gate 6, the Q1 output and the D2 input become “high (H)” as shown in (d), and therefore the Q2 output also becomes “high (H)” as shown in (e). Exclusive O
The output (= D3 input) of the R gate 6 becomes "low (L)" as shown in FIG. As a result, a "low (L)" signal as shown in (g) is output to the output terminal Q3. This Q3 output becomes the switching signal S4 when the non-interlaced method is used. When the switching signal S4 is "low (L)", the switching circuit 4 is set to the b side, and as a result, the second display control signal S5 is selected and sent to the PDP 7. As a result, the required display control is performed. As described above, it is possible to automatically select a required display control signal depending on whether the video signal is the interlace system or the non-interlace system.

[0010]

As described above, according to the present invention, when a video signal having a low horizontal frequency is projected on the PDP, the P
The display control signal supplied to the DP can be an appropriate signal for each of the interlace system and the non-interlace system. Therefore, the present invention is significant in that it solves one of the problems in the PDP conversion of the multi-scan monitor.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a PDP display control signal switching circuit according to the present invention.

2A and 2B are principle waveform diagrams of the coded portions in FIGS. 1A to 1G, in which FIG. 2A shows the case of the interlace system and FIG. 2B shows the case of the non-interlace system.

[Explanation of symbols]

 1 First Display Control Signal Generation Circuit 2 Inverter 3 Second Display Control Signal Generation Circuit 4 Switching Circuit 5 Flip Flop 6 Exclusive OR Gate 7 PDP (Plasma Display Panel) S1 Composite Video Signal S2 Vertical Sync Signal S3 First Display control signal S4 Switching signal S5 Second display control signal

Claims (1)

[Claims] 1. A display control signal for a PDP, which switches between a first display control signal generated from an interlaced vertical synchronization signal and a second display control signal generated from a non-interlaced vertical synchronization signal. Inputting the first display control signal to a switching circuit and a first input terminal,
The output signal of the first output end corresponding to the first input end is input to the second input end, and the second output end and the third input end corresponding to the second input end and the third input end are input. A third flip-flop circuit having a third output terminal corresponding to each of the three input terminals and using a vertical synchronizing signal as a clock signal;
And an exclusive OR gate that receives the output signals of the second output terminal and the signal of the output terminal that is input to the third input terminal, and the switching circuit uses the output signal from the third output terminal. The first display control signal is selected when the vertical synchronizing signal is an interlace type signal, and the second display control signal is selected when the vertical synchronizing signal is a non-interlace type signal.
2. A PDP display control signal switching circuit, wherein the display control signal is selected.