JPH0777060B2 - Rotating head type digital tread recorder - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotary head type digital tape recorder for reproducing digital information signals such as digital audio signals and digital video signals.

[Outline of Invention]

According to the present invention, a PCM signal recorded on one track is encoded with an error correction code, and a recording signal obtained by interleaving a PCM signal for every two adjacent tracks is used as a pair of rotary heads. In a rotary head type digital tape recorder that alternately reproduces by, when reproducing the magnetic tape at a speed faster than that at the time of recording,
Of the first reproduction data and the second reproduction data reproduced by the pair of rotary heads, one reproduction data having a better error state is validated, and one reproduction data is insufficient. It interpolates the PCM signal and prevents abnormal sounds from being generated during playback.

[Conventional technology]

As an error correction code when recording / reproducing a digital audio signal (referred to as a PCM signal) by a pair of rotary heads, a PCM signal of an amount recorded / reproduced by one rotary head is arranged in a matrix, and this matrix arrangement is used. An error correction code C1 is encoded for each PCM signal aligned in the vertical direction of the matrix, and an error correction code C2 is encoded for each PCM signal aligned in the horizontal direction of the matrix arrangement. The PCM signal encoded with this error correction code and the check symbols of each of the error correction codes C1 and C2 are recorded / reproduced for each vertically aligned check symbol. The error correction of the reproduction signal is the decoding of the error correction code C1 (C1 decoding)
Then, the error correction code C2 is decoded (C2 decoding).

When an uncorrectable error occurs, even-numbered data of the PCM signal and its odd-numbered data may be recorded separately on two adjacent tracks in order to facilitate interpolation of error symbols. Has been done. A pair of rotary heads is called a magnetic head A and a magnetic head B.
In the case of a PCM signal, even-numbered data Le of the L (left) channel and odd-numbered data Ro of the R (right) channel are recorded on the magnetic tape by the magnetic head A, and odd-numbered data Lo and R channel of the L channel. The even-numbered data Re of is recorded on the magnetic tape by the magnetic head B.
The pair of tracks formed by each magnetic head in this way is called an interleaved pair. The data recorded on the tracks of the interleaved pair have the same frame address in the additional code, and the reproducing side can know the interleaved pair from the frame address. The reproduced data is subjected to the error correction processing as described above, and is converted into a PCM signal in which the reproduced data of each interleaved pair is combined.

Further, in order to increase the utilization rate of the magnetic tape, a recording method without a guard band between tracks is used. That is, the gap extending direction of the magnetic head A and the gap extending direction of the magnetic head B are made different from each other, and the crosstalk from the adjacent track is suppressed by the azimuth loss.

[Problems to be solved by the invention]

The rotary head type digital tape recorder is capable of a conversion reproducing operation in which the running speed of the magnetic tape is doubled or tripled the speed at the time of recording. During this conversion playback,
The reproduced tracks are intermittent as shown in FIGS. 7A and 7B. In FIG. 7, T _A indicates a track formed by the magnetic head A, and T _B indicates a track formed by the magnetic head B. For track T _A ,
Direction of the gap of the magnetic head A (+ azimuth) is shown in the track T _B, the direction of the gap of the magnetic head B (- azimuth) is shown. Also, two adjacent tracks T _A and T _B are an interleaved pair.

During double-speed reproduction in which the magnetic tape 3 is run at a speed twice as high as that at the time of recording, every other track is scanned as shown by the diagonal line in FIG. 7A. Therefore, there arises a problem that the continuous reproduction output signal of the magnetic head A and the continuous reproduction output signal of the magnetic head B are not reproduction output signals from the interleaved pair.

During triple-speed reproduction in which the magnetic tape 3 is run at a speed three times higher than that during recording, every two tracks scan as indicated by the diagonal lines in FIG. 7B. Therefore,
Similar to the double speed reproduction, the continuous reproduction output signal of the magnetic head A and the continuous reproduction output signal of the magnetic head B are not reproduction output signals from the interleaved pair.

When the track T _A is scanned by the magnetic head B or the track T _B is scanned by the magnetic head _A during the 2 × speed reproduction and the 3 × speed reproduction, almost no reproduction signal is obtained due to azimuth loss. When the reproduction signal of one track of the reproduction signals from the two tracks mistaken for the interleaved pair is suppressed by azimuth loss,
There is relatively no problem. However, even if the azimuths do not match due to tracking deviations, or if the azimuths match for the playback signals from the two tracks that were mistaken for the interleaved pair, PCM signals that are not related to each other are word-by-word. There is a problem that the reproduced PCM signals alternately included in are obtained, and an abnormal reproduced sound that is offensive to the ear occurs.

Therefore, an object of the present invention is to provide a rotary head type digital tape recorder capable of preventing the generation of an abnormal sound due to an incorrect interleave pair when tracks are scattered.

[Means for solving problems]

According to the present invention, an error correction code is coded on a PCM signal recorded on each of the tracks diagonally formed on a magnetic tape, and the PCM signal is interleaved on every two adjacent tracks. In a rotary head type digital tape recorder that alternately reproduces the recorded signal with a pair of magnetic heads provided in the rotary head at a predetermined angular interval, the magnetic tape is run at a speed faster than that during recording.
A discriminating means for discriminating between the error state of the first reproduced data and the error state of the second reproduced data reproduced by the pair of magnetic heads at the time of reproducing the track intermittently, and using the output signal of the discriminating means. Interpolating means for validating one of the first and second reproduced data having a good error state, invalidating the other reproduced data, and interpolating the other insufficient reproduced data using the one reproduced data. And a rotary head type digital tape recorder.

[Action]

When a track is intermittently reproduced, such as 2 × speed reproduction or 3 × speed reproduction, the first reproduction data and the second reproduction data, which are respectively reproduced by the pair of rotary heads, do not become the interleaved pair reproduction data. . Therefore, the error states of the first reproduction data and the second reproduction data are determined. Of the two reproduction data, one reproduction data having a better error state is used, and the other reproduction data having a bad error state is not used. As a result, the PCM signal corresponding to the other reproduction data is insufficient. This lack of P
The CM signal is interpolated using one reproduction data. Therefore, even if the interleave pair is mistaken, the reproduced sound is prevented from becoming abnormal.

〔Example〕

An embodiment in which the present invention is applied to a rotary head type digital tape recorder (abbreviated as R DAT) will be described with reference to the drawings. The explanation of this one embodiment is as follows.
The order is as follows:

a. Overall structure of digital tape recorder b. Data structure of digital tape recorder c. Error correction code of digital tape recorder d. Playback signal processing circuit a. Overall structure of digital tape recorder Figure 1 shows the rotary head type. The entire structure of a digital tape recorder, so-called R DAT, is shown. 1 is 200 with a diameter of 30 mm
It is a drum rotated at 0 rpm. A pair of magnetic heads 2A and 2B are attached to the drum 1 at an angular interval of 180 °. A magnetic tape 3 (shown by a chain line) is obliquely wound around the drum 1 at a winding angle of 90 °. The magnetic tape 3 is wound around the reel hubs 4A and 4B of the tape cassette, and is run at a speed of 8.15 (mm / sec) by the capstan 5 and the pinch roller 6.

By alternately sliding the magnetic heads 2A and 2B on the magnetic tape 3, the inclined tracks 7A and 7A as shown in FIG.
7B is formed on the magnetic tape 3. The tape width A of the magnetic tape 3 is 3.81 mm. The magnetic gap of one rotary head 2A is tilted by + α with respect to the direction orthogonal to the track, and the magnetic gap of the other rotary head 2B is tilted by −α with respect to the direction orthogonal to the track. (Α = 20
゜). The angles of the magnetic gaps of the magnetic heads 2A and 2B are called + azimuth and −azimuth, respectively.

The magnetic heads 2A and 2B are alternately selected by the head changeover switch 8, and a recording signal from the terminal r of the recording / reproducing switch 9 is supplied to the magnetic heads 2A and 2B via a rotary transformer (not shown), Reproduction signals of the heads 2A and 2B are taken out to a terminal p of the recording / reproducing switch 9 via a rotary transformer (not shown).

The analog audio signal from the input terminal 10 is supplied to the A / D converter 12 via the low-pass filter 11 and converted into a digital audio signal by (sampling frequency: 48 KHz, 16-bit linear quantization). The digital audio signal from the A / D converter 12 is supplied to the recording signal processing circuit 13. The recording signal processing circuit 13 performs error correction coding of the digital audio signal and conversion of recording data into a format as described later. In this case, the ID signal (PC that identifies the pre-emphasis on / off of the recorded signal, sampling frequency, number of quantization bits, etc.)
M-ID) is added. Further, a subcode such as a program number of a signal to be recorded, a time code, and an ID signal (subcode ID) for the subcode are formed by a subcode encoder (not shown), and a recording signal processing circuit is provided from a terminal 14. Supplied to 13.

From the recording signal processing circuit 13, serial recording data for each track is generated in synchronization with the rotation of the magnetic heads 2A and 2B. The recording data is supplied to the head changeover switch 8 through the recording amplifier 15 and the terminal r of the recording / reproducing switch 9. Recording data is alternately supplied to the magnetic heads 2A and 2B by the head changeover switch 8.

The signal reproduced by the magnetic heads 2A and 2B is supplied to the reproducing amplifier 16 through the head changeover switch 8 and the terminal p of the recording / reproducing switch 9. The output signal of the reproduction amplifier 16 is supplied to the PLL 17, and the PLL 17 extracts a clock synchronized with the reproduction signal. The reproduced signal is subjected to processing such as error correction and interpolation in the reproduced signal processing circuit 18,
The reproduced digital audio signal is supplied to the D / A converter 19. The reproduced audio signal from the D / A converter 19 is taken out to the output terminal 21 via the low pass filter 20. At the same time, in the reproduction signal processing circuit 18, the subcode and the subcode ID are separated and taken out to the output terminal 22. A subcode decoder is connected to the output terminal 22, and control data and the like are formed from the subcode.

A control signal for controlling the head changeover switch 8 and the recording / reproduction changeover switch 9 is formed by the timing control circuit 23. Also, the timing control circuit 23
Generates a clock signal and a timing signal required by each of the recording signal processing circuit 13 and the reproduction signal processing circuit 18.

b. Data structure of digital tape recorder The entire data recorded on one track is called one segment. FIG. 3A shows the structure of one segment of data recorded by one rotary head. When the unit amount of recording data is one block, one segment includes 196 blocks (7500 μsec) of data.
Margins (11 blocks) are provided at both ends of one segment corresponding to the end of the track. Subcode 1 and subcode 2 are recorded adjacent to each of the margins. The two subcodes are the same data and are double-recorded. The sub code is a program number and time code. A run-in section (2 blocks) and a post-amble section (1 block) of the PLL are arranged on both sides of the recording area of 8 blocks of the subcode.

In addition, the inter block
A gap is provided and sandwiched between three blocks of inter block gaps, and pilot signals for ATF are recorded over five blocks. Within the 130 block length area at the center of one segment, the recorded PCM signal is recorded in the 129 block length area excluding the 2-block PLL run-in section. This PCM signal is data corresponding to the audio signal during the time when the rotary head rotates 1/2 turn.

This PCM signal consists of a 2-channel stereo PCM signal consisting of L (left) channel and R (right) channel and parity data of error detection / correction code. Fig. 3A
When one segment shown in (1) is recorded / reproduced by the magnetic head 2A, data Le is recorded in the left half of the PCM signal recording area, and data Ro is recorded in the right half thereof. The data Le is composed of even-numbered data of the L channel and parity data regarding this data,
The data Ro consists of odd-numbered data of the R channel and parity data regarding this data. The odd number and the even number are the order counted from the beginning of the interleaved block.

One segment of data is recorded on the track formed by the other magnetic head in the same configuration as the above-mentioned one track. In the data section in the data of one segment of the other track, the data Re is recorded in the left half portion and the data Lo is recorded in the right half portion. The data Re consists of even-numbered data of the R channel and parity data regarding this data. Data Lo is
It consists of odd-numbered data of the L channel and parity data related to this data. In this manner, even-numbered data and odd-numbered data of each channel are separately recorded on two adjacent tracks, and L-channel and R-channel data is recorded on the same track by a dropout or the like. This is to prevent the continuous data of the same channel from being erroneous.

FIG. 3B shows the data structure of one block of the PCM signal. An 8-bit (1 symbol) block synchronization signal is added to the beginning of one block, and then an 8-bit PCM-ID is added. A block address is added after the PCM-ID. With respect to the two symbols (W1 and W2) of the PCM-ID and the block address, error correction coding processing of simple parity is performed, and 8-bit parity is added next to the block address. The block address is shown in Fig. 3D.
As shown in (4), it is composed of 7 bits excluding the most significant bit (MSB), and by setting this most significant bit to "0", it is indicated that it is a PCM block.

The 7-bit block address changes sequentially from (00) to (7F) (hexadecimal display). The PCM-ID recorded in each block of the lower 3 bits of the block address is (000) (010) (100) (110) is defined. An optional code of PCM-ID can be recorded in each block address in which the lower 3 bits of the block address are (001) (011) (101) (111). Each PCM-ID has a 2-bit ID1
~ Contains ID8 and 4-bit frame address. ID1 ~
Identification information is defined for each ID7. A pack is composed of 32 ID8s. For example, ID1 is a format ID, and whether it is for audio or other uses is identified by ID1, ID2 identifies on / off of pre-emphasis and characteristics of pre-emphasis, and ID3 identifies sampling frequency. . The above-mentioned ID1 to ID7 and the frame address are the same data in the segment of the interleave pair.

FIG. 3C shows the data structure of one block of subcode. It has the same data structure as the PCM block described above.
As shown in FIG. 3E, the symbol of the subcode block
The most significant bit of W2 is set to "1", indicating that it is a subcode block. The lower 4 bits of the symbol W2 are the block address, and the 8 bits of the symbol W1 and the 3 bits excluding the MSB and the block address in the symbol W2 are the subcode ID. Subcode block 2
For the symbols (W1 and W2), error correction coding processing of simple parity is performed, and 8-bit parity is added.

The sub-code ID is recorded in the even number of the block address (LSB of the block address (least significant bit) is "0") and in the odd number (LSB of the block address is "1"). And different data. The subcode ID includes a control ID designating a reproduction method, a time code, and the like. The sub-code data is subjected to the error correction code processing by the Reed-Solomon code, like the PCM data.

c. Error correction code of digital tape recorder Error detection / correction code is processed for each 128 blocks of data recorded in one segment. Fig. 4A
Shows the code structure of data recorded by one magnetic head 2A, and FIG. 4B shows the code structure of data recorded by the other magnetic head 2B. 16 quantization bits
The bit PCM signal is divided into upper 8 bits and lower 8 bits, and the error detection / correction code is encoded with 8 bits as one symbol.

Data of (128 × 32 = 4096 symbols) is recorded in one segment. As shown in FIG. 4A, (L0, L2, ...
-A two-dimensional array of even-numbered data Le of the L channel consisting of (L1438) symbols and odd-numbered data Ro of the R channel of (R1, R3, ... R1439) in the vertical and horizontal directions. The error detection code C1 and the error correction code C2 are encoded for each of them. Vertical 28
The C1 code using the (32,28,5) Reed-Solomon code is encoded on these symbols. The parity data P of this C1 code symbol is arranged at the last position of the two-dimensional array. Also, for 52 horizontal symbols (3
2,26,7) C2 code is encoded using Reed-Solomon code. This C2 code is applied to 26 symbols of every 2 symbols of 52 symbols, and the parity data Q consisting of 6 symbols is generated for one code sequence.
Parity data Q consisting of a total of 12 symbols of the C2 code is arranged at the center of the two-dimensional array. The other 52 PCM data symbols positioned in the horizontal direction are similarly coded by the C2 code, and the parity data Q thereof is arranged in the central portion.

In the code structure shown in FIG. 4B, the even-numbered PCM signal of the L channel in the code structure of FIG. 4A is replaced by the even-numbered PCM signal of the R channel (R0, R2, ... R1438). , R-channel odd-numbered PCM signals are replaced by L-channel odd-numbered PCM signals (L1, L3, ... L1439).

As shown in FIG. 3B, a synchronization signal, a PCM-ID, a block address, and a parity are added to 32 symbols arranged in the vertical direction in these code configurations to form one PCM block. It

d. Reproduction signal processing circuit The present invention is applied to the processing of reproduction data at the time of variable speed reproduction in the reproduction signal processing circuit 18 of the above-mentioned rotary head type digital tape recorder. FIG. 5 shows the configuration of the reproduction signal processing circuit 18, in which the reproduction signal is supplied to the input terminal indicated by 31.

The reproduced signal is supplied to the demodulation circuit 32, and 10 bits of 1 symbol are demodulated to 8 bits of 1 symbol. When recorded on the magnetic tape 3, the 8 bits of one symbol have undergone a digital modulation process which is converted into a preferred pattern of 10 bits in order to reduce low frequency components as much as possible. The reproduced data from the demodulation circuit 32 is supplied to the data bus 35 for each symbol via the data register 33 and the buffer 34.

The data bus 35 has a buffer RAM 36 and an error correction circuit 3
7 are combined. Playback data is fetched from the data bus 35 to the buffer RAM 36, and in the error correction circuit 37,
Data stored in the buffer RAM36 is processed by the Reed-Solomon code for error correction (C1 decoding and C2 decoding)
Receive. The error-corrected PCM signal is supplied to the interpolation circuit 38, and the uncorrectable error is interpolated and output terminal 39.
The playback PCM signal is extracted at. This playback PCM signal is D / A
It is supplied to the converter 19 (see FIG. 1). Further, the subcode is subjected to processing such as error correction by a subcode decoder (not shown) and is taken out to the output terminal of the subcode.

In addition, in connection with the demodulation circuit 32, a block address detection circuit
40 are provided. The reproduced block address is read by the block address detection circuit 40. The reproduction block address is supplied to the reproduction address generation circuit 41. The reproduction address generated by the reproduction address generation circuit 41 is supplied to the address bus 42. The reproduction address via the address bus 42 is used as the address signal of the buffer RAM 36. The reproduction block address is an address for writing reproduction data of one segment (32 symbols × 128 blocks) (see FIG. 4) sequentially from the first block to the 128th block for each block.

43 is an address generation circuit for ECC (error correction circuit). The address formed by the ECC address generation circuit 43 is supplied to the buffer RAM 36 via the address bus 42. The ECC address is an address for reading data from the buffer RAM 36 for each of C1 decoding and C2 decoding and a buffer RAM 36 for data after error correction and a pointer.
The address to write to.

At the time of C1 decoding, the C1 series data (PCM signal and parity data P) previously written by the reproduction address is read from the buffer RAM 36 for each block,
PC corrected after error correction in error correction circuit 37
The M signal and the C1 pointer are written to the same block address in the buffer RAM 36. The C1 pointer is written in the memory area where the parity P was written. This error correction process is performed for all C1 sequences. The ECC address generation circuit 43 generates a read address and a write address in the above C1 decoding. During C2 decoding, the C1 decoded PCM signal, C1 pointer and parity data Q are read out for each C2 sequence, and the error correction circuit 37 receives the C2 decoding process. The PCM signal error-corrected by C2 decoding and the C2 pointer are written in the buffer RAM 36. Also in this C2 decoding, the necessary read address and write address are formed by the ECC address generation circuit 43.

The PCM signal for which C1 decoding and C2 decoding have been completed is read from the buffer RAM 36 in the original order. In this case, the tracks are reproduced from the tracks T _A and T _B of the interleaved pair,
A two-channel stereo signal is formed by the error-corrected PCM signal. A D / A address generation circuit 44 is provided to read the error-corrected PCM signal from the buffer RAM 36. The address formed by the D / A address generation circuit 44 is transferred to the buffer RA via the address bus 42.
The PCM signal supplied to the M36 and read from the buffer RAM 36 is supplied to the interpolation circuit 38.

In addition, the PCM-ID or subcode I obtained from the demodulation circuit 32
D (W1), block address (W2) and parity are supplied to the error detection circuit 45, and in the error detection circuit 45,
Error detection is performed using simple parity. An error pulse indicating the presence or absence of an error is generated from this error detection circuit 45. This error pulse is "1" when there is an error and "0" when there is no error. The error pulse is
It is supplied to the counter 46. The counter 46 counts the error pulse that becomes “0” without any error for the reproduction data of one segment.

The count value of the counter 46 is supplied to the comparison circuit 47 and the register 48. The count value of the counter 46 for the reproduction data of one segment reproduced by the magnetic head 2A is registered in the register 48.
The counter circuit 46 compares the count value of the counter 46 and the count value of the register 48 with respect to the reproduction data of one segment reproduced by the magnetic head 2B.
The comparator circuit 47 compares these count values and generates a 1-bit comparison output signal corresponding to the magnitude of the count values. This comparison output signal is supplied to the interpolation control circuit 49. A reproduction mode determination signal is supplied from the terminal 50 to the interpolation control circuit 49. Further, the timing signals LRCK and A / Bi generated by the D / A address generation circuit 44 are
d is supplied to the interpolation control circuit 49.

The interpolation control circuit 49 generates an interpolation control signal for the interpolation circuit 38. The interpolation circuit 38 performs average value interpolation, previous value hold, and the like on the error-corrected PCM signal words specified by the pointer that cannot be error-corrected in the PCM signal. For the PCM signal for which the interpolation control signal from the interpolation control circuit 49 is "1", for example, the interpolation operation is forcibly performed. That is, between the reproduction data from the magnetic head 2A and the reproduction data from the magnetic head 2B,
The reproduction data in the bad error state is interpolated regardless of the pointer. Double speed playback, 3 depending on playback mode discrimination signal
An interpolation control signal for forcibly performing the interpolation operation is formed only during high speed reproduction such as double speed reproduction.

The operation of the above-described embodiment of the present invention will be described with reference to FIG. 6A and 6B are timing signals LRCK and A / Bid synchronized with the PCM signal supplied to the interpolation circuit 38. The timing signal LRCK is synchronized with the data of each channel of the stereo signal during normal reproduction, as shown in FIG. 6A. Also, the timing signal A / Bid is
This is a signal for distinguishing the reproduced data of A and 2B.

As shown in FIG. 4A, the magnetic head 2A records / reproduces even-numbered data Le of the L channel and odd-numbered data Ro of the R channel, and as shown in FIG. , R channel even-numbered data Re and L channel odd-numbered data Lo are recorded / reproduced. Therefore, the period in which the timing signal A / Bid is "0" shown in FIG. 6B is the period of the reproduced data of the magnetic head 2A, and the period in which the timing signal A / Bid is "1" is the reproduced data of the magnetic head 2B. Is the period.

Interpolation control circuit 49, when performing high-speed playback operation,
The interpolation control signal shown in FIG. 6C or 6D is generated according to the comparison output signal of the comparison circuit 47. Interpolation control shown in FIG. 6C when the comparison output signal of the comparison circuit 47 indicates that the data reproduced by the magnetic head 2A has a better error condition than the data reproduced by the magnetic head 2B. A signal is formed. That is, the interpolation control signal becomes "1" during the period of the PCM signal (R0, L1, R2, L3 ...) Reproduced by the magnetic head 2B, and this PCM signal is interpolated. On the other hand, when the reproduced data of the magnetic head 2B has a better error condition than the reproduced data of the magnetic head 2A, as shown in FIG. 6D, the PCM signal (R1 , L
2, R3, L4 ...) An interpolation control signal that becomes "1" is formed. With this interpolation control signal, the PCM signal reproduced by the magnetic head 2A is interpolated.

Unlike the above-described embodiment, the C1 pointer generated by C1 decoding may be used instead of using the result of the parity check in order to determine the error state of the reproduction data of each of the magnetic heads 2A and 2B. The present invention can also be applied to a case where an error can be detected by a CRC code for each block of recording data. Furthermore, the error state of the reproduction signal of the magnetic head may be determined from the envelope of the reproduction signal of the magnetic head.

〔The invention's effect〕

According to the present invention, when PCM signal interleaving is performed over two tracks, an abnormal reproduced sound is generated because the reproduced data of the interleaved pair which is incorrect when the tracks are reproduced intermittently. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the entire structure of a rotary head type digital tape recorder to which the present invention can be applied, FIG. 2 is a schematic diagram showing the tape format of the digital tape recorder, and FIG. 3 is a digital tape. FIG. 4 is a schematic diagram used for explaining the track format and block format of the recorder, FIG. 4 is a schematic diagram used for explaining the error correction code of the digital tape recorder, and FIG. 5 is a block diagram of the main part of one embodiment of the present invention. FIG. 6 is a time chart used for explaining the operation of one embodiment of the present invention.
FIG. 7 is a schematic diagram used for explaining the double speed reproduction operation and the triple speed reproduction operation. Description of main symbols in the drawings 1: Drum, 2A, 2B: Magnetic head, 3: Magnetic tape, 13: Recording signal processing circuit, 18: Reproduction signal processing circuit, 32: Demodulation circuit, 3
4: buffer, 35: data bus, 36: buffer RAM, 37: error correction circuit, 38: interpolation circuit, 40: block address detection circuit, 45: error detection circuit, 47: comparison circuit, 49: interpolation control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-57-32135 (JP, A) JP-A-59-117713 (JP, A) JP-A-60-226075 (JP, A) JP-A-59- 4345 (JP, A)

Claims (1)

[Claims] 1. A PCM signal recorded on each of the tracks diagonally formed on a magnetic tape is encoded with an error correction code, and the PCM signal is recorded on every two adjacent tracks. In a rotary head type digital tape recorder which alternately reproduces the interleaved recording signal by a pair of magnetic heads provided in the rotary head at a predetermined angular interval, the magnetic tape is recorded at a speed faster than that during recording. A discriminating means for discriminating between an error state of the first reproduction data and an error state of the second reproduction data which are respectively reproduced by the pair of magnetic heads at the time of reproduction in which the track is run and the track is intermittently reproduced. Using the output signal of the means, one of the first and second reproduction data having a good error state is validated and the other reproduction data is validated. Was invalid, missing the other rotary head type digital tape recorder characterized by comprising an interpolation means for reproducing data interpolated using one of the reproduced data above.