JPH0777223B2 - Method for forming protective film for stabilizing surface of compound semiconductor device - Google Patents

Method for forming protective film for stabilizing surface of compound semiconductor device

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Publication number
JPH0777223B2
JPH0777223B2 JP24533188A JP24533188A JPH0777223B2 JP H0777223 B2 JPH0777223 B2 JP H0777223B2 JP 24533188 A JP24533188 A JP 24533188A JP 24533188 A JP24533188 A JP 24533188A JP H0777223 B2 JPH0777223 B2 JP H0777223B2
Authority
JP
Japan
Prior art keywords
compound semiconductor
film
protective film
forming
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24533188A
Other languages
Japanese (ja)
Other versions
JPH0291938A (en
Inventor
一孝 上武
雅夫 島田
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NEC Corp
Original Assignee
NEC Corp
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Filing date
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Priority to JP24533188A priority Critical patent/JPH0777223B2/en
Publication of JPH0291938A publication Critical patent/JPH0291938A/en
Publication of JPH0777223B2 publication Critical patent/JPH0777223B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体素子の表面安定化保護膜形成方法
に関する。
The present invention relates to a method for forming a surface stabilizing protective film for a compound semiconductor device.

〔従来の技術〕[Conventional technology]

従来、インジウムリン(InP)やガリウム砒素(GaAs)
等のIII−V族化合物半導体板上に形成されるP/N接合や
ショットキ接合を用いる素子の表面安定化保護膜(以
下、パッシベーション膜という)を形成するにあたって
は、化合物半導体基板の表面を強制的に酸化させず、あ
るいは陽極酸化法(例えばH.Hasegawa et.al.,J.E.C.
S.123 713(1976))、酸素プラズマ酸化法(例えば
T.Sugano et.al.,J.E.C.S.121 113(1974))、光ア
シスト酸化法(例えばT.Suzuki et.al.,A.P.L,31 473
(1977))等により基板表面を強制的に酸化させてシリ
コン酸化膜やシリコン窒化膜等の所謂CVD保護膜(パッ
シベーション膜)を形成させていた。
Conventionally, indium phosphide (InP) and gallium arsenide (GaAs)
When forming a surface stabilizing protective film (hereinafter referred to as a passivation film) of an element using a P / N junction or a Schottky junction formed on a III-V group compound semiconductor plate, etc., the surface of the compound semiconductor substrate is forced. Not oxidize, or anodic oxidation method (eg H. Hasegawa et.al., JEC
S. 123 713 (1976)), oxygen plasma oxidation method (eg,
T.Sugano et.al., JECS 121 113 (1974)), photo-assisted oxidation method (eg T. Suzuki et.al., APL, 31 473).
(1977)), the surface of the substrate was forcibly oxidized to form a so-called CVD protective film (passivation film) such as a silicon oxide film or a silicon nitride film.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

上述した従来のパッシベーション膜形成方法では化合物
半導体表面における該化合物半導体構成元素からなる酸
化物組成と、その深さ方向分布の再現性、均一性が良く
なかったり、一旦制御性良く酸化層を形成しても、連続
してプラズマCVD(シリコン)窒化膜や光アシストCVD窒
化膜等のCVD保護膜を成長させていないため、イオン性
の不純物例えばナトリウムイオン(Na+)や銅イオン(C
u+)等の不純物元素を取込んだり、その後、継続して行
う該化合物半導体基板の洗浄工程やCVD成膜時に該酸化
物層が削られたり、組成変化を起こしたりするため、再
現性や均一性に乏しいという欠点があった。
In the conventional passivation film formation method described above, the reproducibility and uniformity of the oxide composition of the compound semiconductor constituent elements on the surface of the compound semiconductor and its depth direction distribution are not good, or the oxide layer is once formed with good controllability. However, since a CVD protective film such as a plasma CVD (silicon) nitride film or a photo-assisted CVD nitride film is not continuously grown, ionic impurities such as sodium ion (Na + ) and copper ion (C
u + ), etc., is taken in, or the oxide layer is scraped or a composition change occurs during the subsequent cleaning step of the compound semiconductor substrate or CVD film formation, which causes reproducibility and It has the drawback of poor uniformity.

本発明の目的は上記課題を解消した合号物半導体素子の
表面安定化保護膜形成方法を提供することにある。
An object of the present invention is to provide a method for forming a surface stabilizing protective film for a compound semiconductor element, which solves the above problems.

〔発明の従来技術に対する相違点〕[Differences from the Prior Art of the Invention]

上述した従来の表面安定化保護膜形成方法に対し、本発
明はパッシベーション膜の形成前に同一炉内で水蒸気酸
化させることにより素子特性の安定化を図るという相違
点を有する。
The present invention is different from the above-described conventional method for forming a surface stabilizing protective film in that element characteristics are stabilized by steam oxidation in the same furnace before forming a passivation film.

〔課題を解決するための手段〕[Means for Solving the Problems]

前記目的を達成するため、本発明はインジウムリン(In
P)やガリウム砒素(GaAs)等のIII−V族化合物半導体
板上に形成されるP/N接合やショットキ接合を用いる素
子の表面安定化保護膜を形成する化合物半導体素子の表
面安定化保護膜形成方法において、所定水蒸気濃度に保
った雰囲気にて前記化合物半導体基板の素子表面を水蒸
気酸化させ、同一炉内で連続して、プラズマCVD窒化膜
やシリコン酸化膜乃至光アシストCVD窒化膜やシリコン
酸化膜等の表面安定化保護膜を形成するものである。
In order to achieve the above object, the present invention provides indium phosphide (In
P) or gallium arsenide (GaAs), etc. Surface stabilizing protective film of compound semiconductor element for forming surface stabilizing protective film of element using P / N junction or Schottky junction formed on III-V compound semiconductor plate In the forming method, the element surface of the compound semiconductor substrate is steam-oxidized in an atmosphere kept at a predetermined steam concentration, and continuously plasma CVD nitride film or silicon oxide film or photo-assisted CVD nitride film or silicon oxide is formed in the same furnace. A surface stabilizing protective film such as a film is formed.

〔実施例〕〔Example〕

以下、本発明について図面を参照して説明する。 Hereinafter, the present invention will be described with reference to the drawings.

本発明は、インジウムリン(InP)やガリウム砒素(GaA
s)等のIII−V族化合物半導体板上に形成されるP/N接
合やショットキ接合を用いる素子のパッシベーション膜
を形成するにあたって、前記化合物半導体基板の素子表
面を水蒸気酸化させ、同一炉内で連続して、プラズマCV
D(シリコン)窒化膜やシリコン酸化膜乃至光アシストC
VD(シリコン)窒化膜やシリコン酸化膜等のパッシベー
ション膜を形成するものである。
The present invention is applied to indium phosphide (InP) and gallium arsenide (GaA
In forming a passivation film of an element using a P / N junction or a Schottky junction formed on a III-V group compound semiconductor plate such as s), the element surface of the compound semiconductor substrate is steam-oxidized, and the same in the same furnace. Continuously, plasma CV
D (silicon) nitride film, silicon oxide film or optical assist C
A passivation film such as a VD (silicon) nitride film or a silicon oxide film is formed.

水蒸気酸化させる際に、所定水蒸気濃度の雰囲気中で該
化合物半導体基板の素子表面を一定温度(50℃〜400
℃)の下に酸化することにより低温で組成制御された該
化合半導体構成元素からなる酸化物層を形成した後、同
一炉内にて、連続して低温成長温度でのプラズマCVD窒
化膜等の所謂CVD保護膜(パッシベーション膜)を形成
することにより、プラズマ状態に該基板表面がさらされ
ることに伴う所謂プラズマダメージを誘起させないこ
と、また連続成長によるイオン性不純物導入や酸化物変
成等を防止する。また水蒸気雰囲気中にて化合物半導体
基板の熱処理を行うに際して、所定の昇温速度で定温側
から高温側(室温から400℃を上限とする範囲内)に熱
処理することによりIII−V族化合物半導体の短所であ
るV族元素の蒸発を低温側熱処理に形成される該化合物
半導体構成元素からなる酸化物層で被覆させて保護しな
がら所定厚さの酸化物層を形成制御して形成する。
During steam oxidation, the element surface of the compound semiconductor substrate is kept at a constant temperature (50 ° C to 400 ° C) in an atmosphere of a predetermined steam concentration.
(C)) to form an oxide layer composed of the compound semiconductor constituent elements whose composition is controlled at a low temperature by oxidization under a low temperature. By forming a so-called CVD protective film (passivation film), so-called plasma damage due to exposure of the substrate surface to a plasma state is not induced, and introduction of ionic impurities and oxide transformation due to continuous growth are prevented. . Further, when heat-treating the compound semiconductor substrate in a water vapor atmosphere, the heat treatment is performed from a constant temperature side to a high temperature side (within a range from room temperature to 400 ° C. as an upper limit) at a predetermined heating rate to obtain a III-V group compound semiconductor. The formation of the oxide layer having a predetermined thickness is controlled while the evaporation of the group V element, which is a disadvantage, is covered and protected by the oxide layer formed of the compound semiconductor constituent element formed by the heat treatment on the low temperature side.

次に本発明の実施例について説明する。Next, examples of the present invention will be described.

(実施例1) 第1図(a)は本発明の実施例1であるインジウムリン
(InP)化合物半導体基板を用いるアベランシェ・フォ
トダイオード(A.P.D)の縦断面図、第1図(b)〜
(d)は本発明を製造工程順に示す縦断面図である。
(Embodiment 1) FIG. 1 (a) is a longitudinal sectional view of an avalanche photodiode (APD) using an indium phosphide (InP) compound semiconductor substrate, which is Embodiment 1 of the present invention, FIG. 1 (b)-
(D) is a longitudinal sectional view showing the present invention in the order of manufacturing steps.

第1図(b)において、高濃度N型インジウムリン(n+
InP)基板1上に低濃度n-インジウムガリウム砒素(n-I
nGaAs)層2及びn型インジウムリン(InP)層3からな
るエピタキシャル成長層を有する基板にCVD法によりシ
リコン酸化膜乃至五酸化燐を含むシリコン酸化膜(CVD
SiO2)膜9を成長させたのち、通常のフォトリソグラフ
ィーと弗酸水溶液により該CVD SiO2膜9の所望領域を開
窓してから、燐を含む亜鉛化合物を用いた封管拡散法に
より所定温度熱処理を施して高濃度P型拡散層(p+Zn)
4によるPN接合を形成する。次いで第1図(c)に示す
ように該CVD SiO2膜9を弗酸水溶液により除去した後、
本発明による表面安定化保護膜を以下の要領で形成す
る。
In FIG. 1 (b), high-concentration N-type indium phosphide (n +
Low concentration n - indium gallium arsenide (n - I) on the InP substrate 1.
A substrate having an epitaxial growth layer composed of an nGaAs) layer 2 and an n-type indium phosphide (InP) layer 3 is formed by a CVD method on a silicon oxide film or a silicon oxide film containing phosphorus pentoxide (CVD).
After the SiO 2 ) film 9 is grown, a desired region of the CVD SiO 2 film 9 is opened by ordinary photolithography and an aqueous solution of hydrofluoric acid, and then a predetermined process is performed by a sealed tube diffusion method using a zinc compound containing phosphorus. High-concentration P-type diffusion layer (p + Zn) after heat treatment
4 to form a PN junction. Then, as shown in FIG. 1 (c), after removing the CVD SiO 2 film 9 with a hydrofluoric acid aqueous solution,
The surface stabilizing protective film according to the present invention is formed in the following manner.

すなわち、図示しないプラズマCVD窒化膜成長装置に接
続された所定温度の純粋槽に窒素ガスを所定量バブルさ
せることにより一定濃度の水蒸気を含む窒素ガスを該成
長装置に流し込んでおき、第1図(c)に示すように、
該プラズマCVD窒化膜成長装置内の基板の温度を所定昇
温速度で室温から300℃まで昇温して所定水蒸気雰囲気
中にて該InP基板1の素子表面にIn2O3,In(PO3やIn
PO4等のInとPからなるインジウムリン酸化物槽(p+InP
層)5を所定厚さ、所定範囲の組成混合比にて形成さ
せ、その後、水蒸気雰囲気から完全に窒素雰囲気に置換
させた後、モノシランガス(SiH4),アンモニアガス
(NH3)からなる窒素混合ガス雰囲気にてプラズマ放電
させた所謂プラズマCVD窒化膜6を成長させる。
That is, a predetermined amount of nitrogen gas is bubbled in a pure tank at a predetermined temperature connected to a plasma CVD nitride film growth device (not shown), so that nitrogen gas containing a constant concentration of water vapor is flown into the growth device. As shown in c),
The temperature of the substrate in the plasma CVD nitride film growth apparatus is raised from room temperature to 300 ° C. at a predetermined heating rate, and In 2 O 3 , In (PO 3 ) 3 and In
Indium phosphide tank consisting of In and P such as PO 4 (p + InP
Layer 5 is formed with a predetermined thickness and a predetermined composition mixture ratio, and then the steam atmosphere is completely replaced with a nitrogen atmosphere, and then a nitrogen mixture of monosilane gas (SiH 4 ) and ammonia gas (NH 3 ) is added. A so-called plasma CVD nitride film 6 which is plasma-discharged in a gas atmosphere is grown.

然る後、第1図(d)に示すように亜鉛拡散を施したp+
InP層5及びプラズマCVD窒化膜6の一部を通常のフォト
リソグラフィーと弗酸水溶乃至熱リン酸等により開窓
し、金亜鉛(AuZu)等のP型InP層に対するオーミック
電極を介してチタン,白金,金(Ti/pt/Au)のアノード
電極7を形成する。次いで第1図(a)に示すように、
n+InP側に金,ゲルマニウム合金とニッケルからなるN
型溶オーミック電極を介してチタン,金等のカソード電
極8を形成してアバランシェ・フォトダイオードを完成
する。
Then, as shown in Fig. 1 (d), p +
A part of the InP layer 5 and the plasma CVD nitride film 6 is opened by ordinary photolithography and hydrofluoric acid aqueous solution or hot phosphoric acid, and titanium is inserted through an ohmic electrode for the P-type InP layer such as gold zinc (AuZu). An anode electrode 7 of platinum and gold (Ti / pt / Au) is formed. Then, as shown in FIG. 1 (a),
N consisting of gold, germanium alloy and nickel on the n + InP side
The cathode electrode 8 made of titanium, gold or the like is formed through the mold solution ohmic electrode to complete the avalanche photodiode.

上述したように実施例1によれば、水蒸気雰囲気中でイ
ンジウムリン(InP)化合物半導体基板の素子表面を酸
化して該化合物半導体基板の構成元素からなるインジウ
ムリンの酸化層を形成させたのち、同一炉内で連続して
CVD窒化膜6を形成することにより、特にAPDの逆方向耐
圧の安定化、リーク電流の減少化が達成される。
As described above, according to Example 1, after the element surface of the indium phosphide (InP) compound semiconductor substrate is oxidized in a water vapor atmosphere to form an oxide layer of indium phosphide composed of the constituent elements of the compound semiconductor substrate, Consecutively in the same furnace
By forming the CVD nitride film 6, it is possible to stabilize the reverse breakdown voltage of the APD and reduce the leak current.

(実施例2) 第2図(a)は本発明の第2の実施例であるガリウム砒
素(GaAs)化合物半導体基板を用いるショットキ接合型
電界トランジスタを基本能動素子とし、他に抵抗等の受
動素子からなる集積回路素子を示す縦断面図、第2図
(b)〜(e)は第2図の集積回路素子の形成方法を示
す縦断面図である。
(Embodiment 2) FIG. 2A shows a Schottky junction type electric field transistor using a gallium arsenide (GaAs) compound semiconductor substrate which is a second embodiment of the present invention as a basic active element, and other passive elements such as resistors. 2 is a vertical cross-sectional view showing an integrated circuit element made of, and FIGS. 2B to 2E are vertical cross-sectional views showing a method for forming the integrated circuit element of FIG.

先ず第2図(b)に示すように、半絶縁性ガリウム砒素
(GaAs)基板21上にシリコン等のN型不純物イオンを所
定領域にイオン注入させて、活性化アニールを施しn型
ガリウム砒素(GaAs)領域22を形成したのち、通常のCV
D法によるシリコン酸化膜23を形成する。続いてチタ
ン,白金,金からなるショットキゲート電極24を該シリ
コン酸化膜23の所定領域を開窓して形成する。次いで第
2図(c)に示すように該シリコン酸化膜23をスペーサ
層とするレジストリフトオフ技術により金,ゲルマニウ
ム合金(AuGe)とニッケル(Ni)からなるN型GaAsへの
ソースオーミック電極25、ドレインオーミック電極26、
抵抗層オーミック電極27を形成する。特に、ここで重要
なことは該スペーサ層としてのシリコン酸化膜を形成弗
酸水溶液にて除去したのち、熱リン酸や塩酸等にて該Ga
As露出面上の自然酸化層等の酸化物を十分除去しておく
こと及びn型能動領域以外の半絶縁性GaAs基板21の表面
等の所謂フィールド領域のシリコン酸化膜23は全面的に
除去する必要がある。次いで第2図(d)に示すように
本発明の方法により化合物半導体板の構成元素であるGa
とAsからなるガリウム砒素酸化物層28を水蒸気雰囲気に
て形成したのち、シリコン酸化膜(CVD SiO2膜)29を形
成する。然る後に通常のショットキ接合型GaAs電界効果
トランジスタ製造方法に従い、CVD SiO2膜29の所定位置
を開窓してソース電極30、ドレイン電極31及び抵抗電極
32及びゲート引出し電極をチタン,白金,均等のメタル
で接続して第2図(a)に示すショットキ接合型GaAs電
界効果集積回路素子を完成する。
First, as shown in FIG. 2 (b), N-type impurity ions such as silicon are ion-implanted in a predetermined region on a semi-insulating gallium arsenide (GaAs) substrate 21, and activation annealing is performed to perform n-type gallium arsenide ( After forming the (GaAs) region 22, a normal CV
A silicon oxide film 23 is formed by the D method. Subsequently, a Schottky gate electrode 24 made of titanium, platinum and gold is formed by opening a predetermined region of the silicon oxide film 23. Then, as shown in FIG. 2C, a source ohmic electrode 25 and a drain for N-type GaAs made of gold, germanium alloy (AuGe) and nickel (Ni) are formed by a resist lift-off technique using the silicon oxide film 23 as a spacer layer. Ohmic electrode 26,
A resistance layer ohmic electrode 27 is formed. In particular, what is important here is that the silicon oxide film as the spacer layer is removed with a hydrofluoric acid aqueous solution, and then the Ga gas is removed with hot phosphoric acid or hydrochloric acid.
Sufficient removal of oxides such as a natural oxide layer on the exposed surface and removal of the silicon oxide film 23 in the so-called field region such as the surface of the semi-insulating GaAs substrate 21 other than the n-type active region are entirely removed. There is a need. Then, as shown in FIG. 2 (d), Ga, which is a constituent element of the compound semiconductor plate, is formed by the method of the present invention.
After a gallium arsenide oxide layer 28 made of As and As is formed in a water vapor atmosphere, a silicon oxide film (CVD SiO 2 film) 29 is formed. Then, in accordance with the usual Schottky junction type GaAs field effect transistor manufacturing method, a predetermined position of the CVD SiO 2 film 29 is opened to form a source electrode 30, a drain electrode 31 and a resistance electrode.
The Schottky junction type GaAs field effect integrated circuit device shown in FIG. 2 (a) is completed by connecting the 32 and the gate extraction electrode with titanium, platinum and even metal.

本実施例によれば、半絶縁性GaAs基板21の表面のみを選
択的に組成比制御して水蒸気酸化させることにより、シ
ョットキ接合型GaAs型電界効果トランジスタの集積回路
製造で最も問題となるサイドゲート効果が大幅に改善さ
れ、しかも該強制酸化に伴うトランジスタへの影響を全
く無視して行える利点を有する。
According to the present embodiment, by selectively controlling the composition ratio of only the surface of the semi-insulating GaAs substrate 21 to oxidize it with water vapor, the side gate which is the most problematic in the manufacture of the integrated circuit of the Schottky junction type GaAs field effect transistor. The effect is greatly improved, and the effect on the transistor due to the forced oxidation can be ignored.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は水蒸気雰囲気中で化合物半
導体基板の素子表面を酸化して該化合物半導体基板の構
成元素からなる酸化物層を形成したのち、同一炉内で連
続してプラズマCVDシリコン窒化膜やシリコン酸化膜乃
至CVDシリコン酸化膜を形成することにより、該半導体
基板の素子表面にプラズマダメージを誘起させないばか
りでなく、イオン性不純物等の不純物混入を防ぐととに
該化合物半導体基板の構成元素からなる酸化物層の低温
形成によるIII−V族化合物半導体特有のV族元素の蒸
発防止、CVDシリコン窒化膜及びシリコン酸化膜と化合
物半導体との界面特性を該酸化層を介して再現性、均一
良く制御できる効果を有する。
As described above, according to the present invention, the element surface of the compound semiconductor substrate is oxidized in a water vapor atmosphere to form an oxide layer composed of the constituent elements of the compound semiconductor substrate, and then plasma CVD silicon nitriding is continuously performed in the same furnace. By forming a film or a silicon oxide film or a CVD silicon oxide film, not only plasma damage is not induced on the element surface of the semiconductor substrate, but also the mixing of impurities such as ionic impurities is prevented and the structure of the compound semiconductor substrate is formed. Evaporation prevention of group V elements peculiar to III-V group compound semiconductors by low-temperature formation of oxide layers made of elements, reproducibility of interfacial characteristics between CVD silicon nitride film and silicon oxide film and compound semiconductors through the oxide layers, It has the effect that it can be uniformly and well controlled.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)は本発明の第1の実施例を示すInP化合物
半導体基板を用いるアバランシェ・フォトダイオード
(APD)の縦断面図、第1図(b)〜(d)は第1図
(a)に示すAPDの形成方法を工程順にしめす縦断面
図、第2図(a)は本発明の第2の実施例を示すGaAs化
合物半導体基板を用いるショットキ接合型電界効果トラ
ンジスタ集積回路素子の縦断面図、第2図(b)〜
(e)は第2図(a)の形成工程を示す縦断面図であ
る。 1……高濃度N型インジウムリン基板 2……低濃度n-インジウムガリウム砒素層 3……n型インジウムリン層 4……高濃度P型拡散層 5……インジウムリン酸化物層 6……プラズマCVD(シリコン)窒化膜 7……アノード電極、8……カソード電極 9,23,29……シリコン酸化膜 21……半絶縁性ガリウム砒素基板 22……n型ガリウム砒素領域 24……ショットキゲート電極 25……ソースオーミック電極 26……ドレインオーミック電極 27……抵抗層オーミック電極 28……ガリウム砒素酸化物層、30……ソース電極 31……ドレイン電極、32……抵抗電極
FIG. 1 (a) is a longitudinal sectional view of an avalanche photodiode (APD) using an InP compound semiconductor substrate showing a first embodiment of the present invention, and FIGS. 1 (b) to (d) are FIG. FIG. 2A is a vertical cross-sectional view showing the method for forming an APD shown in a) in the order of steps, and FIG. 2A is a vertical cross-sectional view of a Schottky junction field effect transistor integrated circuit device using a GaAs compound semiconductor substrate according to a second embodiment of the present invention. Plan, FIG. 2 (b)-
(E) is a longitudinal sectional view showing a forming step of FIG. 2 (a). 1 ... High-concentration N-type indium phosphorus substrate 2 ... Low-concentration n - indium gallium arsenide layer 3 ... n-type indium phosphorus layer 4 ... High-concentration P-type diffusion layer 5 ... Indium phosphorus oxide layer 6 ... Plasma CVD (silicon) nitride film 7 …… Anode electrode, 8 …… Cathode electrode 9,23,29 …… Silicon oxide film 21 …… Semi-insulating gallium arsenide substrate 22 …… N-type gallium arsenide region 24 …… Schottky gate electrode 25 …… Source ohmic electrode 26 …… Drain ohmic electrode 27 …… Resistive layer ohmic electrode 28 …… Gallium arsenide oxide layer, 30 …… Source electrode 31 …… Drain electrode, 32 …… Resistive electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/812 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 29/812

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】インジウムリン(InP)やガリウム砒素(G
aAs)等のIII−V族化合物半導体基板上に形成されるP/
N接合やショットキ接合を用いる素子の表面安定化保護
膜を形成する化合物半導体素子の表面安定化保護膜形成
方法において、所定水蒸気濃度に保った雰囲気にて前記
化合物半導体基板の素子表面を水蒸気酸化させ、同一炉
内で連続して、プラズマCVDシリコン窒化膜やシリコン
酸化膜乃至光アシストCVDシリコン窒化膜やシリコン酸
化膜等の表面安定化保護膜を形成することを特徴とする
化合物半導体素子の表面安定化保護膜形成方法。
1. Indium phosphide (InP) and gallium arsenide (G)
P / formed on a III-V compound semiconductor substrate such as aAs)
In the method of forming a surface stabilizing protective film of a compound semiconductor element for forming a surface stabilizing protective film of an element using N-junction or Schottky junction, steam oxidize the element surface of the compound semiconductor substrate in an atmosphere kept at a predetermined water vapor concentration. , Surface stabilization of a compound semiconductor device characterized by continuously forming a surface stabilizing protective film such as a plasma CVD silicon nitride film or a silicon oxide film or an optically assisted CVD silicon nitride film or a silicon oxide film in the same furnace. Protective film forming method.
JP24533188A 1988-09-29 1988-09-29 Method for forming protective film for stabilizing surface of compound semiconductor device Expired - Lifetime JPH0777223B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24533188A JPH0777223B2 (en) 1988-09-29 1988-09-29 Method for forming protective film for stabilizing surface of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24533188A JPH0777223B2 (en) 1988-09-29 1988-09-29 Method for forming protective film for stabilizing surface of compound semiconductor device

Publications (2)

Publication Number Publication Date
JPH0291938A JPH0291938A (en) 1990-03-30
JPH0777223B2 true JPH0777223B2 (en) 1995-08-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP24533188A Expired - Lifetime JPH0777223B2 (en) 1988-09-29 1988-09-29 Method for forming protective film for stabilizing surface of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPH0777223B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149843A (en) * 2005-11-25 2007-06-14 Sharp Corp Method for forming passivation film and method for manufacturing solar cell
JP5531610B2 (en) * 2009-12-24 2014-06-25 住友電気工業株式会社 Manufacturing method of semiconductor laser device

Also Published As

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JPH0291938A (en) 1990-03-30

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