JPH077730A - Synchronous control device and method - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a synchronization control device and method capable of ensuring timing synchronization between a plurality of types of data after decoding from composite data read from a recording medium. [Structure] A system decoder (host CPU), a video decoder, and an audio decoder each have a function as a master clock circuit and a function as a slave circuit, and these functions can be selectively switched and used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system, and more particularly to a synchronization control device and method for synchronizing image data and audio data.

[0002]

2. Description of the Related Art Recently, a plurality of types of digital data, for example, video data and audio data, are combined and recorded on a recording medium such as a CD-ROM, and these data are read and output as needed. Multimedia personal information equipment is planned and developed. This kind of equipment decodes the composite data read from the recording medium into data of each type, and performs a necessary decoding for each type of data.
G (Moving Picture coding Image Experts Group) has established various standards, which include compression / expansion methods for image signals and audio signals.

A basic decoding system based on this MPEG is shown in FIG. In the figure, the digital data recording medium 1
Is composed of, for example, a CD-ROM or the like, and records a plurality of types of digital data such as image data and audio data in a composite form. The composite data recorded on the digital data recording medium 1 is read by a pickup (not shown) and sequentially sent to the system decoder (host CPU) 3.

The system decoder 3 extracts the time information by decoding the composite data and outputs it to the clock controller 5, and also outputs the audio data to the audio decoder 7 and the image data to the image decoder 9, respectively. The clock controller 5 supplies a system clock to the audio decoder 7 and the image decoder 9 based on the time information from the system decoder 3.

The audio decoder 7 and the image decoder 9 transmit and receive time information to and from the clock controller 5, respectively, to perform decoding of audio data and image data in synchronization with each other, and obtain the obtained data respectively as images. It is sent to the output device 8 and the audio output device 10.

In such a decoding system, a plurality of types of digital data, for example, audio data and image data are multiplexed based on time information from the data flow read from the digital data recording medium 1 by the system decoder 3. In order to serve as an input to the audio decoder 7 and the image decoder 9, the data streams of audio and video are distributed and decoded.

The syntax of a bit stream according to the MPEG standard is a sequence header and six layers (from top to bottom: sequence, GOP (Group).
ofPictures), pictures, slices, macroblocks (16 × 16 pixel blocks, which are units for calculating motion compensation vectors), and blocks (8 × 8)
It becomes the unit of calculation of DCT composed of elements)). A 32-bit byte-arranged start code is prepared. These bit patterns do not occur in the video bitstream except at the start. Start codes other than sequence error codes (which represent uncorrectable errors from storage media) are defined in the syntax. In front of the start code, an arbitrary number of 0s are added to keep the byte arrangement. The sequence header specifies the screen format and so on.
To enable playback from the middle, the sequence header can be added to the beginning of all GOPs.
The sequence header attached to OP can change only the quantization matrix. The contents after the sequence start code are the horizontal size (12 bits) of the image, the vertical size (12 bits), the pixel aspect ratio (4 bits), the picture rate (4 bits), the bit rate (18 bits), and the VBV (vide). buffering ver
ifier) buffer size (10 bits), limit parameter flag (1 bit), two quantization matrix flags (1 bit) and contents (64 × 8 bits).

GOPs are not completely independent. The first GOP in the sequence allows starting with an I-picture in original screen order, but at the beginning of a general GOP is M
-1 (M is a P-picture period, usually about 3 to 6) B-pictures. The some B-pictures can use predictions from the last I, P-picture of the previous GOP. For reproduction from the middle, in a GOP with a sequence header, it is necessary to discard the first M-1 B-pictures when reproducing from the middle. The GOP layer is provided with a closed GOP flag and a broken link (Broken Link) flag. The closed GOP flag is the GOP
Indicates that the previous GOP screen is not required. GO
The first M-1 B-pictures of P mean that only backward prediction is used. This is a flag set during encoding. GO a sequence that is not a closed GOP
When editing in P units, it is necessary to set a broken link flag for the GOP next to the joining part. The decoder must discard the first M-1 B-pictures of the GOP having the broken link flag, without displaying them. The group start code is followed by a time code (25 bits), a closed GOP (1 bit), a broken link flag (1 bit) and the like.

Pictures have four types that are functionally different. The D-picture is image data of only the DC component used for high speed feed and high speed reverse. The D-picture is a decoder essential requirement, but the D-picture is included in another sequence. The sequence is different from the normal image of I, P, B-pictures. After the picture start code, the temporal reference (10 bits), the picture code type of the picture type (3 bits), and the value of the input virtual buffer of the decoder are indicated by vbv (16b).
after its), the motion vector must be an integer unit,
Describe the required number of motion vector frame intervals for P and B types. Other than the sequence and GOP header, extension and user data may follow.

A slice is a 16-pixel wide band of arbitrary length and cannot extend over a picture. The first and last macroblocks are non-skip (Nonskippe
d), and at least one macroblock is non-skip. A quantization scale (quantizersc) is added after the slice start code including the vertical position of the slice.
ale) (5 bits), followed by extra information.

Macroblocks do not have a start code. After MBA comes the macroblock type. Depending on the type, the quantization scale may follow. Also, the required number of motion vectors is attached. In Coded types other than intra, a macroblock pattern (CBP) is attached.

In the block layer, the DCT coefficient is EOB.
Continues until. The block dropped due to CBP does not have the block layer itself. Generally, the sequence of image information is divided into several packets as shown in FIG.
Each packet is a GOP (Group of Pictu) consisting of a plurality of pictures (one still screen) and its lower layer data.
Res). The sequence information is the top layer that represents the coding hierarchy, and consists of a header and some GOPs. 1 GOP
Is a unit that can be randomly accessed as it is.
This GOP is a minimum coding unit that can be independently decoded within the range of a sequence, and is composed of one header and a plurality of pictures. One picture corresponds to one frame of a moving image or movie. FIG. 7 shows the interrelationship of three types of pictures that compose a GOP defined by the MPEG standard, that is, I, P, and B pictures, and each one picture is one of a moving image or a movie.
Corresponds to the frame. That is, I picture: This I picture is a random access picture that has the most data amount among the three types of pictures and is only subjected to basic data compression, and can be coded regardless of other pictures. Is. That is, it is an intra-frame (Intra frame) encoded screen, and all macroblocks are Intra encoded. The purpose is to easily maintain the independence of GOPs.

P picture: This P picture is coded for motion compensation of the previous I or P picture. That is, it is an inter-frame (Predictive) predictive coding screen, and is CCITT H.264. Similar to H.261, this is a screen type in which Intra coding and Inter coding can be selected for each macroblock.

B picture: This B picture is a picture with the highest data rate compression rate among the three types of pictures, and is coded for motion compensation of the preceding or following I or P picture. That is, bidirectional
This is a screen type which is a predictive coding screen and is a screen type peculiar to MPEG, and not only the past I and P pictures can be used for prediction but also the future I and P pictures can be used for prediction.

As shown by the arrows in FIG. 7, the above-mentioned dependency relationship between I, P and B pictures is such that only an I picture exists independently, and a P picture is a B picture in the preceding I or P picture. The picture depends on the preceding or following I or P picture.

In some applications, there is a demand to reproduce the image signal in the reverse direction. However, since there are pictures generated depending on the previous or next pictures as described above, a memory having a capacity capable of storing all the pictures forming one GOP is used, and once the GOP is forwarded. If the decoder configuration is such that the pictures in the memory are reproduced and stored in the memory and then the pictures in the memory are read in the reverse direction, the above requirements cannot be realized. Therefore, a large amount of display memory is required to store the decoded picture as compared with the case of reproducing the image in the forward direction. As a result, it was practically difficult to realize the reverse reproduction as described above.

Further, if the reverse reproduction is performed by using only the I picture which is an independent picture that does not depend on other pictures in the GOP, the problem of the capacity of the display memory can be avoided, but on the other hand, Since the number of pictures actually used for display is greatly reduced, it is not practical because only a moving image with rough motion and no smoothness and low display quality can be obtained.

Further, the MPEG algorithm does not specify the frequency to be freely selected and coded and the position in the GOP of the I picture that does not depend on other pictures, and can be freely set. There is.
Therefore, in an application in which the random access function is important, I pictures are arranged and used about twice a second.

As described above, the currently available MPEG image decoder does not support the forward / reverse bidirectional scanning function at all, and can only scan the I picture by using the external application software. there were.

However, in order to realize a high-speed forward / reverse scanning function, it is expected to use an external system for distributing I-pictures to the image decoder in the display order. However, in the conventional MPEG system, the forward / reverse rotation of the MPEG picture is dependent on the application software.
The reverse scanning function must be identified by the external system of the image decoder by decoding the bitstream to find the position of the I-picture for scanning. This imposes a great load on the external system decoder 3.

In addition, since the generally used semiconductor chip for MPEG image decoding does not store and hold the information regarding the position of the I picture in the bit stream, the recording of this information is performed by the upper system decoder 3
Must be held, and the burden on the system decoder 3 was heavy.

The digital decoder also receives coded bitstream data, decodes it, stores it in an external memory, and arranges the frames in order before displaying. In the case of MPEG, since there are I, P, and B type moving images, each moving image must be instantly stored in three buffers of the external memory. Various reproduction functions are realized by the digital decoder for the stored moving image. Such functions include, for example, normal play, high speed / low speed play, still image, and search. However, conventional MPEG standards or other digital video decoders do not have the function of inverting the decoded moving image.

In the case of JPEG, various moving image operations (including inversion of moving images) are performed on the decoded moving image, but a DSP or graphic chip is additionally required in addition to the video decoder. As described above, currently commercially available digital video decoders do not have a function of inverting a moving image (right-left or up-down) before displaying it. In order to realize this function by using a commercially available digital video decoder, a graphic chip and a frame memory are required in the video system that receives the decoded moving image data.

Further, in a decoder which decodes composite data read from a recording medium into data of each type and further performs necessary decoding for each type of data, timing synchronization is performed between a plurality of types of data decoded from the composite data. Need to take. As a general method for achieving this synchronization, data is read from the recording medium at a fixed ratio and various data are assigned to respective decoder blocks. In such a case, the fixed ratio when reading various data from the recording medium is determined in synchronization with the overall operation timing.

[0025]

In this case, when audio data and video data are decoded from the recording medium,
There is no synchronization between the respective data after the decoder output. For example, by repeatedly performing "stop" and "playback start", there is a problem that the output timings of audio and video are misaligned. Will occur.

That is, conventionally, the synchronization between the multiple data streams supplied to the various decoders of the system is performed by the system decoder 267 as shown in FIG.
Data is read at a constant rate from No. 3, separated, and each data stream (DS1 to DSn) is supplied to each decoder. In this case, the timing and synchronization of each decoder are determined by the rate of reading data from the recording medium. Therefore, when audio data and video data are decoded from a common recording medium, if the display of the video data and the audio output are not synchronized after decoding, there is a correlation with the actual audio output timing and video output timing. Disappears.

An object of the present invention is to provide a synchronization control device and method capable of ensuring timing synchronization between a plurality of types of decoded data from composite data read from a recording medium.

In this embodiment, each decoder such as a video decoder and an audio decoder is provided with a function as a master clock circuit and a function as a slave clock circuit, and these functions can be selectively switched and used. ing. As a result, the system decoder 2
Since 69 does not need to supply the master clock signal to various decoders, the load is reduced and it is possible to service other applications. Further, when each decoder has a data buffer, for example, it is possible to prevent data underflow or overflow. Also,
Each decoder can act as a master timekeeper that synchronizes with the rest of the other decoders, allowing flexibility in system design. Moreover, synchronization between multiple streams can be achieved by presentation time stamps in the common data stream. Therefore, it is possible to synchronize the reproduction of N streams by adjusting the reproduction of all the data streams to the master time base rather than adjusting the reproduction of one data stream to the reproduction of another data stream.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first decoder 273 and a second decoder 275 to which the synchronization control circuit of the present invention is applied. In FIG. 1, DSM (digitals)
A storage medium 263 is a recording medium for storing composite data of video data and audio data (digital data of ISO11172 standard). The system decoder 269 is realized by, for example, the CPU of the host system and a control program, reads composite data from the DSM 263, separates it into video data and audio data, and supplies them to the first decoder 273 and the second decoder 275, respectively. That is, the system decoder 269 receives information about video data and time (system clock re).
ference (SCR), presentation
time stamp (PTS), and deco
ing time stamp (DTS), video data is stored in a video buffer 277, and time information is stored in a system time clock counter (STCC) 27.
Output to 9. Further, the system decoder 269 separates the audio data and the time information (SCR, PTS, DTS), the audio data into the audio buffer 281, and the time information into the S.
Output to TCC283. The video data output from the video buffer 277 and the audio data output from the audio buffer 281 are decoded by the video decoder 285 and the audio decoder 287, and output to the output control circuits 289 and 291 respectively.
The output control circuit 289 performs video data output control and timing control based on the PTS from the STCC 279. Similarly, the output control circuit 291 controls the STC
Based on the PTS from C283, output control of audio data and timing control are performed.

In this embodiment, there are three modes.
i) If the system decoder becomes the time master, then i
i) if the first decoder becomes the time master, iii)
This is the case where the second decoder becomes the time master. When the system decoder becomes the time master, the first and second
Each decoder operates as a slave. The system decoder 269 transmits the system clock and time information (SCR, DTS, PT) to the STCCs 279 and 283, respectively.
S) is supplied. Each STCC 279, 283 corrects the system time clock using the supplied SCR.

When the first decoder 273 becomes the time master, the system decoder 269 and the second decoder 27 are used.
5 operates as slaves. System decoder 269
Reads the differential data generated by the STCC 279 in the first decoder 273 in response to the interrupt signal from the first decoder 273. The system decoder 269 corrects its own system time clock based on the read difference data and supplies the difference data to the STCC 283 in the second decoder 275 which is a slave. The system decoder 269 is the first decoder 273.
And STCC 27 provided in the second decoder 275
The system time clock is corrected on the basis of the difference data read from the first decoder 273 by having the same hardware configuration as that of No. 9, 283 or by software control by the system decoder 269.

When the second decoder 275 is the time master, the system decoder 269 and the first decoder 273.
Acts as a slave. In this case, the system decoder 269 reads the difference data from the STCC 283. The system decoder 269 corrects its own system time clock based on the read difference data, and supplies the read difference data to the first decoder 273 which is a slave.

The generation of difference data in STCC 279 and 283 will be described in detail below. FIG. 2 is a detailed block diagram showing the STCC 279 shown in FIG. 1 and its peripheral circuits. The second decoder STCC283
Has the same configuration.

In FIG. 2, the system clock from the clock controller 271 in the system decoder 269 is input to the frequency dividing circuit 293, where it is appropriately frequency-divided to I.
A 90 KHz clock signal of SO11172 standard is created and supplied to the STCC 279. STCC279 is
Difference register 29 in synchronization with the 90 KHz clock signal
The value of the difference data held in 5 is counted up or down. The count value from the STCC 279 is sent to the comparison circuit 297 and also used as a clock signal for synchronization control as a video buffer 277 and a video decoder 28.
5 and output control circuit 289.

The comparison circuit 297 also uses the SCR 299 as the time information TS from the system decoder 269.
The DTS 301 and PTS 303 are appropriately input. The comparison circuit 297 compares the time information and the count value of the STCC 279, and the difference data thereof is selected by the selector 305.
Output to. The selector 305 selects the difference data from the comparison circuit 297 in the time master mode and the difference data supplied from the time master in the slave mode and loads it into the difference register 295. The select signal to the selector 305 is supplied from the system decoder 269.

SCR299, DTS301, PTS30
3 is a predetermined time (less than 0.7 seconds in the MPEG1 standard)
It is input periodically every time. Therefore, the count value of the STCC 279 is also corrected every predetermined time. The video buffer 277 is controlled in timing based on SCR299, the video decoder 285 is controlled in accordance with DTS301, and the output control circuit 289 is controlled in accordance with PTS303.

As a result of these timing controls, even if a temporal "deviation" occurs between the video data and the audio data, this is corrected in real time and synchronized video data and audio data are output. be able to.

The STCC 279 operates in the master clock mode or the slave clock mode. ST
When CC 279 operates in the master clock mode, STCC 283 in the second decoder 275 and the host system operate in the slave mode. In this case, the first decoder 273 outputs an interrupt signal to the system decoder 269 to notify the system decoder 269 of the difference data set in the difference register 295. In response to this interrupt signal, the system decoder 269 reads the difference data in the difference register 295. The read difference data is the second slave
Load to STCC 283 difference register in decoder 275.

That is, the system time clock of the system decoder 269 and the ST in the second decoder 275.
The system time clock of CC 283 is corrected by the difference data output from the difference register 295 in the first decoder 273. The system decoder determines which decoder's STCC will be the time master. (For example, the user selects it by the setup menu program on the host system side).

3 and 4 are flowcharts showing the operation in the master mode and the slave mode. In this example, the case where the first decoder 273 is in the master mode will be described, but similar control is performed even when the second decoder 275 is in the master mode.

In step 311, system decoder 269 extracts the SCR 299 and data. Next, in step 313, each decoder determines whether it is the master mode or the slave mode. If the user is in master mode, the first S
Determine whether it is CR299. If it is not the first SCR 299, the process proceeds to step 321. If it is determined in step 315 that it is the first SCR 299, the value of SCR 299 is set in STCC 279 in step 317. Then, in step 319, decoding is started. In step 321, the comparator 297 compares whether the value of the STCC 279 is equal to the PTS 303, that is, the value of the difference register 295 is “0”. If the value of the difference register 295 is not “0”, the difference between the value of STCC 279 and the PTS 303 is set in the difference register 295 in step 323,
ST based on the value set in the difference register 295
Correct the value of CC279. Then, the data is displayed in step 325, and the difference data set in the difference register 295 in step 327 is output to the system decoder 269.

On the other hand, when it is judged in the slave mode in step 313, it is judged in step 329 whether it is the first SCR, and if it is the first SCR, in step 331, the value of SCR299 is set to STCC.
279 and the difference register 295 is set to "0". Then, in step 333, decoding is started. In step 335, it is determined whether the value of the difference register 295 is "0". If not "0", in step 337, the value of the difference register 295 is set to STC.
In addition to C279, the value of STCC279 is corrected, and the process returns to step 335. When the value of the difference register 295 is “0”, the comparison circuit 297 compares in step 339 whether the value of the STCC 279 matches the PTS 293. If they match, the data is displayed in step 341, and the process returns to step 335. If they do not match in step 339, step 343.
At, it is determined whether PTS 293 is larger than the value of STCC 279. If so, step 3
At 45, wait until the values of PTS 293 and STCC 279 match, and proceed to step 341. On the other hand,
When PTS293 is smaller than the value of STCC279, the display is skipped in step 347 and the process returns to step 335.

In the embodiment shown in FIG. 2, the difference register is used to add the difference data to the STCC 279. However, as shown in FIG. 5, the PLL (phase) is used.
STC using the locked loop circuit 351
It may be configured to control C279.

In the above embodiment, the synchronization control circuits included in the video decoder and the audio decoder both have the circuit configuration shown in FIG. 2. However, for example, the video decoder is the master decoder, and the synchronization control circuit is shown in FIG. A circuit configuration as shown in the figure may be used, and the audio decoder is used as a slave decoder, and the synchronization control circuit is configured to have only STCC and a difference register so as to supply the difference data from the master decoder to the difference register of the slave decoder. Good.

Further, in the embodiment shown in FIG. 2, the system decoder is configured to read the difference data set in the difference register of the time master and set it in the difference register of the slave in response to the interrupt signal. The difference data register may be configured to be polled, or a data bus connecting the time master and the slave may be provided and the difference data may be directly supplied from the time master to the slave.

[0046]

According to the synchronous control apparatus and method of the present invention, the video decoder and the audio decoder are provided with the functions of the master clock circuit and the slave clock circuit, and these functions are selectively switched for use. It is configured to be able to. As a result, the system decoder 269 (CPU 43 of the host system) does not need to supply the master clock signal to various decoders, which reduces the load and can serve other applications. Further, when each decoder has a data buffer, for example, it is possible to prevent data underflow or overflow. In addition, each decoder can play the role of a master time keeper that synchronizes with the rest of the decoders, thus providing flexibility in system design. Furthermore, synchronization between multiple streams can be achieved by presentation time stamping on the common data stream. Therefore, it is possible to synchronize the reproduction of N streams by adjusting the reproduction of all the data streams to the master time base rather than adjusting the reproduction of one data stream to the reproduction of another data stream.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration when a synchronization control device of the present invention is applied to an MPEG1 standard decoder system.

FIG. 2 is a detailed circuit diagram showing a system time clock counter (STCC) shown in FIG. 1 and its peripheral portion.

FIG. 3 is a part of a flowchart showing control when the synchronous control device shown in FIG. 2 operates in a master mode and a slave mode, respectively.

FIG. 4 is the rest of the flowchart showing the control when the synchronous control device shown in FIG. 2 operates in the master mode and the slave mode, respectively.

5 is a circuit diagram showing a modification of the synchronization control device shown in FIG.

FIG. 6 is a block diagram showing the configuration of a general decoding system based on the MPEG standard;

FIG. 7 is a diagram showing a dependency relationship of pictures in a GOP based on the MPEG standard;

FIG. 8 is a diagram showing an example of the structure of a picture in a data packet based on the MPEG standard;

FIG. 9 is a block diagram showing conventional synchronization control;

[Explanation of symbols]

1. ． ． Digital recording medium, 3. ． ． System decoder, 5. ． ． Clock control circuit, 7. ． ． Audio decoder, 9. ． ． Video decoder, 263. ． ． Digital data recording medium 267. ． ． System decoder, 268
-1 to 268-n. ． ． Decoder, 269. ． ． System decoder, 271. ． ． Clock controller, 2
73. ． ． First decoder, 275. ． ． Second decoder,
277. ． ． Video buffer 279, 283. ． ． System time clock counter, 285. ． ． Video decoder, 289. ． ． Output control circuit, 281. ． ． Audio buffer, 287. ． ． Audio decoder, 2
93. ． ． Frequency divider, 295. ． ． Difference register, 29
7. ． ． Comparator, 299. ． ． System clock reference (SCR), 301. ． ． Decoding Time Stamp (DTS), 303. ． ． Presentation time stamp (PTS), 305. ． ． Selector, 3
51. ． ． PLL

Claims (12)

[Claims] 1. A device for synchronizing the operation of various decoders of a system for real time display, wherein the system and each decoder count a system time clock based on a system clock supplied from the system. Time clock counter means; comparing means for comparing the system time clock signal output from the system time clock counter means with a system clock reference supplied from the system and outputting difference data thereof; difference from the comparing means Selector means for selectively outputting data and difference data supplied from the system or another decoder; means for holding the difference data output from the selector means; and difference data held in the holding means System black Synchronous control apparatus comprising: a means for providing the click time counter means. 2. Each of the decoders has means for generating an interrupt signal to the system, and the system is held by differential data holding means in the decoder which has generated the interrupt signal in response to the interrupt signal. 2. The synchronization control device according to claim 1, further comprising means for reading the difference data stored therein and supplying it to another decoder. 3. The system has means for setting which decoder is to be the time master, polls the holding means in the decoder set as the time master, reads the held difference data, etc. 2. The synchronization control device according to claim 1, further comprising means for supplying to the decoder of. 4. The system supplies a selection signal for selecting the difference data from the comparison means to selector means in the decoder set as a time master, and the other selectors from the system to the decoder. 4. The synchronization control device according to claim 3, further comprising means for supplying a selection signal for selecting the difference data of. 5. A device for synchronizing the operation of various decoders of a system for real-time display, wherein the system and each decoder count a system time clock based on a system clock supplied from the system. Time clock counter means; comparing means for comparing the system time clock signal output from the system time clock counter means with a system clock reference supplied from the system and outputting difference data thereof; Selector means for selectively outputting difference data and difference data supplied from the system or another decoder; means for holding the difference data output from the selector means; and difference data held in the holding means The cis Synchronization control unit, characterized in that it comprises a phase-locked loop means for feeding back to the beam clock time counter means. 6. Each of the decoders has means for generating an interrupt signal to the system, and the system is held by differential data holding means in the decoder which has generated the interrupt signal in response to the interrupt signal. 6. The synchronization control device according to claim 5, further comprising means for reading the difference data stored therein and supplying it to another decoder. 7. The system has means for setting which decoder is to be the time master, polls the holding means in the decoder set as the time master, reads the held differential data, etc. 6. The synchronous control device according to claim 5, further comprising means for supplying the decoder to the decoder. 8. The system supplies a selection signal for selecting the differential data from the comparison means to selector means in the decoder set as a time master, and to the other decoders from the system. 8. The synchronization control device according to claim 7, further comprising means for supplying a selection signal for selecting the difference data of. 9. A method for synchronizing the operation of various decoders of a system for real-time display, the operation of said system and each decoder comprising: a) a system time clock based on a system clock provided by said system. B) comparing the system time clock signal counted in step a) with a system clock reference signal supplied from the system and outputting difference data thereof; c) the difference data And selectively outputting difference data supplied from the system or another decoder; and d) adding the selected difference data to the count value of step a). And the synchronous control method. 10. The synchronization control method according to claim 9, wherein the system further comprises a step of reading differential data in a decoder which has generated an interrupt signal and supplying the differential data to another decoder. 11. The system further comprises the steps of setting which decoder is the time master and polling the decoder set as the time master to read the difference data and supplying it to another decoder. The synchronization control method according to claim 9, wherein 12. The step of selecting step c) selects the difference data obtained in the comparing step of step b) in the decoder set as the time master, and selects the difference data from the system in other decoders. 10. The synchronization control method according to claim 9, wherein the difference data of is selected.