JPH0778190A - Circuit design support device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the efficiency of circuit design, the circuit design information is divided while maintaining logical consistency, and the function to integrate the divided circuit design information is provided. A circuit design support device is provided. [Structure] A file name 71, layout design information 73, and related file information 75 are included in an original data file representing a circuit structure. Then, the name of the child data file representing the configuration of the block formed by dividing the circuit is stored in the related file information 75. The layout design information of the child data file has the same structure as the original data file. When the layout design work of each block is completed, the layout design information of the child data file is integrated into the original data file based on the connection information 83.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit design support device having a function of dividing or integrating circuit design information.

[0002]

2. Description of the Related Art Conventionally, CAD has been used as a device for supporting circuit design of printed circuit boards and semiconductor integrated circuits.
(Computer Aided Design) system is often used. In these CAD systems, in order to improve the sophistication and labor saving of the circuit design work, the graphic information in which the elements for constructing the circuit are expressed by graphics and the attributes of each element and the connection relation between the elements are expressed. It has a function to manage it in combination with the logical information.

[0003]

By the way, in recent years,
In order to improve the function of the circuit, further high density and large scale circuit is being developed. When designing a circuit having a complicated structure, the circuit may be divided into several blocks and the design work may be performed for each block.

However, in the conventional circuit design support apparatus, the designer often requires a great deal of effort to maintain the consistency of the logical data between the divided blocks.

Further, after designing the blocks individually in parallel, when verifying the entire circuit using a circuit rule simulator or the like, data of the entire circuit must be newly created based on the data of each block. did not become.

The present invention has been made in order to solve the problems in improving the efficiency of such circuit design, and divides the circuit design information while maintaining the logical consistency, Another object is to provide a circuit design support device having a function of integrating divided circuit design information.

[0007]

In order to achieve the above object, the invention according to claim 1 is characterized in that a first storage means for storing design information for representing a circuit configuration and a first storage means are provided. Designating means for designating a position to divide the circuit represented by the stored design information, and a plurality of designs for representing respective configurations of the plurality of circuits formed by dividing the circuit at the position designated by the designating means. Dividing means for generating information and information for expressing a mutual logical connection relationship of the plurality of circuits based on the information stored in the first storage means; the plurality of design information and the logic; And a second storage means for storing information for representing a specific connection relationship.

According to a second aspect of the present invention, an integrating means for integrating the plurality of design information based on the information for expressing the logical connection relationship and a design information integrated by the integrating means are provided. And a third storage means for storing.

According to a third aspect of the present invention, the design information is
It is possible to include reference information for referring to other design information, and further includes a reference unit for referring to the plurality of design information by the reference information.

[0010]

According to the configuration of the first aspect, the first storage means stores the design information for representing the configuration of the circuit. The position for dividing the circuit represented by the design information stored in the first storage means is designated by the designating means. A dividing unit divides a plurality of design information for expressing respective configurations of a plurality of circuits formed by dividing the circuit at the designated position and information for indicating a mutual logical connection relationship of the plurality of circuits. It is generated based on the information stored in the first storage means. The second storage unit stores the plurality of design information generated by the dividing unit and the information for representing the logical connection relationship.

According to the structure of claim 2, the integrating means integrates the plurality of design information based on the information for expressing the logical connection relation. The third storage unit stores the design information integrated by the integration unit.

According to the configuration of claim 3, the reference means refers to other design information by the reference information included in the design information.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a circuit layout design support device (hereinafter simply referred to as “device”) 10 according to this embodiment. The device 10 receives logic design data representing a function of a circuit from an external circuit logic design system 11, executes a CAD system, and designs a layout on a circuit mounting. The device 10 is
CPU (Central Processing Unit) 1 that controls the whole
2 and a RAM that functions as a memory of the CPU 12
A (Random Access Memory) 14, a ROM (Read Only Memory) 16 that stores a system program for performing start-up processing and basic input / output processing, and an external storage device 18 that stores various processing programs and data. Including. Further, the apparatus 10 includes a CRT (Cathode Ray Tube) 20 for displaying CAD data and the CRT 20.
Display buffer 2 for storing and holding data to be displayed on the screen
2 and keyboard 2 for inputting data and operation commands
4, a mouse 26 for instructing an operation command displayed on the screen of the CRT 20 or a menu, a plotter 32 for outputting the created circuit design drawing, and a printer 36 for printing out data. including.

In the external storage device 18, an OS (Operating System) 40 for managing the basic operation of the device 10,
A CAD basic system 42 including a CAD basic command program and a graphic processing function, a conversion processing program 43, a layout design processing program 44, and a division processing program 46 to which the CAD basic system 42 is applied.
And a processing program such as an integrated processing program 48 are stored. Further, the external storage device 18 stores the logical design data storage area 49 for storing the logical design data input from the circuit logic design system 11 and the layout design data created based on the logical design data. And a layout design data storage area 50 are provided.

The conversion processing program 43 converts the logical design data stored in the logical design data storage area 49 into the device 10.
Is a program for converting into layout design data for designing a circuit layout. The data output by the conversion processing program 43 is stored in the layout design data storage area 50. The layout design processing program 44 uses the layout design data storage area 5
It is a program for inputting the constituent elements of the circuit and the wiring between the constituent elements as graphic information with respect to the data stored in 0 and setting the attribute of each element. The division processing program 46 is a program for dividing the circuit represented by the data stored in the layout design data storage area 50 into a plurality of blocks. Further, the integration processing program 48 is the division processing program 4
It is a program for integrating the data of the blocks divided by 6. Layout design data storage area 5
The data file stored in 0 is stored in the CPU 12 by the verification simulator system 60 for verifying the consistency of the connection relation of the designed circuit and the validity of the circuit rule.
It is possible to perform a verification simulation by reading the data through the.

FIG. 2 is a block diagram showing a procedure and data flow of a circuit layout design process using the device 10. 3 to 6 are diagrams showing an example of data displayed on the screen of the CRT 20 (FIG. 1). The outline of the process of the apparatus 10 will be described with reference to FIGS. 2 to 6.

From the circuit logic design system 11 to the CPU 12
The logical design data input via the external storage device 1
8 is stored in the logical design data storage area 49. This logical design data is data representing the function of the circuit, and has a structure as shown in FIG. 3, for example. In addition, in FIG.
As an example, a circuit including three functional blocks A, B, and C is illustrated. The logical design data input to the device 10 is converted into layout design data by the conversion processing program 43 (FIG. 1). FIG. 4 shows an example of layout design data. Next, the layout design data generated by the conversion processing is divided into the division processing program 46 (FIG. 1).
Is divided into a plurality of layout blocks by. In the example, 3 for each of the functional blocks A, B, and C shown in FIG. 3 above.
It is shown that the layout design data A, B, and C are generated by dividing the layout block into one layout block. A screen display example of layout design data A, B, and C created by division is shown in FIG.
Shown in. The details of the processing of the division processing program 46 will be described later.

Next, each layout design data A, B, C
A layout design process is performed individually for each. The layout design processing is performed by the layout design processing program 44.
(FIG. 1). In this way, by dividing the entire circuit into, for example, functional blocks and performing design work individually, even if the degree of integration of the circuit is high or the scale is large, the work of the designer is divided. It becomes possible and can respond flexibly.

When the layout design processing is completed for each functional block, the layout design data A, B, C are integrated by the integration processing program 48 (FIG. 1). FIG. 6 shows a screen display example of the layout design data after integration.
Then, a verification process is performed by the verification simulator system 60 on the integrated layout design data to verify the consistency and validity of the circuit design. If a defect is found as a result of the verification, it returns to the layout design process again,
The layout design data is corrected for the defective block, and the verification process is performed again after the integration process. If it is determined by the verification process that the circuit design is proper, it is output as design completion data. The details of the processing of the integrated processing program 48 will be described later. Further, the circuit logic design system 11, the conversion processing program 43, the layout design program 44, the verification simulator system 60.
With respect to (1), since it does not include the features of this embodiment and has the same configuration as the conventional one, the description thereof will be omitted.

FIG. 7 is a schematic diagram showing a file structure of layout design data. FIG. 7A shows the structure of the original data file after the division processing, and FIG. 7B shows the structure of the data file generated by dividing the original data file (hereinafter referred to as “child data file”). Indicates. Further, FIG. 7C is a diagram showing the configuration of a data file (hereinafter referred to as “grandchild data file”) generated by dividing the child data file. As shown in FIG. 7 (a),
The layout design data file includes a file name 71, layout design information 73, and related file information 75. The file name 71 is for referring to the data file. The layout design information 73 is information indicating the configuration of the entire circuit, the types of included components, the placement positions of the components, and the connection relationship between the components. The layout design information 73 includes design specification information 81, connection information 83, component information 85, graphic information 87, and library information 89. The details of each piece of information included in the layout design information 73 will be described later.

The related file information 75 includes the name of the child data file. The child data file shown in FIG. 7B is a data file in which layout design information of each block formed by dividing a circuit is stored. The name of the child data file is stored in the original data file because it is necessary to refer to the child data file during processing of the original data file.

The structure of the child data file is similar to that of the original data file, and includes a file name 91, layout design information 93, and related file information 95. In the related file information 95 of the child data file, FIG.
As shown in (c), the name of the grandchild data file is stored.

As described above, in this embodiment, the layout design data files for the circuits and the blocks formed by dividing the circuits are hierarchically managed, and the original data files can be sequentially searched. This makes it possible to refer to the original data and the data of other blocks at any time even when the layout design work is being performed individually for each block.

Next, the layout design information 7 shown in FIG.
The details of No. 3 will be described. FIG. 8 shows the design specification information 81.
It is a schematic diagram which shows the structure of. In the design specification information 81, in order to represent the specifications of the entire circuit, a “board external size” 101 indicating a dimension and a net as a unit of logical connection information (described later)
“Maximum net number” 103 indicating the maximum number of “No.” and “Number of wires” 105 indicating the number of wires that must be connected,
“Number of wiring completed” 107 indicating the number of wirings that have been connected
“Number of board layers” 109 indicating the number of layers of the board, “Clearance value” 111 indicating the characteristics of the board, and “Number of wiring pairs / number of wiring pairs” for defining a combination of two layers.
And 113 are stored. This design specification information 81 is
The same contents are inherited in common from the original data file to the child data file and the grandchild data file.

FIG. 9A is a schematic diagram showing the structure of the connection information 83. The connection information 83 includes information indicating the connection relationship of the pins provided on the components included in the circuit. Each pin has a given condition, eg "potentially equivalent"
It is included in the group called the net by the conditions such as. In FIG. 9B, the part number “0/2” has five pins, and the name of the net to which each pin belongs (SIGNAL
NAME) is "S $ OPEN", "%%% 200"
02 "," %%% 20003 "," %%% 2000
3 "and" %%% 20003 ". This net manages the logical connection information in the circuit, and the logical connection information between the blocks formed by dividing the circuit. In the connection information 83, the “number of nets” 121 included in the circuit (or block) is stored at the beginning as information for expressing the configuration of this net, and subsequently, information for each net is stored. . The information for each net includes "net number / net name" 123 for identifying the net and "terminals (pins) included in the net.
Number ”125,“ wiring method ”127 for identifying normal wiring or one-stroke writing wiring,“ data type ”129 for identifying power supply or GND, and“ voltage value ”
131 and "inner layer number" for representing the wiring layer of the net 1
33 and “part number / pin number / pin attribute / subnet number” 135 for specifying the included pin. The subnet number is a number for representing a local connection relationship between pins included in the net.

FIG. 10 is a schematic diagram showing the structure of the component information 85. The component information 85 includes information on each component included in the circuit. The information regarding the parts includes a "mounting layer" 141 for identifying whether the parts are to be mounted on the front side or the back side of the board, "part coordinates" 143 indicating the placement position of the parts, and "part name" 145. , "Component library name" indicating the name of the library (described later) corresponding to the component 1
47, and a "part number" 149 for identifying the part,
"Silk information" 151 showing the name of the library that defines the occurrence value of silk and the basic shape of silk included in the part
There is "pin information" 153 indicating the coordinates of the pins of the component, the number of the net including the pin, the subnet number, the corresponding circuit point number, and the like.

FIG. 11 is a schematic diagram showing the structure of the graphic information 87. The graphic information 87 includes information about the external shape of the circuit and a graphic such as a wiring graphic for connecting pins. The information included is "graphic coordinates"
There are 154, a “layer” 155, a “net number / subnet number” 157 when the figure is a wiring, and an “attribute” 159 indicating what figure it is.

FIG. 12 is a schematic diagram showing the structure of the library information 89. The library information 89 includes a basic shape library 161, a part shape library 163, and a part logic library 165. Basic shape library 1
Reference numeral 61 is a library for individually defining graphic elements representing shapes such as lands, solders, drills, component outlines, and silk. Each graphic element defines a line segment, a circle, an arc, a rectangle, a polygon, a character string, etc. alone or in combination. The part shape library 163 is a library for defining the shape of a part by combining the graphic elements defined in the basic shape library 161, setting the outline of the part, the position of pins, the position of silk data, and the like. The component logic library 165 is a library for adding logic information as an attribute to each component. The logical information to be added includes the type of component (resistor, capacitor, surface mounting type, etc.), the height of the component, the number of gates (circuit elements), the input / output order of pins of each gate, and the like.

FIG. 13 is a flow chart showing details of the processing of the division processing program 46 shown in FIG.
When the division processing program 46 is activated, the external storage device 1
The layout design data is read from the layout design data storage area 50 of No. 8 and is output to the display buffer 22 by the CPU 12. Based on the layout design data stored in the display buffer 22, the layout design screen of the circuit shown in FIG. 4 is displayed on the CRT 22 (S11). On the displayed layout design screen, a cursor (not shown) is moved by the mouse 26 to specify the division position of the circuit (S13). When designating the division position, for example, as shown in the schematic diagram of FIG. 14, after inputting arbitrary polygons D1 to D6, the execution key is pressed from the keyboard 24 to determine the division position. It is checked whether the division position is proper (S14), and if it is not proper, an error is displayed (S15).

When the division position is determined (YE at S14)
S), creating divided data for each block with reference to the layout design data file. Design specification information 81 of the layout design information 73 included in the original data file
Is directly copied to the child data file (S16). Next, the component and its pin included in each block are detected based on the component coordinate 143 and the coordinate data of the pin information 153 (FIG. 10), and the information such as the net and subnet related to each component and pin is extracted from the original data file. It is extracted and moved to the child data file (S17). Further, the library information on each part is moved from the original data file to the child data file (S18). When the necessary data movement is completed, the division processing ends. In this way, a child data file corresponding to each block formed by dividing the circuit is created. The connection relationship between each block can be grasped from the net information and the subnet information.

FIG. 15 is a flow chart showing details of the processing of the integrated processing program 48 shown in FIG.
When the activation command of the integrated processing program 48 is input from the keyboard 24 (FIG. 1), the child data files of each block are read (S21), and the pins included in different blocks are identified based on the subnet information described above. The connection is associated (S22). After generating the logical connection information of each block, the net information is integrated (S
23), and subsequently, the component information, the graphic information, and the library information are integrated (S24). When the data integration is completed, the integration process ends.

As described above, the device 10 of this embodiment is
Divide the circuit layout design data into blocks,
Layout design work can be done individually for each block. Conventionally, when dividing layout design data,
The logical connection information could not be maintained, and the designer had to bear a great deal of effort to maintain the consistency of each block. Also, when integrating the individually designed blocks, it takes a lot of time and effort to associate the information of the boundary position between the blocks. When the device 10 of this embodiment is used, the design work is performed while maintaining the mutual logical connection information of the divided blocks. Therefore, the layout design of each block can be reliably and appropriately performed, and the data can be easily integrated after the design work is completed.

Correspondence between the structure of this embodiment and the structures described in the above claims will be described. The original data file of the layout design data shown in FIG. 7A corresponds to the "first storage means" recited in the claims. The keyboard 24, the mouse 26, and the cursor displayed on the screen shown in FIG. 1 correspond to "designating means" in the claims. The CPU 12 and the division processing program 46 shown in FIG. 1 correspond to "dividing means" in the claims. The child data file and grandchild data file shown in FIGS. 7B and 7C correspond to the "second storage means" in the claims. The CPU 12 and the integrated processing program 48 shown in FIG. 1 correspond to the "integrated means" in the claims. The data file integrated by the integration processing program 48 corresponds to the "third storage means" in the claims. The file name of the layout design data corresponds to "reference information" in the claims. The CPU 12 shown in FIG. 1 corresponds to "reference means" in the claims.

In the present embodiment, the circuit logic design system 11 and the verification simulator system 60 are provided outside the circuit layout design support apparatus 10 as shown in FIG. Either one or both of the above and the verification simulator system may be stored in the external storage device 18, and the circuit logic design processing and / or the verification simulation may be executed in the circuit layout design support device 10. .

[0035]

As described above, according to the first aspect of the present invention, the design information for representing the circuit configuration is divided into a plurality of design information by the dividing means, and each configuration of the circuit that can be divided is divided. Since a plurality of design information for expressing and the information for indicating the mutual logical connection relationship of each circuit are generated, each circuit is individually maintained while maintaining the logical connection relationship of the circuits which can be designated for division. Can be designed.

Further, according to the invention described in claim 2, the design information for representing a plurality of circuits is integrated by the integration means on the basis of the information for representing the logical connection relationship, so that the design information is individually designed. The design information of a plurality of circuits can be easily integrated.

According to the third aspect of the present invention, the design information includes reference information for referring to other related design information, and the design information associated with the reference means using this reference information. Is referred to, it is possible to easily refer to related design information.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a circuit layout design support device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a data flow and a processing procedure in the circuit layout design support device.

FIG. 3 is a diagram showing an example of circuit logic design data input to the circuit layout design support device.

FIG. 4 is a diagram showing an example of layout design data in the circuit layout design support device.

FIG. 5 is a diagram showing an example of layout design data subjected to division processing in the circuit layout design support device.

FIG. 6 is a diagram showing an example of layout design data integrated by the circuit layout design support apparatus.

FIG. 7 is a schematic diagram showing a configuration of a layout design data file.

FIG. 8 is a schematic diagram showing a configuration of design specification information included in the layout design data file.

FIG. 9 is a schematic diagram showing a configuration of connection information included in the layout design data file.

FIG. 10 is a schematic diagram showing a configuration of part information included in the layout design data file.

FIG. 11 is a schematic diagram showing a configuration of graphic information included in the layout design data file.

FIG. 12 is a schematic diagram showing a configuration of library information included in the layout design data file.

FIG. 13 is a flowchart showing a processing procedure of a division processing program.

FIG. 14 is a schematic diagram showing how a division position of a circuit is designated in a division processing program.

FIG. 15 is a flowchart showing a processing procedure of an integrated processing program.

[Explanation of symbols]

 10 circuit layout design support device 12 CPU 14 RAM 16 ROM 18 external storage device 24 keyboard 26 mouse 42 CAD basic system 44 layout design processing program 46 division processing program 48 integrated processing program 50 layout design data storage area 73 layout design information 75 related files Information 81 Design specification information 83 Connection information 85 Parts information 87 Graphic information 89 Library information

Claims (3)

[Claims] 1. A first storage unit for storing design information for representing a circuit configuration, and a designating unit for designating a position at which the circuit represented by the design information stored by the first storage unit is divided. A plurality of pieces of design information for representing respective configurations of a plurality of circuits formed by dividing the circuit at a position designated by the designating means, and a mutual logical connection relation of the plurality of circuits. Dividing means for generating information and information based on the information stored in the first storing means, and second storing means for storing the plurality of design information and information for expressing the logical connection relationship. A circuit design support device including. 2. A third storing means for storing the design information integrated by the integrating means, the integrating means for integrating the plurality of design information based on the information for expressing the logical connection relationship. The circuit design support apparatus according to claim 1, further comprising: 3. The design information can include reference information for referring to other design information, and further includes a reference unit for referring to the plurality of design information by the reference information. Alternatively, the circuit design support device according to any one of 2 and 3.