JPH0778480A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a decoding circuit in which a delay time of a delay circuit is variable in order to ensure stable operation at the time of writing while using a self-reset circuit suitable for high-speed operation as the decoding circuit. [Structure] The input of a delay circuit 950 that generates reset signals 31, 32 in phase with the output signal 20 and delayed by a predetermined time in the self-reset circuit is used as an output signal 20 and a pulse width control signal 40, and the pulse width control signal 40 is high. The pulse width of the output signal 20 is changed by changing the level time. Also the output signal
A latch circuit 201 that holds the potential of 20 is added. [Effect] The pulse width of the output signal 20 can be made larger than that of the input signals 10 and 11. By adding the latch circuit 201 that holds the potential of the output signal 20, it is possible to prevent the output potential 20 from being lowered by the elements 400, 401, and 200 that directly apply the potential to the output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a high speed CMOS memory circuit.

[0002]

2. Description of the Related Art CMOS circuits are widely used in the field of semiconductor memory devices, and high speed and high integration have been achieved by miniaturization of processing technology. As a problem with miniaturization, information destruction rate of memory LSI due to alpha ray incidence (Soft
Error Rate (abbreviated as SER below) is known to increase SR
In AM, measures are taken to increase the SER, such as adding capacitance to the memory cell and increasing the time constant of the feedback circuit of the flip-flop of the memory cell.
At the same time as miniaturization, higher speeds have been promoted by devising circuits. As a speed-up by such a circuit device, it has been proposed to shorten a memory access time and realize a pipeline operation using a synchronous circuit. For example, as a synchronous high-speed CMOS memory circuit, the 1990 symposium
On buoy ls eye circles digest
Of Technical Papers Page 49-50 (1990 Sym
posium on VLSI Circuits, Digest of Technical Paper
s, pp49-50) circuit or I / E E-Journal of Solid State Circuits Volume 26 Number 11 1991 Page 1577-1585 (IEEE Jounal
of Solid-State Circuits, Vol.26, No.11, November 19
91, pp1577-1585) is known. In these conventional circuits, by pulsing the circuit, normal CMOS
The input capacitance was halved compared to the circuit, and the speed of the circuit was increased. In addition, a pulse for reset pulse or post-charge of this pulse operation decoding circuit,
By detecting and generating a change in the output signal, a relatively low power and high-speed pipeline operation has been realized. on the other hand,
As a configuration of a sense circuit for a high-speed pipeline memory, the circuit disclosed in Japanese Patent Laid-Open No. 2-3177 is known. Japanese Patent Laid-Open No. 2-3177
In the circuit of, the memory circuit that stores the output of the sense amplifier is
By providing two, it was possible to stably read the data even when the access time fluctuates when reading the data in a cycle time shorter than the access time.

[0003]

Conventional circuits (IEEE Jounal
of Solid-State Circuits, Vol.26, No.11, November 19
91, pp1577-1585) and an effective channel length of 0.5 μm CMOS
A synchronous memory with an access time of about 4 ns and a cycle time of 2 ns (reading and writing data) was realized in the device. However, if the processing technology is miniaturized for higher speed and higher integration, the capacity of the memory cell is increased to suppress the increase of SER, or the feedback time constant of the flip-flop of the memory cell is increased. Measures are needed. These measures for suppressing the increase in SER are accompanied by an increase in the write time to the memory cell. That is, in a memory LSI using fine memory cells,
When trying to secure reliability against alpha ray incidence,
It becomes difficult to equalize the data read access time and the data write time. Therefore, for stable operation, it is necessary to change the pulse width of the word line between reading and writing to make the writing pulse width larger than that during reading. However, in the conventional memory using the self-reset circuit and the post-charge circuit in the decoding circuit, the pulse width of the signal is determined by the delay time of the delay circuit, so it is not possible to change the pulse width of the signal during writing and during reading. Can not.
In other words, in order to secure the reliability against alpha ray incidence and to operate stably, the cycle time at the time of reading must be increased in accordance with the cycle time of writing, and if the cycle time is set to be small in accordance with the reading. However, the writing operation becomes unstable, or the reliability with respect to the alpha ray incidence cannot be sufficiently secured. A first object of the present invention is to use a self-reset circuit and a post-charge circuit capable of high-speed operation in a decoding circuit, and to ensure sufficient reliability against alpha ray incidence, read cycle time and write cycle time. It is to provide a memory circuit capable of independently setting. In addition,
In 2-3177, a BiCMOS circuit constitutes a memory circuit that stores a sense amplifier and an output of the sense amplifier, and a case where a CMOS circuit is applied is not described. BiCMOS
In a memory, a high-speed and high-speed bipolar differential amplifier can be used to configure a high-speed sense amplifier and the above memory circuit, but in a CMOS memory, a low-gain MOS amplifier must realize a high-speed and stable operation. . A second object of the present invention is to provide a sense amplifier suitable for a pipeline memory composed of a CMOS circuit and a memory circuit for storing the output of the sense amplifier.

[0004]

In order to achieve the above first object, according to an embodiment of the present invention, a delay circuit (950) is provided in a self-reset circuit (post-charge circuit).
A signal (40) for controlling the delay time of the delay circuit is added to, and the pulse width of the output signal (20) is made variable by this signal (40).
(See Figures 1 and 2) Also, this pulse width variable self-reset circuit (Figure 1)
In the word line drive circuit (955) and the column selection circuit (958) for writing, or in the row decoder (954) and the column decoder (957). By making (958) a normal CMOS circuit instead of a self-reset circuit, the pulse widths of the word line (35) and column selection line (39) at the time of writing and reading are set to different values at the time of writing and at the time of reading, Word line when writing
The pulse width of (35) and the column selection line (39) is made larger than that at the time of reading. (See FIGS. 3 and 4) In order to achieve the second object, according to the embodiment of the present invention, two sets of latch type amplifier circuits (961, 962) are prepared, and the output of the latch type amplifier circuit ( 68, 69, 72, 73) to the latch circuit (8
40, 841 and 843, 844). (See Figs. 11 and 12) Control signals (70, 74) for fetching the output signals (66, 67) of the sense amplifiers (505, 506, 507) to the latch type amplifier circuit are alternately set to low level (hereinafter "L level"). "Or" L "), and also
The activation signals (71, 75) of the latch type amplifier circuit are alternately set to a high level (hereinafter "H level" or "H"). In addition, the data acquisition control signal (70, 74) indicates the time during which the activation signal (71, 75) of the latch type amplification circuit becomes "H" and is activated.
Set longer than the time that is "L". (See Figure 15)

[0005]

In the typical embodiment of the present invention (FIG. 1), the time at which the MOS (301, 102) that resets the signal becomes conductive can be delayed by the control signal (40), so the output signal (20) The pulse width of can be increased. By using this circuit (FIG. 1) in the word line drive circuit (955) and the column selection circuit (958) for writing, the pulse width of the word line (35) and column selection line (39) at the time of writing can be It can be larger than that when reading. As a result, stable writing characteristics can be achieved even when using a fine memory cell that has reliability against alpha-ray incidence, which is provided with measures such as adding capacitance to the memory cell or increasing the feedback time constant of the flip-flop of the memory cell. A high-speed pipeline memory can be realized. (Figure
3) According to the embodiment of the present invention (FIGS. 11 and 12), two sets (961 and 962) of latch type amplifier circuits are prepared, and the output (6
8, 69, 72, 73) latch circuit (840, 841 and 843, 844)
The cycle time of each latch-type amplifier circuit (961, 962) can be doubled by holding it at and operating alternately, and the activation signal (71, 75) of the latch-type amplifier circuit becomes "H". Is activated by the data acquisition control signal (70, 7
It can be set longer than the time when 4) is "L". It is possible to amplify the output signal (66, 67) of the sense amplifier (505, 506, 507) to the power supply voltage with the MOS amplifier (961, 962) by setting the activation time of the latch type amplifier circuit to be long. Becomes In addition, the latch type amplifier circuit (961, 962), the latch circuit (8
40, 841 and 843, 844)) and store the data alternately, the characteristic is that the data can be read stably even if the access time changes when reading the data in a cycle time shorter than the access time. realizable.

[0006]

FIG. 1 shows an embodiment of the decoding circuit of the present invention, and FIG. 2 shows the operation waveforms of the circuit of FIG. The circuit of FIG. 1 functions as a NAND circuit which outputs NAND logic signals of inputs 10 and 11 to 30 and an inverter circuit which outputs a signal having a phase opposite to that of 30 to 20. The following measures have been taken to increase the speed. Figure
In the circuit of 1, PMOS 400, 401, NMOS 200
The gate width is NMOS
It is designed to be sufficiently smaller than 100, 101 and PMOS 300. PMO
S 301 and NMOS 102 are designed with a sufficiently large gate width. Also, in order to make the pulse width of the output 20 variable, a delay circuit 950
A signal 40 for controlling the pulse width is applied to.

The operation of the circuit shown in FIG. 1 will be described in detail with reference to FIG. The operation waveform of FIG. 2 shows a waveform when the control signal 40 is set to “L” in order to increase the pulse width of the output 20. A pulse that changes from "L" to "H" and then to "L" as shown in Fig. 2 is input to inputs 10 and 11, and output 20 changes from "L" to "H" and then to "L". A pulse is output. At the same time, the pulse width control signal 40 is changed from "H" to "L" and then to "H". When inputs 10 and 11 are "L", 30 is "H", 20 is "L"
So, 31 is "H" and 32 is "L". Inputs 10 and 11 are "L"
When changing from "H" to 30, "30" changes to "L" and 20 changes to "H". Even if 20 changes to "H", the NAND circuit 804 is maintained while 40 is "L".
Output 33 of is held at "H". Also, because 20 becomes "H"
The NMOS 201 becomes conductive. Inputs 10 and 11 are "H" from this state
When it changes from "L" to "L", the PMOS 400 and 401 become conductive. However, since its gate width is small, the parallel ON resistance of PMOS 400 and 401 is large. The potential of 30 is the parallel O of PMOS 400 and 401.
It is determined by the resistance division of N resistance and ON resistance of NMOS 201. PMOS 40
Since the parallel ON resistances of 0 and 401 are large, the potential of 30 can be held at “L” even if the gate width of the NMOS 201 is designed to be a relatively small value. Since 30 is "L", PMOS 300 is conductive and 20 holds "H". That is, NMOS 201 and PMOS 30
By configuring the latch circuit with 0, the inputs 10 and 11 change from "L" to "H", and after 20 becomes "H", the inputs 10 and 11 become "H".
Even if it changes from "H" to "L", 20 will be "H" regardless of inputs 10 and 11.
The property of holding is realized. If there is no NMOS 201, 40 is "L", 31 is "H", 32 is "L", PMOS 301, NMOS 10
Inputs 10 and 11 are "H" to "L" even when 2 is not conducting
When it changes to, the PMOSs 400 and 401 become conductive, the potential of 30 changes to "H" gradually, and the potential of 20 changes to "L" gradually.
20 cannot be held at "H" beyond the time constant determined by the parasitic capacitance of 401 and 30, and the load capacitance of 200 and 20. 20 from "H" to "
To reset to "L", turn on PMOS 301 and NMOS 102. When 20 changes to "H" and 40 changes from "L" to 40 changes from "L" to "H", the output of NAND circuit 804 33 changes from "H" to "L", 31 changes from "H" to "L" with delay time of inverters 801 and 802, and 32 changes from "L" to "L" with delay of 803 delay.
The potential of 30 changes from "L" to "H" because the NMOSs 100 and 101 are non-conductive when 31 becomes "L" and the PMOS 301 becomes conductive. Becomes "H", the PMOS
When 300 goes off and 32 goes "H", output 20 goes "H" to "H"
It changes to L ". When 20 changes from" H "to" L ", 31
Becomes "H" and 32 becomes "L". By setting 31 to "H" and 32 to "L", PMOS 301 and NMOS 102 become non-conducting, then the inputs 10 and 11 change from "L" to "H", and 30 becomes From "H"
Even if "L" and 20 change from "L" to "H", PMOS 301, NMOS 102
No through current flows through. As explained above 20
Is changed from "H" to "L" at the time when 40 is changed from "L" to "H" from the NAND circuit 804 and the inverters 801, 802, 803.
Since the delay time is after, the pulse width of 20 (the period of 20 being "H") can be set arbitrarily by changing the time when 40 is changed from "L" to "H". 20 if 40 is fixed at "H"
Needless to say, the pulse width of is determined by the delay time of the NAND circuit 804 and the inverters 801, 802, 803, and operates similarly to the conventional self-reset circuit. For example, the circuit in Figure 1
The simplest read / write control when used in a word line driving circuit will be briefly described here.
In the read state, 40 is always set to "H" to drive the word line (20) with a pulse width determined by the delay time of the delay circuit 950. When writing, set the control signal 40 from "H" to "L" and then "H"
The pulse width of the word line (20) can be increased by changing to. In addition, the circuit of FIG. 1 has been devised as follows for speeding up. Although the gate widths of the PMOS 301 and the NMOS 102 are designed to be large, the gate electrodes of the NMOS 102 and the PMOS 301 are connected to the outputs of the inverters 803 and 802, and the inverter 80
2 inputs are driven at output 20 through 804, 801, 804, 80
The size ratio of 1, 802, 803 is the smallest 804, 801, 802,
The input capacitance of 804 can be made sufficiently small by designing in order of 803. By designing the PMOSs 400, 401, and the NMOS 200 to be sufficiently small, the capacitances of the inputs 10, 11, and the NAND output 30 are represented by the gate capacitances of the NMOSs 100, 101, and PMOS 300, respectively. That is, compared to a normal CMOS circuit, if the current that can be supplied to the load capacitance is the same, the input capacitance will be about 1/2, and the inputs 10 and 11 will change from the non-selected state of "L" to the selected state of "H". The delay time when the output 20 changes from "L" to "H" is shortened, and high-speed operation is possible. As described above, in the circuit of the present invention in FIG. 1, the input signals 10 and 11 and the output signal 20 are pulse signals, and the gate widths of the PMOS 400, 401, and NMOS 200 are sufficient for the NMOS 100, 101, and PMOS 300. A PMOS 301 and an NMOS 102 that are small in size and have a large gate width are provided, and the gate is driven by a NAND circuit 804 and inverters 801, 802, and 803 to achieve high-speed operation.
The input circuit 40 of the NAND circuit 804 is "
It is characterized by realizing the characteristic that the pulse width of the output 20 can be set arbitrarily by designing the time when it changes from "L" to "H". The circuit of Fig. 1 has one delay circuit for one output. An example is shown in Figure 1.
Since it is necessary to keep the occupied area small when using the circuit of, it is desirable to use one delay circuit for every two or four delay circuits. The delay circuit at that time can also be easily configured by replacing the inverter circuit of the delay circuit in FIG. 1 with a logic circuit such as a NOR circuit. In the circuit of FIG. 1, the NAND circuit 950
An example in which the delay time of the delay circuit 950 is controlled by setting the control signal 40 of “L” and designing the time when 40 changes from “L” to “H” is shown. NM
A current limiting MOS is provided in series with the OS and PMOS to change the gate potential of the current limiting MOS to make the current flowing during the switching of the inverter variable, or to output the output of the inverter circuit of the delay circuit and a predetermined capacitance. A control MOS is provided between the two, and the delay time can be changed by means such as turning on and off the control MOS to change the load capacitance.
It goes without saying that the same effect as that of the circuit can be obtained.
In the circuit of FIG. 1, even if a logic function other than NAND logic is used, for example, 804 is an inverter, 801 is a NOR circuit, a control signal is added to the NOR circuit, and the control signal changes from "H" to "L". It goes without saying that the characteristics similar to those of the circuit shown in FIG. 1 can be obtained by designing the time to be performed. In addition, NMOS 201 and PMOS 3
The latch circuit composed of 00 is not limited to the example of the circuit shown in FIG. 1, and if the output circuit 20 can be held at “H” even after the inputs 10 and 11 become “L”, the circuit shown in FIG. It goes without saying that the example is not limited to.

FIG. 3 shows an embodiment of the memory circuit of the present invention.
FIG. 4 shows a timing diagram of the circuit of FIG. 951 in FIG. 3 is clock 12 applied from outside the chip to clock inside the chip
The circuits for generating 34 are 953 and 956 for address signals 13 and 14
The address buffer circuit for fetching into the chip by the in-chip clock 34, 954 and 957 are the decoding circuits using the conventional self-reset circuit, and 955 and 958 are the word driver circuits and column selection circuits using the circuit of FIG. , 800 is a memory cell, 959, 970, 971 is a sense amplifier, 960 is a write circuit, 15 is a write / read control signal, 16 is write data, 35 is a word line, 36 and 37 are data. Line, 39 for column select signal, 41, 42 for common data line, 4
3, 44 are common data lines for writing, 21, 24 are data outputs, 66, 67 are outputs of the sense amplifier 959, NMOS 500, 5
Reference numerals 01 and 502 denote column amplifiers, and NMOSs 503 and 504 denote write transfer MOSs. (For simplification, only one signal 13 and 14 are shown for the address signal for both the row address and the column address, and the rest are omitted.) The internal clock 34 is generated by the external clock 12 to 951 and the address 13, Take in 14. The signals of the address buffers 953 and 956 are decoded by decoding circuits 954 and 957, and further decoded by 955 and 958 to select rows and columns. 953, 954, 955, 956, 95
Outputs of 7 and 958 are "L" unselected, "H" selected, and the on-chip clock 34 changes from "H" to "L" to select and deselect each signal. Change to a state.
The circuit of FIG. 3 shows an example in which the address buffers 953 and 956 and the decoding circuits 954 and 957 are the conventional self-reset circuit, and the word line drive circuit 955 and the column selection circuit 958 are the pulse width variable self-reset circuits of FIG. ing.

The operation of the circuit of FIG. 3 will be described with reference to the timing chart 4. The circuit of FIG. 3 has an address signal, a write control signal 15, and a write data signal while the clock 12 is "H".
Timing is shown in FIG. 4 as a circuit for incorporating 16 in the chip. That is, after the address signal, the write control signal, and the write data signal are confirmed, 12 is changed from "L" to "
It becomes "H" and holds the address signal, write control signal, and write data signal while 12 is "H", and after 12 changes from "H" to "L", next address signal, write control signal, write data As shown in Fig. 4, in the read operation, a set of addresses is supplied from the outside while the external clock 12 changes by one cycle, and in the write operation, the set of addresses is changed by 12 cycles during the two cycles. It supplies a set of addresses, and the read cycle (the cycle labeled read on external clock 12 in Figure 4) requires the external clock 12
Becomes "H" every cycle, the internal clock 34 becomes "L", the address signal is taken into the address buffer circuit, the row and column are selected, and the data is read out through the sense amplifier 959 (for simplicity, in FIG. (The sense amplifier control signal and output timing waveform are omitted.) On the other hand, in the write cycle (the cycle represented by write and wait in Fig. 4), the write control signal 15 becomes "L", and the second cycle of fetching this in the chip, that is, the second write cycle (in Fig. 4, Do not generate the internal clock 34 in the cycle indicated as wait) (even if 12 becomes "H", 34 does not
It remains at "H" and does not change.) Also, the first write cycle
In the cycle (shown as write in Fig. 4), 15 is in "L" state, 12 goes from "L" to "H", and 34 goes from "H" to "L". The control signal 40 is set to "L". Word line 3
5, pulse width control signal 40 before column selection signal 39 becomes "H"
Is set to "L", and 40 is set to "H" after a predetermined time passes after 35 and 39 become "H". This allows word line 3 when writing.
5. The pulse width of the column selection signal 39 can be made larger than the pulse width at the time of reading. Thus, word line 35,
Even if the pulse width of the column selection signal 39 is increased, the
In the second cycle, since the internal clock 34 does not change and remains "H" even when 12 becomes "H", the address signal and the write data are not taken in and the double selection does not occur. As described above, in the circuit of FIG. 3, the pulse width variable self-reset circuit of FIG. 1 is used in the word line drive circuit 955 and the column selection circuit 958.
, The word line 35 and column selection signal at the time of writing.
By realizing the characteristic that the pulse width of 39 is larger than the pulse width at the time of reading, and not generating the internal clock 34 for fetching the address and write data in the second write cycle, the word line and the column select signal line It is characterized by avoiding double selection. In the circuit of FIG. 3, the word line drive circuit 955 and the column selection circuit 958 are shown as an example of the circuit of FIG. 1, but the row decoder 954 and the column decoder 957 are shown in FIG.
Of the word line driver circuit 955 and the column selection circuit 958.
By using a normal CMOS circuit instead of the self-reset circuit, the pulse widths of the word line 35 and the column selection line 39 at the time of writing and reading can be set to different values at the time of writing and at the time of reading. The circuit of FIG. 3 is fast because the direct peripheral circuit is also a self-reset circuit, but the circuit size is large, whereas when the direct peripheral circuit is a normal CMOS circuit, the circuit size is small and the occupied area is large. Can be made smaller.

FIG. 5 shows an internal clock generation circuit of the present invention (see FIG.
951), and FIG. 6 shows operation waveforms of the circuit of FIG.
Reference numeral 47 in FIG. 5 is a cycle control signal at the time of writing, and when 47 is "L", the circuit of FIG. 5 outputs a signal having a phase opposite to that of the clock input 12 inside the chip at the first cycle at the time of reading and writing. It works as an inverter circuit that outputs to the clock 34 of, and even if the clock input 12 changes in the second cycle of writing,
Acts as a circuit that holds "H". When 47 is "H", the on-chip clock 34 is generated when the cycle 12 changes at the time of both writing and reading. By providing the cycle control signal 47 at the time of writing, the word line 35 at the time of writing,
If the cycle time of the external clock 12 is sufficiently long for the pulse width of the column selection signal 39, the write cycle is set to 12
There is an advantage that it is possible to use the external clock 12 as one cycle for both reading and writing without reading the above two cycles. FIG. 6 shows a case where 47 is "L" and writing is performed.

The operation of the circuit shown in FIG. 5 will be described in detail with reference to FIG. A clock that changes from "L" to "H" and then to "L" is input to the input 12, and the write control signal 15 is 12
Set to "L" before the 1st cycle of becomes "H", and set to "H" before the 2nd cycle of 12 becomes "H". In the first cycle, when 12 becomes "H", the NMOS 103 becomes conductive and the output 34 becomes "L". At this time, the reset signal 45 is "H", 46 is "H", and when 12 becomes "H", the reset signal 45 changes to "L" after delay time of 817, 806, 807, 808, 809. NMOS 104 is non-conducting, PMOS 30
2 becomes conductive and 34 returns to "H". Also, when 15 is "L" and 12 becomes "H", 50 changes to "L" and 52 changes to "H".
1 becomes "L". When 51 becomes "L", 46 becomes "L".
As a result, 12 is returned to "L" and 53 is "H", 54 is "H"
And the reset signal 45 also holds "L". Since 45 remains "L", even if the second cycle of clock 12 becomes "H"
34 keeps "H" without changing to "L". At this time, since the write control signal 15 is "H", 49 changes to "L", 51 changes to "H", and 52 changes to "L". When 51 becomes "H", 46 becomes "H", when clock 12 returns to "L" and 53 becomes "H", 54 becomes "H".
When the 54 becomes "L", the reset signal 45 also becomes "H" and the next change of the clock 12 from "L" to "H" is detected. In the circuit of FIG. 5, the write control signal 15 is sent to the flip-flops (811, 812, 813,
814) to control the reset signal 45, and the output 34 is NAND logic of the external clock 12 and the reset signal 45 to realize the characteristic that the internal clock 34 is not generated in the second cycle when writing, write cycle control By providing the signal 47, the use of the write cycle as one cycle of the external clock 12 is enabled when the cycle time of the external clock 12 is sufficiently long. In FIG. 6, in the first cycle of the external clock 12, the write control signal 1
Although the example in which 5 is returned to "H" and writing is completed in 2 cycles of the external clock 12, the write control signal 15 is set to "H".
By setting the timing to be the second cycle of the external clock 12, writing can be completed in 3 cycles of the external clock 12, and the write cycle time can be easily changed. Also, in the circuit of FIG. 5, the external clock 12 is "
This is an example of a clock circuit for fetching an address inside in the state of "H", but a clock circuit for fetching an address inside when the state of "12" is "L" can be configured with the same circuit as the circuit of FIG. Needless to say.

FIG. 7 shows an address buffer circuit (951, 95 in FIG. 3).
An example of 6) is shown. The circuit of FIG. 7 takes in the address signal 13 with the internal clock 34, and 22 or 23 depending on whether 13 is "H" or "L".
This is a circuit that generates the "H" pulse. Similar to the circuit in FIG. 1, 100-series NMOS is an element for resetting the outputs 22 and 23, and the gate width is designed to be large for speeding up. 200
The series NMOS is an element for giving a DC output potential, and the gate width is designed to be smaller than that of the series 100 NMOS. The operation of the circuit of FIG. 7 is the same as that of the circuit of FIG. 1 except for the delay time control signal of the delay circuit, and detailed description thereof will be omitted.

FIG. 8 shows a pulse width control signal generating circuit of the present invention.
One example (952 in FIG. 3) and FIG. 9 show operation waveforms of the circuit in FIG. In the circuit of FIG. 8, when the write control signal 15 is "L" and the internal clock 34 changes to "L", 57 is "H" and 40 is "L".
Generate a pulse of. Similar to the circuits in FIGS. 1 and 7, 100-series NMOS and 300-series PMOS are elements for switching output, and the gate width is designed to be large for high speed.
200-series NMOS and 400-series PMOS are elements for giving a DC output potential, and the gate width is designed smaller than 100-series NMOS and 300-series PMOS.

The operation of the circuit shown in FIG. 8 will be described with reference to FIG.
Internal clock 34 is "L" when write control signal 15 is "L"
When it changes to, 57 changes from "L" to "H" and then to "L". Five
The pulse width of 7 is determined by the delay time of the delay circuits 827, 828, 829, 830. For a high speed read cycle, it is desirable that the pulse width of the internal clock 34 is small. Meanwhile, the figure
3, as described in the description of FIG. 4, the pulse width control signal 40 is set to "L" before the word line 35 and the column selection line 39 change to "H",
The pulse width of 40 must be larger than the pulse width of 34, and must be set to "H" after a predetermined period of time from 5 and 39 becoming "H". For example, the pulse widths of the internal clock 34, the decode signal, the word line 35 at the time of reading, and the column selection line 39 are all set to the delay time of four inverter stages, and 35 and 39 are set to "H" at the time of writing for stable operation. If the margin when setting the pulse width control signal 40 to "L" is about 3 stages of inverter delay time, the pulse widths of 35 and 39 during writing are equivalent to 8 stages of inverters that are double that during reading. In order to obtain the delay time of about 40, the pulse width of 40 requires a delay time of about 7 inverter stages. Since it is necessary to change the pulse width of the internal clock 34 and the pulse width of the pulse width control signal 40 in this way, the following measures are taken as in the circuit of FIG. After the output 57 of the first stage becomes "H" and 40 changes to "L", even if 57 becomes "L", the reset signal 60 becomes "L" and PM
Until the OS 309 becomes conductive, the inverter 831, the NMOS 208, and the PMOSs 403 and 404 form a latch so that the 40 can hold "L". When the output 57 becomes "H" and 40 becomes "L", the output 59 of the inverter 831 becomes "H". When 59 becomes "H", P
MOS 403 is non-conductive, NMOS 208 is conductive, 57 is "L"
Even if the PMOS 404 becomes conductive due to, "L" is output to 40. After 40 changes to "L", 831, 832, 833, 834, 83
Reset signal 60 after a delay of 5, 836, 837, 838
Becomes "L", the PMOS 309 becomes conductive, and 40 becomes "H". 40 is "
The minimum time after returning to "H" that 57 can be set to "H" is the time until 60 returns to "H" and PMOS 309 becomes non-conducting. The following measures have been taken to reduce the cycle time: In order to reduce the time when 60 becomes "H" after 40 becomes "H", the output signal 40 and the delay circuit are placed in the middle of the delay circuit. Provide 835 that takes the logic with the intermediate output 61 of 40. By this, 40 becomes "H" and 83
61 becomes "H" after a delay time of 1, 832, 833, 834, and at the same time, reset signal 60 becomes "H" after a delay time of 835, 836, 837, 838. As shown in Fig. 8, if the latch circuit and the delay circuit are a set of circuits, even if the first-stage circuit and the second-stage circuit in Fig. 8 are placed at a distance, the long-distance wiring is There is an advantage that only the output 57 of the first stage is enough.
In addition, the pulse width control signal 40 is the word line 35 and the column selection line 39.
Although it has been described that it must be set to "L" before it changes to "H", high speed operation becomes possible by using the self-reset circuit as in the circuit of FIG. Further, when the read operation is changed to the write operation or the write operation is changed to the read operation, the pulse width control signal 40 is the word line 35 corresponding to the read address, the pulse of the column selection line 39 and the word corresponding to the write address. It must be changed during the period between the pulses of the line 35 and column selection line 39 ("L" period when all word lines and column selection lines are in the non-selected state), and there is a delay due to power supply voltage fluctuations, temperature fluctuations, etc. Even if the time fluctuates,
In order to realize stable writing and reading operations, it is necessary to keep the absolute value of the variation in the delay time of the pulse width control signal 40 small. For this purpose, it is effective to reduce the absolute value of the variation in the delay time by using the self-reset circuit and reducing the delay time of the pulse width control signal generating circuit as in the circuit of FIG. As described above, in the circuit of FIG. 8, the pulse width control signal 40 is generated by the self-reset circuit, and the delay time of the pulse width control signal generation circuit is reduced to reduce the absolute value of the variation in the delay time. High-speed read / write switching, internal clock 34 and pulse width control signal 40
Added a latch circuit to change the pulse width of
A logic circuit that receives the pulse width control signal as an input is added to the middle stage of the delay circuit, and the pulse width of the pulse width control signal is large, and only the pulse width of the reset pulse is reduced to facilitate high-speed cycle operation. . Although FIG. 8 shows an example in which the pulse width control signal 40 is generated by a circuit having two stages, it goes without saying that the number of stages is optimized by the load capacity of 40. In the case of FIG. 3, the load capacitance of 40 is the sum of the input capacitances of the delay circuits of all the circuits directly in the peripheral circuit. Since the gate width of the first stage of the delay circuit is designed to be small, if the memory capacity is not large, the load capacity of 40 does not increase, and as shown in Figure 3, all circuits can be driven by the circuit of Figure 8. Needless to say, when the capacity is large and the number of peripheral circuits is large, the charge / discharge current of the pulse width control signal line can be reduced by generating a pulse width control signal by forming a logic with the address signal.

FIG. 10 shows an example of the first stage sense amplifier. In FIG. 10, 800 is a memory cell, 35 is a word line, 36 and 37 are data lines, 39 is a column selection line, 41 and 42 are common data lines, 4
Reference numerals 3 and 44 denote write common data lines. 3 in 63
At the time when 9 becomes "H" and signals are output to 41 and 42
The control signal to become H "is added to stop the precharge by the PMOS 605 and 606 and the equalization by the 607. The circuit of FIG. 10 is characterized in that the load PMOS 603, 604 and 600, 601 of the data line are provided and Column select signal 39 is added to the gate electrode
The gate electrodes of 0 and 601 are the signals of the paired data lines. This makes it possible to reduce the DC current flowing from the positive power supply (Vcc) to the data line at the time of reading and writing data, and at the time of writing, by setting one data line to the GND potential, the other becomes It is possible to prevent the potential of the data line from being lowered due to the leak current or noise due to the conduction of the PMOS having the data line signal applied to its gate.

FIG. 11 shows an example of the second stage sense amplifier of the present invention, and FIG. 15 shows the waveform of the control signal. The circuit of FIG. 11 amplifies the signals of the common data lines 41 and 42 and transmits them to 66 and 67, and
The 961 and 962 are operated alternately and the signals of 66 and 67 are amplified to the power supply voltage. The following measures have been taken to amplify the signals of 66 and 67 up to the power supply voltage. 2 latch type amplifier circuits
A set (961, 962, where 962 is the same circuit as 961) is prepared, and control signals 70, 74 for fetching the output signals 66, 67 of the second stage sense amplifier (505, 506, 507) to the latch type amplification circuit Are alternately set to "L", and the activation signals 71, 7 of the latch type amplifier circuit
5 is set to "H" alternately, and the activation signal 71,
The time when 75 is "H" and is activated is set longer than the time when the data fetch control signals 70 and 74 are "L".

The operation of the circuit shown in FIG. 11 will be described with reference to FIG. When 63 (FIG. 10) becomes “H”, a potential difference occurs between 41 and 42, and when 64 and 65 are set to “H”, a potential difference also occurs between 66 and 67. (It is desirable to shift the times 63, 64, and 65 to "H" in order, but they are shown as the same time for the sake of simplicity.) At the time when a potential difference occurs at 66 and 67, 70 is set to "L". And then 6
The signals of 6 and 67 are taken into 961. At the same time, 71 is set to "H" and the latch type amplifier 961 is activated to amplify the captured signal. 63, 64, 65 "L" at the time when the potential difference between 41 and 42 becomes zero
As a result, 66 and 67 are equalized, 70 is set to "H", and the latch type amplifiers 961 and 66 and 67 are separated. By setting 70 to "H" and disconnecting the latch type amplifiers 961 and 66 and 67, the pulse width of 71 and 6
The pulse widths of 3, 64 and 65 can be set independently.
Also, since the latch type amplifier circuits 961 and 962 are used alternately, 71
The pulse width of can be set to a large value, and the captured signals 66 and 67 can be amplified to about the power supply voltage.

FIG. 12 shows an example of a latch circuit for storing the signals of the outputs 68, 69, 72 and 73 of the circuit of FIG. The circuit in Figure 12
Latch circuits 840, 841, 843, 844 for 68, 69, 72, 73 signals
Hold with, and output the held data with control signals 76, 77
It works to output to 21 and 24. The outputs 68, 69 of the circuit of FIG.
Since 72 and 73 are at the potential of the positive power supply (Vcc) 2 when they are equalized, the signal stored in the circuit of FIG. 12 is 68,
It is retained without being destroyed by the equalization of 69, 72, 73. Also, data can be output to the outside by setting 76 and 77 to "L".

FIG. 13 shows the control signals 70, 71, 74, 75 of the present invention.
FIG. 16 shows an example of the generation circuit of FIG. 11 and the waveform of the control signal. The circuit of FIG. 13 is similar to the circuit of FIG.
It is characterized by generating 0, 71, 74, 75 (FIG. 11).
The NAND signals of the clock signal 84 and the selection signals 82 and 83 are set to 70 and 74, the signals of 70 and 74 are input to the self-reset circuit to which a latch circuit is added, and the output signals thereof are set to 71 and 75. 964 is 9
It shows the same circuit as 63. By using a self-reset circuit with a latch circuit, 71 with a large pulse width,
75 signals are generated from 70 and 74 signals.

FIG. 14 shows an example of a circuit for generating the selection signals 82 and 83 of the circuit shown in FIG. The circuit of FIG. 14 fetches the selection signal 17 supplied together with the address signal from the outside of the chip into the flip-flops 855, 856, 857 and 858 at the clock 12 and the delay circuits 965 and 966 so that the circuit of FIG. 11 operates at the time. Delay and supply signal to 82, 83 in FIG. Since the memory circuit to activate (961, 962 in Fig. 10) can be specified from the outside of the chip, the data output corresponding to a predetermined address can be changed to 78 in Fig. 12.
You can specify whether to store in 80 or 80. As a result, the user of the memory can determine which of 76 and 77 is set to "L" to obtain the corresponding data output, which has the advantage of simplifying the control circuit.

[0021]

As described above, according to the present invention, the read cycle and the write cycle can be set independently while using the self-reset circuit for the decoder.
It is possible to realize a highly reliable memory capable of a stable high-speed read cycle even if the address access time changes while using an OS device.

[Brief description of drawings]

FIG. 1 is a diagram of a decoding circuit showing an embodiment of the present invention.

FIG. 2 is a schematic diagram of operation waveforms in FIG.

FIG. 3 is a diagram showing an example of a memory circuit of the present invention.

FIG. 4 is a schematic diagram of the timing waveform of FIG.

FIG. 5 is a diagram showing an example of a clock generation circuit of the present invention.

FIG. 6 is a schematic diagram of operation waveforms in FIG.

FIG. 7 is a diagram showing an example of an address buffer circuit.

FIG. 8 is a diagram showing an example of a pulse width control signal generation circuit of the present invention.

9 is a schematic diagram of the operation waveforms of FIG.

FIG. 10 is a diagram showing an example of a sense amplifier circuit.

FIG. 11 is a diagram showing an example of a sense amplifier circuit.

FIG. 12 is a diagram showing an example of a latch.

FIG. 13 is a diagram showing an example of the control signal generation circuit of FIG. 11.

14 is a diagram showing an example of a selection circuit of the circuit of FIG.

FIG. 15 is a schematic diagram of operation waveforms of the control signal of the circuit diagram 11 of the present invention.

16 is a schematic diagram of operation waveforms in the circuit diagram 13. FIG.

[Explanation of symbols]

1 ... GND terminal, 2 ... Positive power supply terminal, 10, 11 ... Signal input, 1
2, 34, 84 ... Clock signal, 13, 14 ... Address signal, 15
... write control signal, 16 ... write data, 17 ... selection signal of external input latch type amplifier circuit, 20, 22, 23 ... signal output, 21, 24 ... data output, 30 ... NAND output, 31, 32, 45,
55, 56, 58, 60, 86 ... Reset signal, 33, 85 ... Delay signal, 35 ... Word line, 36, 37 ... Data line, 39 ... Column selection signal, 40 ... Pulse width control signal, 41, 42 ... Common Data line,
43, 44 ... Write common data line, 46, 48, 49, 50, 5
1, 52, 53, 54, 57, 59, 61, 62, 78, 79, 80, 81, 8
7, 88… Terminals inside the circuit numbered for explanation, 47
... Write cycle control signals, 63, 64, 65, 70, 71, 7
4, 75 ... Sense amplifier control signal, 68, 69, 72, 73 ... Latch type amplifier circuit output, 76, 77 ... Latch circuit output control signal, 82, 83 ... Latch type amplifier circuit selection signal, 100 series ... NMOS transistor with large gate width, 200 series ... NMOS transistor with small gate width, 300 series ... PMOS transistor with large gate width, 400 series ... PMOS transistor with small gate width, 500 series ... NMOS transistor, 600 series ... PMOS transistor, 700 ... Capacity, 800 ... Memory cells, 801, 802, 80
3,807,808,809,810,816,817,818,819,820,82
1, 822, 823, 824, 825, 826, 827, 828, 829, 830, 83
1, 832, 833, 834, 836, 837, 838, 839, 842, 846, 84
7, 848, 849, 851, 852, 853, 854 ... Inverter circuit, 8
04, 806, 811, 812, 813, 814, 815, 840, 841, 843, 8
44, 845, 850, 855, 856, 857, 858 ... NAND circuit, 835,
... NOR circuit, 950, 965, 966 ... Delay circuit, 951 ... Clock generation circuit, 952 ... Pulse width control signal generation circuit, 953, 956
... Address buffer, 954,957 ... Decoding circuit, 955 ...
Word driver, 958 ... Column selection circuit, 959, 970, 971 ... Sense amplifier, 960 ... Write circuit, 961, 962 ... Latch type amplification circuit, 963, 964 ... Sense amplifier control signal generation circuit,

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical display location G11C 11/409 H03K 5/13 G11C 11/34 311 354 A (72) Inventor Katsuro Sasaki 1 Higashi Koikeku, Kokubunji, Tokyo 280-chome, Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A first CM comprising an NMOS transistor and a PMOS transistor, and a gate electrode to which a first input signal is applied.
In a circuit in which the drain electrode of the first MOS transistor is connected to the first output of the OS circuit and a signal in phase with the first output signal is added to the gate electrode of the first MOS transistor with a delay of a predetermined time, A semiconductor integrated circuit characterized in that the gate signal of the first MOS transistor is generated in a first delay circuit including a first output signal as an input, and the delay time of the first delay circuit is variable. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit characterized by using a logical function of a first control signal and a first output signal for delay time control in order to make the delay time of the first delay circuit variable. 3. The semiconductor integrated circuit according to claim 1, wherein
In order to make the delay time of the first delay circuit variable,
A semiconductor integrated circuit characterized by using a latch circuit for holding the potential of the output signal of. 4. A semiconductor integrated circuit comprising: a memory matrix including a plurality of memory cells; address means for selecting at least one of the memory cells of the memory matrix in response to an address signal; and the selected memory cell. In a memory circuit including a sense amplifier that amplifies a signal from the
The drain electrode of the first MOS transistor is connected to the first output of the first CMOS circuit to which the input signal of 1 is applied.
Includes a first circuit that applies a first reset signal that is in phase with the first output signal and delayed by a predetermined time to the gate electrode of the transistor, and that is a word line or column selection signal line of the memory matrix when reading and writing data. The semiconductor integrated circuit is characterized in that the periods in which are selected are set to different values. 5. The semiconductor integrated circuit according to claim 4, wherein:
The address means is a first address generated from the reference clock signal.
The address signal is taken in response to the first internal clock signal, the first internal clock signal is generated from at least the reference clock signal and the write control signal, and the cycle time of the first internal clock signal is the reference time when reading data. A semiconductor integrated circuit, which is equal to the clock signal and is longer than the cycle time of the reference clock signal at the time of writing. 6. The semiconductor integrated circuit according to claim 4, wherein:
In order to set the period during which the word line or the column selection signal line of the memory matrix is in the selected state at the time of reading and writing the data to different values, the first reset signal of the first circuit is the first circuit. The semiconductor integrated circuit is characterized in that the output of the first delay circuit is generated in the input and the delay time of the first delay circuit is variable. 7. A semiconductor integrated circuit comprising: a memory matrix including a plurality of memory cells; address means for selecting at least one of the memory cells of the memory matrix in response to an address signal; and the selected memory cell. A first storage circuit having its input connected to the output of the sense amplifier, and a second storage circuit having its input connected to the output of the sense amplifier. In the memory circuit, the first and second storage circuits are respectively controlled by a first control signal for capturing an output signal of the sense amplifier and a second control signal for amplifying the captured signal, 2
2. The semiconductor integrated circuit, wherein the activation period of the control signal is set to be longer than the activation period of the first control signal.