JPH0778697B2 - Timing generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a timing generation circuit capable of freely setting a timing signal used when controlling an electronic device or the like.

[Conventional technology]

FIG. 2 is a configuration explanatory view showing a conventional variable timing generation circuit. In the figure, 1 is a timing counter for counting the reference clock φ, and 1L is a latch signal _DCR.
Accordingly, the latch that holds the reset value of the timing counter 1 and the comparator 1C that compares the count value of the timing counter 1 with the value in the latch 1L.

Further, TM _{1 to} TM _n are timing generation circuits that generate timing signals T _{1 to} T _n . The timing generation circuit TM ₁ is provided with two comparators C _1a and C _1b , two latches L _1a and L _1b, and one flip-flop FF ₁ in the inside thereof.
L _1a and L _1b are set count values of the timing signal T ₁ , respectively.
The reset count value is held according to the latch signals D _S1 and D _R1 , and the comparator C _1a compares the count value CA of the timing counter 1 with the value in the latch L _1a , and the comparator C _1a
1b is the count value CA of the timing counter 1 and the latch L _1b
The values in are compared and the results are respectively flip-flops FF ₁
Is output to. Flip-flop FF ₁ is comparator C
_The timing signal T ₁ is output with the output signal of _1a as the set signal S ₁ and the output signal of the comparator C _1b as the reset signal R ₁ . The other timing generation circuits TM _{2 to} TM _n are also
It has the same configuration as the timing generation circuit TM ₁ .

In such a configuration, the latch signals D _CR , D _{S1 to} D _Sn , D _R1
By sending ~ D _Rn to the latches 1L, L _{1a to} L _na , L _{1b to} L _nb , the reset value of the timing counter 1 and the set values and reset values of the timing generation circuits TM _{1 to} TM _n are appropriately set.

Then, a reset signal (not shown) is sent to the timing counter 1
By outputting to, the count value of the timing counter 1
Set CA to the initial value (for example, "0").

The subsequent operation will be described in the timing generation circuit TM ₁ . Latches L _1a and L _1b in the timing generation circuit TM ₁ store predetermined data d _1s and d _1r by latch signals D _S1 and D _R1 , respectively, and comparators C _1a and C _1b store timing counter 1 data. It is constantly compared with the count value CA.

Then, the count value CA of the timing counter 1 and the latch
When the data d _{1s of} L _1a matches, the set signal S ₁ is sent to the cassette input section of the flip-flop FF ₁ , and when the count value CA of the timing counter 1 and the data d _1r of the latch L _1b match, the reset input of the flip-flop FF ₁ Send reset signal R ₁ to the section. Therefore, assuming that d _1s <d _1r , the timing signal T ₁ output from the flip-flop FF _{1 rises} when the count value CA of the timing counter 1 reaches d _1s ,
After that, when the count value CA reaches d _1r , it falls.

Such an operation is similarly performed in parallel in the timing generation circuits TM _{2 to} TM _n . After that, timing counter 1
When the comparator 1C detects a match between the count value CA and the data in the latch 1L, the comparator 1C outputs the control signal S _C.
Is output to the timing counter 1 and the count value CA of the timing counter 1 is initialized, one cycle ends. Therefore, by properly setting the latch signals D _{S1 to} D _Sn and D _{R1 to} D _Rn , it is possible to generate _n timing signals T _{1 to} T _n . The timing of each timing signal T _{1 to} T _n is latched by the latch signals D _{S1 to} D _Sn and D _{R1 to} D _Rn.
It can be changed freely by storing arbitrary set values and reset values in _{1a to} L _na and L _{1b to} L _nb .

[Problems to be solved by the invention]

Since the conventional variable timing generation circuit is configured as described above, each of the timing generation circuits TM _{1 to} TM _n requires a latch and a comparator. Therefore, by increasing the number of timing signals T, the circuit scale increases and power consumption also increases. For this reason, there is a problem that not only the chip area becomes large at the time of integration, but also the manufacturing conditions of the integrated circuit become strict, which eventually leads to an increase in cost in commercialization.

The present invention has been made to solve the above problems, and the circuit scale and power consumption do not increase even if the number of timing signals is increased. Therefore, when integrated, the chip area becomes small and An object of the present invention is to obtain a timing generation circuit that generates a plurality of variable timing signals that is easy to implement.

[Means for solving problems]

A timing generation circuit according to the present invention stores a timing counter that generates a timing count value according to the passage of time and a count value that indicates the operation timing of each of a plurality of timing signal generation circuits in association with an address according to a temporal order. A storage section for sequentially specifying the address, and sequentially selecting a count value indicating the operation timing from the storage section according to the temporal order, and the plurality of timing signals according to the temporal order. Second selecting means for sequentially selecting the generating circuits, a timing count value of the timing counter and the first
Comparing means for comparing the count values selected by the selecting means, and the timing signal generating circuit selected by the second selecting means outputs the timing signal in response to the comparison result of the coincidence by the comparing means. Configured to generate.

[Action]

In the present invention, since the count value for instructing the operation timing of each timing generation circuit is stored in association with the address in the storage unit, it is not necessary to provide a storage area for instructing the operation timing in each timing generation circuit. Since the comparing means compares the timing count value of the timing counter with the count value selected by the first selecting means, it is not necessary to provide a comparing means in each timing generating circuit.

〔Example〕

FIG. 1 is a configuration explanatory view showing a timing generation circuit according to an embodiment of the present invention. In the figure, 1 is a timing counter, which counts the reference clock φ. Reference numeral 2 denotes a comparator, which compares the count value CA of the timing counter 1 with the output value S3 _a of the memory 3, and the result thereof is a timing counter / address counter reset gate 4, timing set gates GS _{1 to} GS _n and timing reset gate GR. Output as a match signal / mismatch signal to _{1 to} GR _n .

The memory 3 has information about which timing set gates GS _{1 to} GS _n , timing reset gates GR _{1 to} GR _n or the timing counter / address counter reset gate 4 is valid and the count value to be set (reset) at that time. The data DT are stored by allocating addresses in the order of their time sequence (that is, the ascending order of count values). Such data DT is sent to the address decoder 5
Gate decoder in accordance with the address signal A _d that is specified, the count value is output as an output shaft S3 _a to the comparator 2, as specified gate _{4, GS 1 ~GS n, GR} 1 ~GR information _n is the output value S3 _b by 8 is output.

The address decoder 5 decodes the address value S6 designated by the address counter 6, sent to the memory 3 as the address signal A _d, the address counter 6 is the address control circuit 7 addresses a control signal S7 from is sent, the address value 1 When the reset signal S4 is sent from the timing counter / address counter reset gate 4, the address value is set to the initial value.

According to the output value S3 _b of the memory 3, the gate decoder 8 receives the timing counter / address counter reset gate 4,
A gate-on signal S _ON is sent to any of the timing set gates GS _{1 to} GS _n and the timing reset gates GR _{1 to} GR _n .

In the timing counter / address counter reset gate 4, the output signal S2 of the comparator 2 is a coincidence signal,
Further, when the gate-on signal S _ON is sent by the gate decoder 8, the timing counter 1 and the address counter 6
Send a reset signal S4 to initialize the.

The timing cassette gate GS ₁ ~GS _n are each output signal S2 of the comparator 2 is coincidence signal, and when a gate-on signal S _ON is sent by the gate decoder 8, the set input of the flip-flop FF ₁ to ff _n When the output signals of the comparators 2 of the timing reset gates GR _{1 to} GR _n are coincident signals and the gate-on signal S _ON is sent by the gate decoder 8,
It is a gate that sends a reset signal to the reset input section of the flip-flops FF _{1 to} FF _n . In addition, flip-flop
FF _{1 to} FF _n have the same configuration as the conventional _one and generate timing signals T _{1 to} T _n .

In such a configuration, first, the data DT having the above-described configuration is stored in the memory 3 in advance, and the timing counter 1 and the address counter 6 are initialized by a reset signal (not shown). At this time, the data DT is stored in the memory 3 in the order of addresses according to the temporal order. Therefore, in the storage area of the memory 3 which is accessed by the address signal A _d output from the address decoder 5 in response to the output signal S6 of the initialized address counter 6, the flip-flop to be set (reset) first. FF _{1 to} FF _n gate GS
Information that specifies _{one of 1 to} GS _n and GR _{1 to} GR _n and its count value are held. Then, these pieces of information are output to the gate decoder 8 and the comparator 2 as signals S3 _b and S3 _a , respectively. The gate decoder 8 in accordance with signal S3 _b is corresponding gate GY _X (Y: S, R and x: 1 to n) to send a gate-on signal S _ON.

Thereafter, when the output value S3 _a count value CA and the memory 3 of the timing counter 1 match, the comparator 2 is coincidence signal all gate _{GS 1 ~GS n, GR 1 ~GR} n and the timing counter, the address counter reset gate 4 Send to. Here, since the gate-on signal S _ON is sent only gate GY _X, flip-flops F which is connected to the gate GY _X
The timing signal T _X is set (reset) only for F _X.

On the other hand, when the coincidence signal is sent from the comparator 2, the address counter control circuit 7 sends the signal S7 to the address counter 6.
Is sent, and the address value S6 of the address counter 6 is incremented by 1.
As a result, the data DT of the memory 3 accessed by the address signal A _d decoded by the address decoder 5
The gate GS ₁ of the flip-flop FF ₁ to ff _n should be set (reset) to the second ~GS _n, GR ₁ ~GR _n or timing counter address counter reset gate 4
It becomes the data which shows the information which designates either of these and its count value.

After that, the same operation is repeated, and the information in the memory 3 is sequentially selected by the address decoder 5 in accordance with the time sequence of the timings T _{1 to} T _n , and finally the timing counter / address counter set gate 4 is selected. The reset signal S4 is applied from the counter / address counter reset gate 4 to the timing counter 1 and the address counter 6 and initialized, whereby one cycle is completed. Further, at the timing of each timing signal T _{1 to} T _n, a memory write signal D _i is sent from a CPU (not shown) or the like, and
It can be freely changed by appropriately rewriting the data DT in.

In this way, the information indicating which gates 4, GS _{1 to} GS _n , GR _{1 to} GR _n are turned on and the count value thereof are stored in the memory 3 as a set according to the temporal order, so that each flip-flop is stored.
It is not necessary to provide latches corresponding to FF _{1 to} FF _n . Further, since the count value according to the temporal order is sequentially sent from the memory 3 to the comparator 2 and compared with the count value CA of the timing counter 1, the flip-flops
It is not necessary to provide comparators corresponding to FF _{1 to} FF _n . Therefore, even when the number of timing signals T is increased,
The circuit scale does not increase, the chip area increases,
It does not lead to an increase in power consumption. Therefore, integration is easy. Further, by reducing the chip area, the processing speed can be increased.

The gate GS ₁ ~GS _n in this embodiment, the selection of the GR ₁ ~GR _n, the data DT in the memory 3 was performed by decoding the gate decoder 8, the output address A _d of the address decoder 5 It can also be configured to respond and select sequentially. In this case, the data DT stored in the memory 3
Has a merit that only the count value can be used and the gate decoder 8 can be omitted. However,
The selection order of the gates GS _{1 to} GS _n and GR _{1 to} GR _n is fixed. Further, the decoders 5 and 8 can be divided into a plurality of functions by dividing the functions (for example, upper bits and lower bits) as necessary, and can reduce the formation area of each to facilitate integration.

〔The invention's effect〕

As described above, according to the present invention, the count value instructing the operation timing of each timing generation circuit is stored in one storage unit in association with the address, and the timing count of the timing counter is stored by one comparing unit. Since the value is compared with the count value selected by the first selecting means, the circuit scale and power consumption do not change even if the number of timing signals increases. As a result, it is possible to obtain a timing generation circuit that generates a plurality of variable timing signals that has a small chip area when integrated and is easy to integrate.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a timing generating circuit according to an embodiment of the present invention, and FIG. 2 is a structural explanatory view of a conventional timing generating circuit. In the figure, 1 is a timing counter, 2 is a comparator, 3 is a memory, 4 is a timing counter / address counter reset gate, 5 is an address decoder, 6 is an address counter, 7 is an address control circuit, 8 is a gate decoder, and GS ₁ to GS _n is a timing set gate, GR _{1 to} GR _n
Is a timing reset gate, FF _{1 to} FF _n are flip-flops, and T _{1 to} T _n are timing signals. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A timing counter for generating a timing count value according to the passage of time, and a storage section for storing a count value indicating the operation timing of each of a plurality of timing signal generation circuits in correspondence with an address in accordance with a temporal order. , First selecting means for sequentially designating the addresses and sequentially selecting a count value for instructing the operation timing from the storage unit in accordance with the temporal order, and sequentially performing a plurality of timing signal generation circuits in accordance with the temporal order. A second selection means for selecting; and a comparison means for comparing the timing count value of the timing count with the count value selected by the first selection means, the timing selected by the second selection means The signal generation circuit outputs a timing signal in response to the comparison result of the coincidence by the comparison means. Timing generating circuit to produce. 2. The storage section stores, as data, information of a timing generation circuit to be selected in addition to a count value instructing the operation timing, at the same address, and the second selection means includes the first selection means. The timing according to claim 1, which is means for sequentially selecting the plurality of timing signal generation circuits according to information of the timing generation circuit to be selected in the data in the address of the storage section designated by the selection means. Generation circuit. 3. The second selecting means sequentially selects the plurality of timing signal generating circuits in response to an address designated by the first selecting means.
The timing generation circuit according to the item. 4. The plurality of timing signal generation circuits each include a flip-flop that is set or reset in response to a result of comparison of the coincidence by the comparison means. The timing generation circuit according to any of the above.