JPH0778873A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor integrated circuit incorporating a test circuit of a matrix probing system adapted to a standard cell system. [Structure] The outlet position of the standard cell of the probe line running in each standard cell is made constant, and the distance between the end of the standard cell and the outlet position of the probe line is also regulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standard cell type semiconductor integrated circuit in which a plurality of types of standard cells are arranged, and more specifically, a standard cell type semiconductor integrated with a so-called matrix probing type test circuit. Related to integrated circuits.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been used in a wide range of fields.
One is the so-called standard cell system. In this standard cell method, a library of a plurality of types of standard cells, each of which has been confirmed to have a predetermined circuit function, is prepared, and by combining them, a circuit in which a desired operation is executed as a whole is configured. It is a method to do. If this standard cell method is adopted, it takes longer than the gate array in terms of wafer manufacturing because it needs to be manufactured from the beginning of the previous process corresponding to each product type, but the design time is shortened as with the gate array. In addition, it is possible to prevent a wasteful chip area portion from occurring in the gate array.

With the recent trend toward higher integration of semiconductor integrated circuits, how to test manufactured semiconductor chips has become an increasingly important issue. Various proposals have been made.
One of such test circuits is a matrix probing test circuit. FIG. 5 is a schematic diagram of a matrix probing type test circuit, and FIG. 6 is an enlarged view of a portion indicated by a circle A in FIG.

A large number of probe lines 10 are formed so as to extend in the vertical direction of FIG. 5, and a large number of sense lines 20 are formed so as to extend in the horizontal direction. At each intersection of each probe line 10 and each sense line 20, a sense transistor 30 is formed as shown in FIG. One end 31 of the sense transistor 30 is connected to a predetermined node of the internal circuit, and the other end is connected to the sense line 20. The gate of the sense transistor 30 is connected to the probe line 10. The probe line 10 is usually formed of a polysilicon layer so as to also serve as the gate itself of the sense transistor 30. When a certain probe line 10 is activated by the probe line driver 40, the probe line 10
The sense transistor 30 connected to the node is turned on, and the signal of the node connected to the sense transistor 30 is read out via the sense transistor 30, the sense line 20, and the sense line driver / receiver 50, whereby the node The quality of the signal can be determined.

[0005]

The above-described matrix probing type test circuit has a large number of probe wires 10,
It is necessary to form the sense lines 20 vertically and horizontally, which is suitable for a gate array in which the cell arrangement is regularly determined in advance, but in the case of the standard cell system, the cell size also differs depending on the cell type, Further, since the position of the node in the cell that requires sensing varies depending on the type of the cell, the probe line cannot be formed linearly as shown in FIG. When forming, a problem is how to adapt the matrix probing type test circuit to the standard cell type semiconductor integrated circuit.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor integrated circuit in which a matrix probing type test circuit adapted to the standard cell type is incorporated.

[0007]

In a semiconductor integrated circuit of the present invention that achieves the above object, a plurality of probe lines extend in a predetermined first direction and a predetermined second direction intersects with the first direction. A plurality of sense lines extend in the direction, and a matrix probing test circuit that senses the signal of each node near each intersection by each sense transistor arranged at each intersection of each probe line and each sense line is incorporated. Also, in the standard cell type semiconductor integrated circuit, each probe line is formed of a polysilicon layer that also serves as a gate of a sense transistor, and the standard cell has a constant dimension in the first direction regardless of type. In addition, the dimension in the second direction is variable for each type, and further, the plurality of standers of the probe wires arranged in the first direction are arranged. The second part of the end of the standard cell in the first direction of each probe line passing through the inside of the standard cell is arranged such that the portions connecting the cells are arranged on the respective straight lines extending in the first direction. The position in the direction of is defined.

[0008]

According to the semiconductor integrated circuit of the present invention, each standard cell has a second probe line at the end in the first direction.
Since the position in the direction of is determined by a predetermined rule as described above, this test circuit of the matrix probing system is suitable for the standard cell semiconductor integrated circuit.

[0009]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a diagram showing the structure of a cell in one embodiment of the present invention. The size of the cell in the present embodiment in the vertical direction in FIG. 1 is constant regardless of the type of cell, and the method in the horizontal direction in FIG. 1 is variable length according to the circuit scale inside the cell.

Inside the cell, probe lines made of a polysilicon layer extend in the vertical direction in FIG. 1. Within the cell, the intervals between the probe lines are varied depending on the position of the node to be sensed. However, the horizontal positions of the upper and lower edges are constant regardless of the cell. Here, the distances between the adjacent probe wires in the left-right direction at the upper and lower edges are the distances A and B (A ≧ B) as shown in the figure.
The distance between the left and right ends of the cell and the adjacent probe lines is equal to or less than the wider distance A within the cell when there are even number of probe lines in the cell as shown in the figure. When there is an odd number of probe lines, one is the interval A or less and the other is the interval B or less. This is a limitation due to the need to place probe lines adjacent to this cell. In this cell, in addition to the power supply line and the ground line, the sense line is also planned to be wired in a single metal layer at the positions shown in the figure.

FIG. 2 is a schematic diagram showing a cell allocable area in a chip. Finally, the probe lines connected to each one are arranged in the wiring channel region such that the probe lines are aligned in the vertical direction in the drawing in the wiring channel region, and the intervals between them are the intervals A and B alternately. The position of the probe wire within is pre-planned. Each cell is arranged in the cell allocable region, and at that time, the probe lines in the cell and the probe lines in the wiring channel region are connected to each other.

FIG. 3 is a schematic diagram showing a state in which each cell is arranged in the cell arrangeable area. In the portion where the cells are arranged as shown in the figure, the probe lines in the cells are connected to the probe lines in the wiring channel region. However, in this state, the cell is not arranged, and the probe line remains divided. Therefore, next, the divided probe wires are connected.

FIG. 4 is a schematic diagram showing how the divided probe wires are connected. In the example shown in the figure, the cell for the probe line connection (feedthrough cell) is prepared in the library, and the cell is not placed. Therefore, depending on the cell, the feedthrough cell is placed at the place where the probe line was not connected. This connects all probe wires to a single wire.

After that, as in the normal placement and routing process,
The power supply line and the ground line are connected, but this processing includes sense lines and connections. Further, signal lines are also wired, which realizes a standard cell type semiconductor integrated circuit in which a matrix probing type test circuit is incorporated.

[0015]

As described above, according to the present invention,
A standard cell type semiconductor integrated circuit in which a matrix probing type test circuit is incorporated can be realized by adopting a design method that can be easily mounted on a place-and-route tool currently on the market.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a cell according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a cell disposable area in a chip.

FIG. 3 is a schematic diagram showing a state in which each cell is arranged in a cell arrangeable area.

FIG. 4 is a schematic diagram showing how to connect divided probe wires.

FIG. 5 is a schematic diagram of a matrix probing test circuit.

6 is an enlarged view of a portion indicated by a circle A shown in FIG.

[Explanation of symbols]

 10 probe line 20 sense line 30 sense transistor 40 probe line driver 50 sense line driver / receiver

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04

Claims (1)

[Claims] 1. A plurality of probe lines extend in a predetermined first direction, and a plurality of sense lines extend in a predetermined second direction intersecting the first direction, and each probe line and each A standard cell system in which a plurality of types of standard cells are arranged, in which a matrix probing test circuit for sensing the signal of each node in the vicinity of each intersection with each sense transistor arranged at each intersection with the sense line is incorporated. In the semiconductor integrated circuit, the probe lines are made of a polysilicon layer that also serves as the gate of the sense transistor, and the standard cell has a constant dimension in the first direction regardless of type and The dimension in the second direction has a variable length for each type, and further, a plurality of standard cells of the probe lines arranged in the first direction. The second portion at the end of the standard cell in the first direction of each of the probe lines passing through the inside of the standard cell so that the portion connecting the cattle is arranged on each straight line extending in the first direction. The semiconductor integrated circuit is characterized in that the position in the direction of is defined.