JPH0778902A - Circuit element mounting structure - Google Patents
Circuit element mounting structureInfo
- Publication number
- JPH0778902A JPH0778902A JP5172531A JP17253193A JPH0778902A JP H0778902 A JPH0778902 A JP H0778902A JP 5172531 A JP5172531 A JP 5172531A JP 17253193 A JP17253193 A JP 17253193A JP H0778902 A JPH0778902 A JP H0778902A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- circuit element
- conductor layer
- ground
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 回路素子の実装状態で接地導体のインピーダ
ンスの小さい、回路性能の優れた回路素子の実装構造を
提供する。
【構成】 内部に導体層３を有する多層基板１の中央部
にキャビティ２を形成する。このキャビティ２の周囲部
に第１の導体層３と第２の導体層10Ａ〜10Ｄを階層的に
露出形成する。前記第１の導体層３を接地導体15とし、
第２の導体層10Ａ〜10Ｂを信号導体として、回路素子21
の接地端子16Ａ〜16，18Ａ〜18Ｄを接地導体15をボンデ
ィングワイヤ23で接続し、信号端子17Ａ〜17Ｄと信号導
体10Ａ〜10Ｄとを同様にボンディングワイヤ23で接続
し、良好な接地を行う。
(57) [Abstract] [Purpose] To provide a circuit element mounting structure in which the impedance of the ground conductor is small in the mounted state of the circuit element and which has excellent circuit performance. [Structure] A cavity 2 is formed in the center of a multilayer substrate 1 having a conductor layer 3 inside. A first conductor layer 3 and second conductor layers 10A to 10D are hierarchically exposed and formed around the cavity 2. The first conductor layer 3 is a ground conductor 15,
The circuit element 21 using the second conductor layers 10A to 10B as signal conductors.
The ground terminals 16A to 16 and 18A to 18D are connected to the ground conductor 15 by the bonding wire 23, and the signal terminals 17A to 17D and the signal conductors 10A to 10D are similarly connected by the bonding wire 23 to perform good grounding.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、回路基板に搭載する回
路素子の実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for a circuit element mounted on a circuit board.
【０００２】[0002]
【従来の技術】図２には、従来の回路素子の実装構造が
示されている。この回路素子21は四角形状を呈してお
り、その周縁部には信号端子17Ａ，17Ｂ，17Ｃ，17Ｄが
それぞれ設けられている。この各17Ａ〜17Ｄの両側に
は、各信号端子17Ａ〜17Ｄを挟んだ位置に接地端子16
Ａ，18Ａ〜16Ｄ，18Ｄが隙間８を介してそれぞれ設けら
れている。この回路素子21は回路基板22上に搭載されて
おり、回路素子21の周りの回路基板22上には回路素子21
の前後、左右に、前記信号端子17Ａ〜17Ｄと接続する信
号導体14Ａ〜14Ｄが設けられており、これら信号導体14
Ａ〜14Ｄの両側には各信号導体14Ａ〜14Ｄを挟んで、前
記回路素子21に設けた各接地端子16Ａ，18Ａ〜16Ｄ，18
Ｄと接続するための各接地導体15Ａ，19Ａ〜15Ｄ，19Ｄ
が隙間20を介してそれぞれ設けられている。2. Description of the Related Art FIG. 2 shows a conventional mounting structure for circuit elements. The circuit element 21 has a quadrangular shape, and signal terminals 17A, 17B, 17C and 17D are provided on the peripheral portions thereof. On both sides of each of 17A to 17D, ground terminals 16 are provided at positions sandwiching each of the signal terminals 17A to 17D.
A, 18A to 16D, 18D are provided via a gap 8, respectively. The circuit element 21 is mounted on the circuit board 22, and the circuit element 21 is mounted on the circuit board 22 around the circuit element 21.
The signal conductors 14A to 14D connected to the signal terminals 17A to 17D are provided on the front, rear, left and right of the signal conductors 14A to 14D.
Grounding terminals 16A, 18A to 16D, 18 provided on the circuit element 21 with the signal conductors 14A to 14D on both sides of A to 14D.
Ground conductors 15A, 19A to 15D, 19D for connecting to D
Are respectively provided through the gap 20.
【０００３】前記各接地端子16Ａ，18Ａ〜16Ｄ，18Ｄは
ボンディングワイヤ23によって接地導体15Ａ，19Ａ〜15
Ｄ，19Ｄとそれぞれ接続されており、各信号端子17Ａ〜
17Ｄは同様にボンディングワイヤ23によって各信号導体
14Ａ〜14Ｄとそれぞれ接続されている。The grounding terminals 16A, 18A to 16D, 18D are connected to the grounding conductors 15A, 19A to 15 by a bonding wire 23.
D and 19D are connected respectively, and each signal terminal 17A ~
Similarly, 17D uses bonding wires 23 for each signal conductor.
14A to 14D are respectively connected.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記回
路素子21の実装構造では、各信号導体14Ａ〜14Ｄと、こ
れを挟む各２個の接地導体との隙間20が極めて狭いた
め、各接地導体15Ａ，19Ａ〜15Ｄ，19Ｄの導体幅Ｅを十
分に大きくすることができない。そのため、これら接地
導体の断面積は導体幅が狭いので小さくなり、接地導体
の抵抗値が大きくなる。これにより高周波、高速動作の
際に、接地導体の線路でインピーダンスが大きくなり、
回路性能が悪化して回路素子の応答が遅くなって支障を
生ずるという問題があった。However, in the mounting structure of the circuit element 21, since the gap 20 between each of the signal conductors 14A to 14D and each of the two ground conductors sandwiching the signal conductors 14A to 14D is extremely narrow, each ground conductor 15A is formed. , 19A to 15D, 19D, the conductor width E cannot be made sufficiently large. Therefore, the cross-sectional area of these ground conductors is small because the conductor width is narrow, and the resistance value of the ground conductor is large. This increases the impedance of the ground conductor line during high-frequency and high-speed operation,
There is a problem that the circuit performance is deteriorated and the response of the circuit element is delayed to cause a trouble.
【０００５】本発明は、上記課題を解決するためになさ
れたものであり、その目的は、回路素子の実装状態で、
接地導体のインピーダンスの小さい、回路性能の優れた
回路素子の実装構造を提供することにある。The present invention has been made in order to solve the above problems, and its purpose is to mount a circuit element in a mounted state.
An object of the present invention is to provide a mounting structure of a circuit element having a small impedance of a ground conductor and excellent circuit performance.
【０００６】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために、次のように構成されている。すなわち、本
発明の回路素子の実装構造は、回路素子が回路基板に実
装され、回路素子の接地端子が回路基板の接地導体に、
回路素子の信号端子が回路基板の信号導体にそれぞれ接
続されている回路素子の実装構造において、前記回路基
板は内部に１層以上の導体層を有する多層基板により構
成され、この多層基板にはキャビティが設けられ、この
キャビティ内に回路素子が実装されており、キャビティ
の周囲部に第１の導体層と第２の導体層が階層的に露出
形成され、その一方側の導体層を接地導体とし、他方側
の導体層はパターン形成して信号導体としたことを特徴
として構成されている。In order to achieve the above object, the present invention is constructed as follows. That is, the mounting structure of the circuit element of the present invention, the circuit element is mounted on the circuit board, the ground terminal of the circuit element to the ground conductor of the circuit board,
In a mounting structure of a circuit element in which signal terminals of the circuit element are respectively connected to signal conductors of a circuit board, the circuit board is composed of a multilayer board having one or more conductor layers inside, and the multilayer board has a cavity. Is provided, the circuit element is mounted in the cavity, and the first conductor layer and the second conductor layer are hierarchically formed in the periphery of the cavity, and the conductor layer on one side of the first conductor layer and the second conductor layer is used as a ground conductor. The conductor layer on the other side is patterned to form a signal conductor.
【０００７】[0007]
【作用】回路基板として内部に導体層を有する多層基板
にキャビティを設け、このキャビティの周囲部に多層基
板の一部を取り除いた第１の導体層と第２の導体層を階
層的に露出形成し、一方側の導体層を接地導体とし、他
方側の導体層を信号導体とする。回路素子の実装状態に
おいて、前記接地導体は断面積が極めて大きいので良好
な接地が図れる。これにより、接地導体の低インピーダ
ンス化が図れ、高周波、高速動作が可能となる。As a circuit board, a cavity is provided in a multi-layer board having a conductor layer inside, and a first conductor layer and a second conductor layer, which are formed by removing a part of the multi-layer board around the cavity, are hierarchically formed. Then, the conductor layer on one side is used as a ground conductor, and the conductor layer on the other side is used as a signal conductor. In the mounted state of the circuit element, the ground conductor has an extremely large cross-sectional area, so that good grounding can be achieved. As a result, the impedance of the ground conductor can be lowered, and high-frequency and high-speed operation becomes possible.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面に基づいて説明
する。なお、本実施例の説明において、従来例と同一の
名称部分には同一符号を付し、その詳細な重複説明は省
略する。図１には本実施例の回路素子の実装構造が示さ
れている。Embodiments of the present invention will be described below with reference to the drawings. In the description of the present embodiment, the same reference numerals will be given to the same names as those in the conventional example, and detailed description thereof will be omitted. FIG. 1 shows a mounting structure of the circuit element of this embodiment.
【０００９】図１において、回路基板１としては内部に
導体層３を有する多層基板１が用いられ、この多層基板
１は下層基板４の上面に導体層３が形成され、この導体
層３の上側に上側基板５が積層され、その基板５の上側
に導体層10Ａ〜10Ｄが形成されている。この多層基板１
の所望位置には、キャビティ２が設けられている。この
キャビティ２内にトランジスタや電子部品等の半導体チ
ップの回路素子21が実装されており、キャビティ２の周
囲部には第１の導体層３と第２の導体層10Ａ〜10Ｄが階
層的に露出形成されている。前記第１の導体層３は全面
が接地導体15となり、第２の導体層10Ａ〜10Ｄは信号導
体としてパターン形成されている。そして、第１の導体
層３はボンディングワイヤ23によって回路素子21の各接
地端子16Ａ，18Ａ〜16Ｄ，18Ｄと接続されており、第２
の導体層10Ａ〜10Ｄは同様にボンディングワイヤ23によ
って回路素子21の各信号端子17Ａ〜17Ｄと接続されてい
る。In FIG. 1, a multi-layer substrate 1 having a conductor layer 3 inside is used as a circuit board 1. In this multi-layer substrate 1, a conductor layer 3 is formed on an upper surface of a lower layer substrate 4, and an upper side of the conductor layer 3 is formed. The upper substrate 5 is laminated on the substrate 5, and conductor layers 10A to 10D are formed on the upper side of the substrate 5. This multilayer board 1
A cavity 2 is provided at a desired position of. A circuit element 21 of a semiconductor chip such as a transistor or an electronic component is mounted in the cavity 2, and the first conductor layer 3 and the second conductor layers 10A to 10D are hierarchically exposed in the periphery of the cavity 2. Has been formed. The entire surface of the first conductor layer 3 serves as the ground conductor 15, and the second conductor layers 10A to 10D are patterned as signal conductors. The first conductor layer 3 is connected to the ground terminals 16A, 18A to 16D, 18D of the circuit element 21 by the bonding wire 23, and
Similarly, the conductor layers 10A to 10D are connected to the signal terminals 17A to 17D of the circuit element 21 by the bonding wires 23.
【００１０】次に、本実施例の回路素子の実装構造の作
製方法を図１に基づいて説明する。まず、内部に導体層
３を有する多層基板（実施例では２層基板）１の中央部
に四角形状のキャビティ２を形成する。この四角形状の
キャビティ２の周囲部の上層基板５の内側を取り除き、
キャビティ２の周囲部に下層基板４上の第１の導体層３
を露出させる。この露出した導体層３を接地導体15とし
て機能させる。また、多層基板１の上面のキャビティ２
の周囲部にパターニングにより第２の導体層10Ａ〜10Ｄ
を形成し、この導体層10Ａ〜10Ｄを信号導体14Ａ〜14Ｄ
として機能させる。Next, a method of manufacturing the circuit element mounting structure of this embodiment will be described with reference to FIG. First, a quadrangular cavity 2 is formed in the center of a multilayer substrate (a two-layer substrate in the embodiment) 1 having a conductor layer 3 inside. The inside of the upper layer substrate 5 around the rectangular cavity 2 is removed,
The first conductor layer 3 on the lower substrate 4 is provided around the cavity 2.
Expose. The exposed conductor layer 3 functions as the ground conductor 15. In addition, the cavity 2 on the upper surface of the multilayer substrate 1
Second conductor layers 10A to 10D by patterning around the periphery of the
And the conductor layers 10A to 10D are connected to the signal conductors 14A to 14D.
To function as.
【００１１】この多層基板１のキャビティ２内に回路素
子21を搭載し、回路素子21の各信号端子17Ａ〜17Ｄをボ
ンディングワイヤ23によって回路基板としての多層基板
１上の信号導体10Ａ〜10Ｄと接続し、回路素子21の各接
地端子16Ａ，18Ａ〜16Ｄ，18Ｄを同様にボンディングワ
イヤ23によって接地導体15としての第１の導体層３とそ
れぞれ接続して、回路素子21を回路基板１に実装する。The circuit element 21 is mounted in the cavity 2 of the multi-layer substrate 1, and the signal terminals 17A to 17D of the circuit element 21 are connected to the signal conductors 10A to 10D on the multi-layer substrate 1 as the circuit board by the bonding wires 23. Then, each ground terminal 16A, 18A to 16D, 18D of the circuit element 21 is similarly connected to the first conductor layer 3 as the ground conductor 15 by the bonding wire 23, and the circuit element 21 is mounted on the circuit board 1. .
【００１２】本実施例によれば、多層基板１の内側に接
地導体15として全面に第１の導体層３を設けたので、接
地導体15は断面積が大きいため、その抵抗値は小さくな
り、良好な接地が可能となる。これにより、接地導体の
低インピーダンス化が図れ、高周波、高速動作時おいて
も、回路性能の悪化の虞がない。According to this embodiment, since the first conductor layer 3 is provided on the entire surface as the ground conductor 15 inside the multi-layer substrate 1, the ground conductor 15 has a large cross-sectional area, so that its resistance value becomes small. Good grounding is possible. As a result, the impedance of the ground conductor can be lowered, and there is no fear that the circuit performance will deteriorate even during high frequency and high speed operation.
【００１３】なお、本発明は上記実施例に限定されるこ
とはなく、様々な実施の態様を採り得る。例えば、上記
実施例では、多層基板１に設けたキャビティ２の周囲部
の第１の導体層３を接地導体とし、パターニングにより
形成した第２の導体層10Ａ〜10Ｄを信号導体としたが、
第１の導体層３をパターニングして信号導体とし、上側
基板５上の導体層全面を接地導体としてもよい。The present invention is not limited to the above-mentioned embodiment, and various embodiments can be adopted. For example, in the above embodiment, the first conductor layer 3 around the cavity 2 provided in the multilayer substrate 1 is the ground conductor, and the second conductor layers 10A to 10D formed by patterning are the signal conductors.
The first conductor layer 3 may be patterned to be a signal conductor, and the entire conductor layer on the upper substrate 5 may be used as a ground conductor.
【００１４】また、上記実施例では、回路素子21として
トランジスタや電子部品等を用いたが、本発明は、これ
らの回路素子以外の素子の実装構造に適用することがで
きる。Further, in the above-mentioned embodiment, the transistor, the electronic component or the like is used as the circuit element 21, but the present invention can be applied to a mounting structure of elements other than these circuit elements.
【００１５】[0015]
【発明の効果】本発明は、多層基板の内部に第１の導体
層と第２の導体層を階層的に露出形成し一方側の導体層
を接地導体とする構成としたので、接地導体は断面積の
大きい低抵抗の導体層となり、良好な接地が図れる。こ
れにより、接地導体の低インピーダンス化が図れ、高周
波や高速動作が可能となる。According to the present invention, the first conductor layer and the second conductor layer are hierarchically exposed and formed on the inside of the multilayer substrate, and the conductor layer on one side is used as the ground conductor. A low resistance conductor layer with a large cross-sectional area and good grounding. As a result, the impedance of the ground conductor can be reduced, and high frequency and high speed operation can be performed.
【図１】本実施例の回路素子の実装構造の説明図であ
る。FIG. 1 is an explanatory diagram of a mounting structure of a circuit element of the present embodiment.
【図２】従来の回路素子の実装構造の説明図である。FIG. 2 is an explanatory diagram of a conventional mounting structure of a circuit element.
１ 多層基板 ２ キャビティ ３ 第１の導体層 10Ａ〜10Ｄ 第２の導体層 16Ａ〜16Ｄ，18Ａ〜18Ｄ 接地端子 17Ａ〜17Ｄ 信号端子 21 回路基板 23 ボンディングワイヤ 1 Multilayer Substrate 2 Cavity 3 First Conductor Layer 10A to 10D Second Conductor Layer 16A to 16D, 18A to 18D Ground Terminal 17A to 17D Signal Terminal 21 Circuit Board 23 Bonding Wire
Claims (1)
子の接地端子が回路基板の接地導体に、回路素子の信号
端子が回路基板の信号導体にそれぞれ接続されている回
路素子の実装構造において、前記回路基板は内部に１層
以上の導体層を有する多層基板により構成され、この多
層基板にはキャビティが設けられ、このキャビティ内に
回路素子が実装されており、キャビティの周囲部に第１
の導体層と第２の導体層が階層的に露出形成され、その
一方側の導体層を接地導体とし、他方側の導体層はパタ
ーン形成して信号導体としたことを特徴とする回路素子
の実装構造。1. A circuit element mounting structure, wherein a circuit element is mounted on a circuit board, a ground terminal of the circuit element is connected to a ground conductor of the circuit board, and a signal terminal of the circuit element is connected to a signal conductor of the circuit board. The circuit board is composed of a multi-layer board having one or more conductor layers inside, a cavity is provided in the multi-layer board, and a circuit element is mounted in the cavity.
Of the circuit element, wherein the conductor layer and the second conductor layer are hierarchically exposed and formed, the conductor layer on one side thereof is used as a ground conductor, and the conductor layer on the other side is patterned to be a signal conductor. Mounting structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5172531A JPH0778902A (en) | 1993-06-18 | 1993-06-18 | Circuit element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5172531A JPH0778902A (en) | 1993-06-18 | 1993-06-18 | Circuit element mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0778902A true JPH0778902A (en) | 1995-03-20 |
Family
ID=15943644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5172531A Pending JPH0778902A (en) | 1993-06-18 | 1993-06-18 | Circuit element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0778902A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009050843A1 (en) * | 2007-10-19 | 2009-04-23 | Advantest Corporation | Electronic device |
-
1993
- 1993-06-18 JP JP5172531A patent/JPH0778902A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009050843A1 (en) * | 2007-10-19 | 2009-04-23 | Advantest Corporation | Electronic device |
| JPWO2009050843A1 (en) * | 2007-10-19 | 2011-02-24 | 株式会社アドバンテスト | Electronic devices |
| US7947908B2 (en) | 2007-10-19 | 2011-05-24 | Advantest Corporation | Electronic device |
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