JPH077907B2 - OFFSET CANCEL CIRCUIT - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to an off-set cancel cell circuit for canceling off-set voltage generated due to deviation of center frequency of a transmitting station in a radio receiving apparatus for receiving a digital signal. In particular, when it is necessary to make the optimum reception possible in a short time including the synchronization periodic pattern of 1010 ... at the start of transmission, or multi-station transmission in which there are multiple transmitting stations transmitting the same information. The present invention relates to an offset cancel cell circuit used for reception in the system.

[Conventional technology]

An example of a signal detection circuit of a conventional radio receiving device for receiving a digital signal, that is, a conventional offset cancel cell circuit will be described with reference to FIG.

In the figure, IN indicates the input of the demodulated signal of the receiver, and OUT
Indicates the output.

In FIG. 3, a coupling capacitor 31 and a resistor 32 are used to cut a direct current component, and diodes 33 and 34 are used to perform an offset cancel cell. Here, the conduction voltage V _D of the diode is selected to be approximately the same as the amplitude of the signal at the input IN. And the coupling capacitor 31
Then, when the amplitude of the signal at the input IN is exceeded, one of the diodes 33, 34 becomes conductive and is limited to the conduction voltage V _{D or} less.

That is, when the center frequency of the transmitting station (not shown) and the local oscillation frequency of the receiving device are deviated from each other, a DC fluctuation corresponding to the frequency deviation occurs at the start of reception. This DC fluctuation is suppressed by the conduction of one of the diodes 33 and 34, and the optimum receivable state is reached in a short time.

Then, the demodulated signal of the receiver is a coupling capacitor.
After passing through 31, it is compared by the comparator 36. Further, this comparison output is fed back through the resistor 35 to reproduce the low frequency component lost by the coupling capacitor 31 and the resistor 32 on the input side.

[Problems to be solved by the invention]

In the above-mentioned conventional offset cell circuit, "variation" in the modulation sensitivity and demodulation sensitivity and a change due to environmental conditions pose a problem.

That is, when the amplitude of the signal at the input IN is different from the conduction voltage V _{D of the} diodes 33 and 34, the error rate is deteriorated accordingly.

For example, when the amplitude of the signal at the input IN is larger than the conduction voltage V _D , the diode loses the power of the signal component and S /
There was a problem that N deteriorated. On the contrary, when the amplitude of the signal is smaller than the conduction voltage V _D , there is a problem that the DC fluctuation cannot be suppressed forever because neither diode is conductive even if the DC component at the input of the comparator 36 is deviated. . This also causes a problem in reception in the multi-station transmission system.

That is, in the multi-station transmission system, the receiver that moves in the area where the radio waves of multiple transmitters reach is instantaneously most strongly received by the radio waves of different stations, and the direct current is output to the demodulation output according to the offset frequency of each transmitter station. There are fluctuations. At this time, if not only the transmission frequency of each transmitting station but also the modulation sensitivity varies, the optimum receiving cannot be performed for a certain transmitting station even after a long time, and the error rate characteristic remains deteriorated. There was a problem.

[Means for solving problems]

The offset cancel cell circuit of the present invention includes a comparator for comparing the voltage of a received demodulation signal with a reference voltage stored in a capacitor, and a reference voltage for inputting at least the voltage of the demodulation signal to control charging and discharging of the capacitor. Generating means, extracting means for sampling the output of the comparator at the center of the bit, coincidence detecting means for detecting whether or not the output of the extracting means coincides with the previous bit for each bit, and non-coincidence detection of the coincidence detecting means. When the output of the coincidence detecting means indicates a continuation of the disagreement state for a long time by comparing the output of the time constant means with a predetermined value, which sometimes charges slowly and discharges rapidly at the time of coincidence detection, Control means for controlling the reference voltage generating means so that the charging / discharging time of the capacitor is short and the charging / discharging time is long when the detection outputs show coincidence. In which the provided.

[Action]

In the present invention, the reference voltage of the comparator is determined irrespective of the amplitude of the input signal, and optimum reception is possible in a short time.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an offset cancel cell circuit according to the present invention.

In the figure, reference numeral 1 denotes a capacitor for storing a reference voltage, which is configured to be input to a comparator 2 for comparing the received demodulated signal with the reference voltage stored in the capacitor 1. Reference numeral 3 is a reference voltage generating means for generating a reference voltage, which is composed of resistors 4, 5 and 6 and analog switches 7 and 8 and whose output is supplied to the capacitor 1 as a comparison reference voltage Vc.

Reference numeral 9 is an extraction means for sampling the output x ₂ of the comparator ₂ at the center of the bit by the clock CLK, which is constituted by a flip-flop circuit. Reference numeral 10 is a judgment means which receives the output of the extraction means 9 as an input and judges whether or not the pattern does not include a low-frequency component. The judgment means 10 determines whether or not it coincides with the preceding bit for each bit. Match detection means to detect
11, a time constant circuit 12 that charges and discharges the output of the coincidence detection circuit 11, and a control signal generation circuit 13 that compares the output of the time constant means 12 with a comparison reference voltage Vc to generate a control signal. . The coincidence detecting means 11 is composed of a flip-flop circuit 14 and an exclusive logic circuit 15, the time constant means 12 is composed of resistors 16 and 18, a diode 17 and a capacitor 19, and a control signal generating circuit 13 Is composed of a comparator 20 and an inverter 21.

Then, the output of the extraction means 9 is input to the determination means 10, and when it is determined that the low frequency component is not included, the response speed of the output of the reference voltage generation means 3 is controlled to be increased. ing.

IN indicates the input of the demodulated signal of the receiver, and R DATA indicates the extracted output.

The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG.

FIG. 2 is a time chart used to explain the operation of FIG.
(A) shows the input of the comparator 2, (b) the output x ₂ of the comparator ₂ , (c) the clock CLK, (d) the extracted output R DATA (= x ₉ ), ( e) is the output of the match detection means 11
x ₁₁ and (f) show the output x ₁₂ of the time constant means 12, and (g) shows the control output (judgment output) x ₁₃ which is the output of the decision means 10.

First, the demodulated signal of the receiver is input from the input IN and is compared with the reference voltage stored in the capacitor 1 in the comparator 2. Here, the voltage of the capacitor 1 is given by the reference voltage generating means 3.

Then, the reference voltage generating means 3 supplies a current to the capacitor 1 so that the voltage of the capacitor 1 becomes the average voltage of the input IN. This amount of current is controlled by the received signal pattern. For that purpose, the extraction means 9 and the judgment means 10 are used.

The extracting means 9 is composed of the flip-flop circuit as described above, and extracts the output x ₂ of the comparator ₂ at the center of the bit by the clock CLK. Further, the coincidence detecting means 11 in the judging means 10 delays the output x ₉ of the extracting means ₉ by 1 bit by using the flip-flop circuit 14, and further, the delayed output x ₁₄ is exclusive with the output x _{9 of the} extracting means 9. input to the OR circuit 15, the delayed output x ₁₄ and the output x ₉ outputs "1" when the mismatch, if they match is outputting "0". Output x ₁₁ of the coincidence detection means 11 constant means time 1
Are input to the 2, when the x ₁₁ = "1" capacitor 19 is charged voltage up, voltage capacitor 19 discharges when the x ₁₁ = "0" decreases.

Here, when the capacitor 19 is charged, only the current flows through the resistor 18 and the rise of the voltage is slow, but at the time of discharging, the current flows through both the series circuit of the resistor 16 and the diode 17 and the resistor 18, so that the fall of the voltage is fast.

The output x ₁₂ of the time constant means ₁₂ is the control signal generating circuit 13
At, it is compared against a reference voltage Vc by a comparator 20 to obtain a control signal x ₁₃ . In the embodiment shown in FIG. 1, not only the control signal x ₁₃ but also the control signal x ₁₃ is inverted by the inverter 21 and Is used to control the reference voltage generating means 3.

Here, the reference voltage generating means 3 has a first route for supplying the input IN to the capacitor 1 via the resistor 4 and the input IN
Is supplied to the capacitor 1 through the resistor 5 and the analog switch 7, and a third route for supplying the inverted output of the flip-flop circuit constituting the extracting means 9 to the capacitor 1 through the resistor 6 and the analog switch 8. There is.

Then, the analog switches 7 and 8 are To the following.

First, x ₁₃ = "1" , The analog switch 7 is on, the analog switch 8 is off, and the resistor 4 is placed between the input IN and the capacitor 1.
Since a current flows through both the capacitor and the resistor 5, the capacitor 1
The charging and discharging of is performed in a short time. That is, at this time, the average voltage of the input IN is rapidly stored in the capacitor 1.

In the section from time t _{1 to} t _{3 in} FIG. 2, the judgment output shown in (g) is x ₁₃ = “1”. In this section, the reference voltage vc of the comparator input shown in (a) is trying to approach the average value of the voltage of the input IN by “fast change”.

Next x ₁₃ = "0" In the section of, the analog switch 7 is turned off, the analog switch 8 is turned on, and a current flows through the resistors 4 and 6.

In this case, between the input IN and the capacitor 1, since the capacitor 1 is charged and discharged only by the current of the resistor 4, x ₁₃
= "1" The charging / discharging time becomes longer than that in the above case. Further, in this section, the inverted output of the flip-flop circuit of the extraction means 9 is supplied via the resistor 6. The current supplied to the capacitor 1 via the resistor 6 uses the inverted output of the flip-flop circuit, so when the high level continues to the input IN, the capacitor 1 goes to the low level direction and vice versa. When the low level continues, the capacitor 1 tries to change to the high level. Therefore, when the constant voltage condition continues at the input IN, the comparison reference voltage
Since vc becomes the same value as the voltage of input IN, comparator 2
Is prevented from being mistakenly inverted. For example, when the high level state of the input IN continues, a constant voltage is supplied at a low level as feedback from the flip-flop circuit forming the extraction means 9, and the comparison reference voltage vc is set to a certain potential difference with respect to the input IN. The presence of this prevents erroneous inversion of the comparator 2.

In FIG. 2, the judgment output shown in (g) is x ₁₃ = “0” before the time t ₁ and after the time t 3. This section is the reference voltage vc of the comparator input shown in (a).
Is a "slow change" trying to approach the average value of the input IN voltage.

Next, in FIG. 2, the signals from time t ₀ to 1010 ... Are received. At this time, an offset voltage of ΔV is generated in the demodulation output according to the difference between the center frequency of the transmitting station and the local oscillation frequency of the receiving device. The signals 1010 (periodic signals) are also used for phase synchronization of clock reproduction, but in the embodiment shown in FIG. 1, they are used for control to obtain the comparative reference voltage Vc.

That is, the reference voltage vc
Yuki with the optimum voltage, then when (time t ₂ after) the information signal is input, must be close to the average of the values of the input IN of the value of the comparison reference voltage vc to be compared comparator 2 is correctly There is. Therefore, when the signal of 1010 ... Is received from the time point t _0, the output of the coincidence detecting means 11 becomes x ₁₁ = "1" because every bit at this time is different from the previous bit. Then, the time constant means 12 charges this and rises, and when the output of the time constant means 12 becomes x ₁₂ > Vc, the judgment output (control output)
As x ₁₃ = “1”.

As described with reference to FIG. _1, from this time t ₁ , the analog switch 7 is turned on and the analog switch 8 is turned off, so that the response of the comparison reference voltage Vc becomes fast and the input is rapidly performed.
It approaches the average voltage of IN.

Next, when the input IN becomes a signal (periodic signal) of 1010 ... At time t ₂ , the output x ₁₂ of the time constant means 12 rises rapidly, and x ₁₂ = Vc in a short time, and the control output (Judgment output) x ₁₃ = “0” is obtained.

The analog switch 7 is turned off from the time point t _3, analog switch 8 is turned on, the comparison reference voltage Vc represents the mean voltage of the input IN at a very slow changes, the optimum receiving state.

As is clear from the above description, the judgment means 10 is
It is configured to judge that the periodic pattern of 10 ... Is a pattern that does not include a low frequency component, and the judgment means 10
As a time constant that uses the coincidence detection means 11 for detecting whether each bit coincides with the previous bit, according to the output of the coincidence detection means 11, slowly charges at the time of disagreement and discharges rapidly at the time of coincidence. It is configured to obtain a judgment result by inputting it to the means 12 and comparing the output of the time constant means 12 with a predetermined value.

〔The invention's effect〕

As described above, according to the present invention, the comparison reference voltage of the comparator is determined irrespective of the amplitude of the input signal, and optimum reception is possible in a short time. Since it is not affected by variations in temperature, changes in temperature, and changes over time, the practical effect is extremely large.

Further, the present invention is effective not only for receiving a burst signal including a periodic signal at the start of transmission but also for applying it to a receiver that moves within an area where radio waves reach by multi-station transmission.

Further, in the case of the present invention, even if radio waves from different stations are received, the information signal is rapidly and automatically adjusted to the optimum reception state every time the periodic pattern of 1010 ... It is extremely effective in that it can be received normally.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an offset cancel cell circuit according to the present invention, FIG. 2 is a time chart used to explain the operation of FIG. 1, and FIG. 3 is a structure showing an example of a conventional offset cancel cell circuit. It is a figure. 1 ... Capacitor, 2 ... Comparator, 3 ... Reference voltage generating means, 9 ... Extracting means, 10 ... Judging means, 11 ... Match detection means, 12 ... Time constant means, 13 ... Control signal Generator circuit.

Claims (1)

[Claims] 1. A comparator for comparing the voltage of a received demodulation signal with a reference voltage stored in a capacitor, and a reference voltage generating means for inputting at least the voltage of the demodulation signal to control charging and discharging of the capacitor. Extracting means for sampling the output of the comparator at the center of the bit, coincidence detecting means for detecting whether or not the output of the extracting means coincides with the previous bit for each bit, and slow when the disagreement of the coincidence detecting means is detected When the output of the coincidence detecting means indicates the continuation of the non-coincidence state for a long time by comparing the output of the time constant means with a predetermined value which is discharged at the time of coincidence detection while being charged to A control means for controlling the reference voltage generating means so that the charging / discharging time of the capacitor is short and the charging / discharging time is long when the detection outputs show coincidence. Offset cancel circuit comprising the and.