JPH0779164B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a high power, high speed and high frequency switching element is realized monolithically.

[Conventional technology]

As a conventional high power, high frequency, high frequency switching element having a low on-state resistance, there is one as shown in FIG. 3, for example.

FIG. 3 is a sectional view showing the structure of a conventional monolithically constructed conductivity modulation metal oxide semiconductor field effect transistor (hereinafter referred to as CAT element). In this figure, CA
The structure of the T element is n ⁺ of the conventional metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET) made by double diffusion.
The semiconductor substrate to be the drain region is replaced with the n ⁺ semiconductor substrate 7 to be the drain / collector region.
More specifically, on the upper part of the p ^{+ type} semiconductor substrate 7,
For example, the drain drift layer 6 made of an n-type epitaxial layer is formed. Then, the drain drift layer 6
A plurality of p-type base regions 5 are formed on the upper surface of the n-type source regions 5 with a space therebetween, and two n ^{+ -type} source / emitter regions 4 are spaced from each other on the upper surface of the p-type base region 5. Is formed. The surface of the drain drift layer 6 between the p-type base regions 5 and the p-type base region 5 in contact with the drain drift layer 6 to the n ^{+ -type} source / emitter region 4
A gate oxide film 3 made of, for example, silicon dioxide is formed on the surface extending to the peripheral portion. Gate oxide film 3
A gate electrode 2 made of a metal is formed in the interior of the gate electrode 2, and the gate electrode 2 extends up to the n ^{+ type} source / emitter region 4. Further, the surface of the central portion of the p-type base region 5 not covered with the gate oxide film 3, the surface of the n ^{+ -type} source / emitter region 4 and the surface of the gate oxide film 3 are source / source
The emitter electrode 1 is formed. Here, the n ^{+ type} source / emitter region 4, the p type base region 5, and the drain drift layer 6 form an npn transistor parasitic on the MOSFET, and the p type base region 5, the drain drift layer 6, and the p ^{+ type} semiconductor are formed. The substrate 7 constitutes a pnp transistor parasitic on the CAT element. A drain / collector electrode 8 is formed below the p ^{+ type} semiconductor substrate 7. G is the gate electrode terminal, S / E is the source / emitter electrode terminal, D / C is the drain /
Collector electrode terminal, D ₁ is a diode, D ₂ is a pin diode, and R _s is a parasitic resistance.

An equivalent circuit of such a CAT element should be a MOSFET and a pin diode D ₂ connected in series in terms of an ideal current flow. However, in practice, as shown in FIG. And a thyristor composed of an npn transistor and a pnp transistor that are parasitic on this.

Next, the operation of this CAT element will be described.

The gate electrode terminal G and the source / emitter electrode terminal S / E are short-circuited to connect the drain / collector electrode terminal D / C and the source / emitter electrode terminal S / E to the drain / collector electrode terminal D / C.
When a voltage having a reverse bias is applied, the pin diode D ₂ is reverse biased and the reverse bias blocking characteristic appears. Drain / collector electrode terminal D / C and source /
Drain / collector electrode terminal D between emitter electrode terminal S / E
When a voltage that is forward-biased when viewed from / C is applied, the diode D ₁ is reverse-biased and the reverse-bias blocking characteristic appears. In this state, when a voltage higher than the threshold voltage of the MOSFET is applied between the gate electrode terminal G and the source / emitter electrode terminal S / E, a channel is formed in the p-type base region 5.
At the same time that the MOSFET is ready to operate, pin diode D
₂ through the p ^{+ type} semiconductor substrate 7 to the drain drift layer 6
The holes are injected to increase the conductivity of the drain drift layer 6, and the CAT element is turned off with a low on-resistance.

In order to turn off the CAT element, the gate electrode terminal G and the source / emitter electrode terminal S / E are short-circuited so that the voltage applied between these terminals is equal to or lower than the threshold voltage of the MOSFET, and the gate electrode The inversion region on the surface of the p-type base region 5 below 2 is restored to stop the supply of electrons to the drain drift layer 6. At the start of turn-off, a large amount of electrons injected until then are concentrated in the drain drift layer 6, but these electrons are injected into the p ^{+ -type} semiconductor substrate 7, and a current due to holes corresponding to that is p. Flow into the shaped base region 5. If such a state continues, the degree of concentration of electrons in the drain drift layer 6 decreases, and the remaining holes and electrons cancel each other by recombination.
The CAT element turns off.

[Problems to be solved by the invention]

In the conventional CAT element as described above, the direct current amplification factor h _FE of each of the transistor and the pnp transistor is
Is larger than 1 and the voltage drop V _s at the resistance R _s of the p-type base region 5 of the npn transistor due to the Hall current is V _s.
When the voltage is more than 0.4-0.8V at 300 ° K, the npn transistor and the pnp transistor in the thyristor region feedback each other at high current density at turn-on, so the thyristor region latches and the gate control capability of the CAT element increases. It's gone and it's hard to turn it off. Therefore, in order to operate the CAT element normally, it is necessary to use it below the current level at which it latches, but since the current level at which the thyristor region latches is low,
There is a problem that the gate control range is narrow.

In order to solve this problem, the CAT with the structure shown in FIG.
The element has been announced. In FIG. 5, a p ^{+ type} base central region having a high impurity concentration is provided in the central part of the p type base region 5.
50 is formed, and the n ^{+ type} buffer layer 9 is inserted between the drain drift layer 6 and the p ^{+ type} semiconductor substrate 7. this
The equivalent circuit of the CAT element is the same as the circuit shown in FIG.

In this CAT element, the direct current amplification factor h _FE of the parasitic npn transistor is lowered by the p ^{+ type} base central region 50, and holes are injected from the p ^{+ type} semiconductor substrate 7 to the drain drift layer 6 by the n ^{+ type} buffer layer 9. By suppressing and reducing the DC current gain h _FE of the parasitic pnp transistor, the CAT element is less likely to latch at turn-on. That is, although the level of the latching current was raised as compared with the CAT element of FIG. 3, the gate control range could not be made sufficiently wide.

In order to pass a sufficient turn-on main current, the voltage applied between the gate electrode terminal G and the source / emitter electrode terminal S / E is about 10 to 15 V (this value is the gate oxidation formed by the conventional design standard). Control circuit (μ-computer, TTL, CMOS)
There is a problem that the circuit becomes complicated because it is not possible to use only the 5V power supply system for the power supply and a separate power supply of 10 to 15V is required.

The present invention has been made to solve the above problems, and it is a semiconductor capable of increasing the latching current level of the thyristor region parasitic in the MOSFET to extend the gate control range and driving at a low voltage (5V). The purpose is to obtain the device.

[Means for solving problems]

In the semiconductor device according to the present invention, a region corresponding to the lower portion of the source / emitter region in the semiconductor substrate of the first conductivity type and the high impurity concentration, which is the drain / collector region of the CAT element, has the second conductivity type and the high impurity concentration. It is a drain / collector layer of high concentration.

[Action]

In the present invention, holes are partially injected into the drain drift layer from the semiconductor substrate of the first conductivity type which is the drain / collector region and has a high impurity concentration, and the holes injected are second conductivity when turned off. Form to drain to the high impurity concentration drain / collector layer.

〔Example〕

FIG. 1 is a sectional view showing the structure of a CAT element which is an embodiment of a semiconductor device of the present invention which is monolithically structured.

In FIG. 1, the same reference numerals as in FIG. 5 indicate the same parts,
Reference numeral 20 denotes an electrode, which has a shape such that the distance from the p-type base region 5 is smaller than the distance from the drain drift layer 6. 30
Is a gate oxide film covering the electrode 20, and the thickness between the electrode 20 and the p-type base region 5 is thin. 70 drain / collector region to become p ⁺ type semiconductor substrate, the region corresponding to the lower portion of the n ⁺ -type source / emitter region 4 of the n ⁺ -type drain /
A collector layer 10 is formed.

In FIG. 1, n ^{+ type} source / emitter region 4, p type base region 5, p ^{+ type} base central region 50 and drain drift layer
6, n ^{+ type} drain / collector layer 10 is npn parasitic on MOSFET
A p-type base region 5, p ^{+ -type} base central region 50, drain drift layer 6, n ⁺ -type drain / collector layer 10a and p ^{+ -type} semiconductor substrate 70 form a pnp transistor parasitic on the CAT element. , These two transistors form a parasitic thyristor region.

Next, the operation of this CAT element will be described.

First, in the state in which a forward bias voltage when viewed from the drain / collector electrode terminal D / C is applied between the drain / collector electrode terminal D / C and the source / emitter electrode terminal S / E, the gate electrode terminal G and the source / source electrode are connected. If a voltage higher than the gate threshold voltage is applied between the emitter electrode terminals S / E, the CAT element turns on. Here, since the gate oxide film 30 on the p-type base region 5 where the channel is induced is thin and the drain drift layer 6 is thick, the gate threshold voltage is, for example, 4 to 5V. Is low.

Further, since the n ⁺ -type drain / collector layer 10 is partially formed in the p ^{+ -type} semiconductor substrate 70 below each n ^{+ -type} source / emitter region 4, the p ^{+ -type} semiconductor substrate 70 (p of the pnp transistor is Holes are partially injected into the drain drift layer 6 from the ( ⁺ emitter) and are suppressed by the n ^{+ type} buffer layer 9. For this reason, the transport efficiency of the base region of the parasitic pnp transistor is reduced, and its DC current amplification factor h _FE is
Significantly lower than the device. On the other hand, the holes injected from the p ^{+ -type} semiconductor substrate 70 flow upward straight in a narrowed state in the drain drift layer 6, and most of the holes reach the p ^{+ -type} base central region 50, and the remaining The holes reach the p-type base region 5 and escape to the source / emitter electrode terminal S / E. Therefore, the p-type base region 5 due to the hole current
Also, the voltage drop V _s at the resistance R _s of the p-type base central region 50 is smaller than that of the conventional CAT element.

As described above, in this CAT element, the DC current amplification factor h _FE of the parasitic pnp transistor is lowered, and the voltage drop V _{s in} the p-type base region 5 and the p ^{+ -type} base central region 50 of the parasitic npn transistor is reduced. Therefore, the latching current level is higher than that of the conventional CAT element. Therefore, turn-off of the CAT element is facilitated, high-speed high-frequency switching characteristics are improved, and the CAT element operates as an ideal CAT element as shown in the equivalent circuit diagram of FIG.

Also, with this CAT element, the current level for latching rises as described above, so the gate control range is wider than with the conventional CAT element, and it is possible to increase the current density of the CAT element accordingly, and reduce the chip size. It is possible to reduce the size and cost of CAT elements.

Regarding the conductivity modulation of the drain drift layer 6, it is effective to carry out the conductivity modulation effect just under the center of the p ^{+ type} base central region 50 and the gate oxide film 30, and the conductivity modulation effect equivalent to that of the conventional CAT element is obtained. Can be obtained, and the on-voltage can be lowered.

Further, in the conventional CAT element, the p ⁺ -type drain / collector layer 7 (FIG. 3) is formed over the entire drain drift layer 6, so that at the time of turn-off, holes accumulated in the drain drift layer 6 at the time of turn-on. Was blocked by the p ⁺ -type drain / collector layer 7 and hard to escape, but in this CAT element, holes were blocked only in a narrow area at the bottom of the p ^{+ -type} semiconductor substrate 70, and the n ⁺ -type drain / It can easily escape to the collector layer 10, and this also facilitates the turn-off operation of the CAT element and improves the high-speed and high-frequency switching characteristics.

Although the present invention can be applied to a p-type CAT element in which the conductivity types of the layers and regions are opposite, the method of diffusing the n ⁺ -type drain / collector region in the p ^{+ -type} semiconductor substrate 70 is relatively easy. Is.

〔The invention's effect〕

As described above, the present invention provides a drain / catalyst element.
Since the region corresponding to the lower part of the source / emitter region in the semiconductor substrate of the first conductivity type and the high impurity concentration which becomes the collector region is the drain / collector layer of the second conductivity type and the high impurity concentration, the parasitic npn transistor There is an effect that the current level for latching of the thyristor composed of the pnp transistor and the pnp transistor is increased, and the gate control range can be expanded.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a structure of a CAT element which is an embodiment of a semiconductor device of the present invention, which is monolithically constructed, and FIG.
1 is an equivalent circuit diagram of the CAT element shown in FIG. 1, FIG. 3 is a sectional view showing the structure of a conventional CAT element monolithically configured, and FIG. 4 is an equivalent circuit diagram of the conventional CAT element. The figure is a cross-sectional view showing the structure of another conventional CAT element configured monolithically. In the figure, 1 is a source / emitter electrode, 4 is an n ^{+ type} source / emitter region, 5 is a p type base region, 6 is a drain drift layer, 8 is a drain / collector electrode, 9 is an n ^{+ type} buffer layer, and 10 is An n ⁺ -type drain / collector layer, 20 is a gate electrode, 30 is a gate oxide film, 50 is a p ^{+ -type} base central region, and 70 is a p ^{+ -type} semiconductor substrate. The same reference numerals in each drawing indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type having a high impurity concentration, which serves as a drain / collector region, a drain buffer layer of a second conductivity type having a high impurity concentration, which is formed on the semiconductor substrate, and this drain buffer layer. A second conductivity type drain drift layer formed on the upper surface of the drain drift layer; a plurality of first conductivity type base areas formed on the upper surface of the drain drift layer at intervals; A source / emitter region of the second conductivity type and a high impurity concentration, which is formed on the upper surface of the region at a distance, a surface of a drain drift layer between the base regions, and a source / source region from the base region in contact with the drain drift layer. A gate oxide film formed on the surface extending to the peripheral portion of the emitter region and having a gate electrode therein, and the base region not covered with the gate oxide film. Furthermore, the source / emitter electrode formed on the source / emitter regions and on the gate oxide film,
In a conductivity modulation metal oxide semiconductor field effect transistor comprising a drain / collector electrode formed under the semiconductor substrate, a region corresponding to a lower portion of the source / emitter region in the semiconductor substrate is of a second conductivity type. A semiconductor device having a drain / collector layer having an impurity concentration. 2. A semiconductor device according to claim 1, wherein the distance between the gate electrode and the base region is made smaller than the distance between the gate electrode and the drain drift layer.