JPH077931B2 - 2-wire data transmission system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an analog current signal data transmission system, and more particularly to a data transmission system that minimizes delay due to time division multiplexing.

[Conventional technology]

In the case of transmitting a pulse amplitude modulated (PAM) current signal bidirectionally, for example, a method of time division multiplexing the signal may be used. That is, a division slot is provided on the time axis, and an uplink signal slot and a downlink signal slot are allocated between two stations that perform communication.

[Problems to be Solved by the Invention] However, according to the conventional time division multiplexing method, in addition to data information (uplink and downlink multiplexed information), pulse sampling clock information and synchronization information for multiplexing are provided. It is necessary to transmit them together, and a total of three types of information must be transmitted. Therefore, basically three systems of information transmission lines are required. On the other hand, in order to reduce the required transmission path, a method of encoding the synchronization information and putting it on the data information has been considered and used. A system transmission line is required. Therefore, in the conventional bidirectional transmission, at least a 4-wire type transmission line or a 3-wire type transmission line is required to transmit data in real time without delay, and it is impossible with the 2-line type transmission line.

Further, this problem also exists when multiplexing two or more pieces of data information in unidirectional transmission, and two or more pieces of data information cannot be transmitted by the two-wire transmission line.

[Means for solving problems]

The two-wire data transmission system of the present invention has been made in view of the above problems, and supplies a drive current to the main station (4) on the controller side and the actuator (1) and detects it from the transmitter (2). Slave station for inputting signals (3)
Is connected by a 2-wire signal transmission line (13), and a drive control signal that changes between 4 and 20 mA is transmitted from the master station to the slave station via the 2-wire signal transmission line. To 2
A two-wire data transmission method for transmitting a detection control signal that varies between 4 and 20 mA through the two-wire signal transmission path, wherein the two-wire signal transmission path includes first ([0]) and second ( [1]), third
The time slot of ([3]) is divided into a state in which the time slot is sequentially repeated to be multiplexed, and the 2-wire type signal transmission line is set to the base level (zero level) in the first time slot and is used as a synchronization signal. In the second time slot, the two-wire type signal transmission line is set to the level of the drive control signal, and in the third time slot, the two-line type signal transmission line is set to the level of the detection control signal.

[Action]

Since the zero current that is not included in the data is assigned to the synchronization signal, the synchronization signal and the data are completely identified, and the synchronization signal also serves as clock information.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of the present invention. The actuator 1 is a conventional actuator that drives a DC signal of 4 to 20 mA as an input signal. The transmitter 2 is a conventional transmitting means that outputs a DC signal of 4 to 20 mA. The slave station 3 of the multiplex transmission means 6 is provided near the location where the actuator 1 and the transmitter 2 are provided. on the other hand,
A main station 5 of the multiplex transmission means 6 is provided near the PID controller 4 which is a controller. Originally, the PID controller 4 connects the actuator 1 to its current output terminal to give a DC signal of 4 to 20 mA, and connects the transmitter 2 to its current input terminal to input a DC signal of 4 to 20 mA. As a result, the feedback control controller gives the actuator 1 a control signal according to the data while inputting the data from the transmitter 2. Here, the input / output terminal of the feedback control controller is via the multiplex transmission means 6. 1 and transmitter 2.

The main station 4 of the multiplex transmission means 6 is composed of a multiplex signal transmission circuit 7, a multiplex signal reception circuit 8 and a synchronization circuit 9.

The multiplex signal transmission circuit 7 includes a DC power supply 7a, an I / V converter 7b, and a V / I converter 7c with a gate circuit. I / V converter
7b is a means for converting a current signal of 4 to 20 mA into a voltage signal of 1 to 5 V, and its concrete configuration is shown in FIG. In FIG. 2, 21 is an input terminal, 22 is an output terminal, and 23 and 24 are operational amplifiers. The V / I converter 7c with a gate circuit, according to the first sampling clock S1 from the synchronization circuit 9,
This is means for discretely converting a voltage signal into a current signal at a constant cycle, and its concrete configuration is shown in FIG. In FIG. 3, 31 is an input terminal, 32 and 32 'are output terminals, 33 is a sampling clock input terminal, 34 is an operational amplifier, 35 is a photocoupler, and 36 is a switching transistor.

The multiplex signal receiving circuit 8 is composed of an I / V converter 8a, a sample hold circuit 8b, a V / I converter 8c and a DC power supply 8d. The I / V converter 8a is the same as the I / V converter 7b. The sample hold circuit 8b is a means for holding the input voltage until the next clock input at the timing of the second sampling clock S2 from the synchronizing circuit 9, and its concrete configuration is shown in FIG. In the figure, 41 is an input terminal, 42 is an output terminal, 43 is a sampling clock input terminal, and 44 is an analog switch, which performs sampling and holding according to the input state (high or low) of the sampling clock input terminal 43. The V / I converter 8c is means for converting a voltage signal of 1 to 5 V into a current signal of 4 to 20 mA, and a specific example is shown in FIG. This configuration has the gate circuit shown in FIG.
The V / I converter 7c has a structure in which the gate circuit section by the photocoupler 35 is removed, and 51 is an input terminal, 52 and 52 'are output terminals, 53 is an operational amplifier, and 54 is a switching transistor.

The synchronization circuit 9 is composed of a clock pulse oscillator 9a, a ring counter 9b, and a synchronization converter 9c. The ring counter 9b divides the clock pulse from the oscillator 9a to generate the sampling clocks S1 and S2 and the synchronous converter 9c described above.
FIG. 6 shows a concrete example of the means for producing the synchronizing pulse S0 to be given to Connect three JK flip-flop circuits and some logic elements as shown in the figure. Terminal 61 is a clock signal input terminal and terminals 62 to 64 are synchronous pulse S respectively.
By setting 0 and the output terminals of the sampling clocks S1 and S2, the operation is performed as shown in the timing chart of FIG. The terminal 65 is a reset input terminal for making an initial setting at power-on. In FIG.
(A) is a clock pulse output from the oscillator 9a, (b) is a synchronizing pulse S0 output from a terminal 62, (c) is a sampling clock S1 output from a terminal 63, (d) is a terminal 64.
Sampling clock S2 output from each is shown.

The synchronous converter 9c is a means for converting the synchronizing pulse S0 as a voltage value into a current value, specifically, a means for setting the output current when the synchronizing pulse S0 is at a "low" level to zero, that is, a base level. . FIG. 8 shows a specific configuration of the synchronous converter 9c, which is composed of a comparator 81 and a photocoupler 82, which inputs a synchronous pulse S0 from a terminal 83,
Output from terminals 84 and 84 '.

In the main station 4 thus configured, the output terminal of the V / I converter 7c, the input terminal of the I / V converter 8a and the output terminal of the synchronous converter 9c are connected in series to the 2-wire signal transmission line 13. It is connected. A diode 14 is connected between the two output terminals of the V / I converter 7c of the multiple signal transmission circuit 7 as shown in the figure. The input terminal of the I / V converter 7b is connected to the output terminal of the PID controller 5, and the output terminal of the V / I converter 8c is connected to the input terminal of the PID controller 5.

Next, the configuration of the slave station 3 will be described. The basic configuration of the slave station 3 is almost the same as that of the master station 4, and the multiple signal receiving circuit 10,
The multi-signal transmission circuit 11 and the synchronization circuit 12 are provided.
The configuration of the multiplex signal receiving circuit 10 is the same as that of the multiplex signal receiving circuit 8 on the main station 4 side, and the I / V converter 10a, the sample hold circuit 10b, the V / I converter 10c, and the DC power supply 10d are respectively multiplexed. It corresponds to the I / V converter 8a, the sample hold circuit 8b, the V / I converter 8c and the DC power supply 8d of the signal receiving circuit 8. Similarly, the multiplex signal transmission circuit 11 has the same configuration as the multiplex signal transmission circuit 7 of the master station 4.

The synchronization circuit 12 has a configuration slightly different from that of the synchronization circuit 9 of the main station 4, and includes an oscillator 12a, a frequency divider 12b, and a ring counter 12.
c and a sync detector 12d. FIG. 10 is a timing chart showing the operation of the synchronizing circuit 12, where FIG. 10A is a reference sampling pulse output from the frequency divider 12b, and FIG. 10B is a synchronizing pulse S detected by the synchronization detector 12d.
0 ', (c) and (d) of FIG. 3 are sampling clocks S1', S2 'produced by the ring counter 12c, respectively. The reference sampling pulse shown in FIG. 9 (a) is formed by dividing the clock of n times the frequency from the oscillator 12a with reference to the falling edge of the synchronizing pulse S0 'shown in FIG. ing. FIG. 9 shows a synchronization detector 12
The specific example of d is shown, which is composed of a photocoupler 91 and a comparator 92, in which terminals 93 and 93 'are current input terminals and terminal 94 is an output terminal.

In the slave station 3 thus configured, the input terminal of the I / V converter 10a, the output terminal of the V / I converter 11c and the input terminal of the synchronization detector 12d are connected in series to the two-wire signal transmission line 13. ing. A diode 15 is connected between the two output terminals of the V / I converter 11c of the multiplex signal transmission circuit 11 as shown in the figure. The actuator 1 is connected to the output terminal of the V / I converter 10c, and the transmitter 2 is connected to the input terminal of the I / V converter 11b.

Next, the overall operation of the present embodiment configured as described above will be described.
This will be described with reference to FIG.

The current output terminal of the PID controller 5 outputs a current signal α1 whose value linearly decreases from 20 mA to 4 mA as shown in FIG. As shown in b), it is assumed that a current signal α2 whose value linearly increases from 4 mA to 20 mA is output. The current output of the PID controller 5 is input to the multiple signal transmission circuit 7 of the main station 4 and converted into a voltage signal that linearly drops from 5V to 1V in the I / V converter 7b. Similarly, the current output of the transmitter 2 is input to the multiple signal transmission circuit 11 of the slave station 3, and the I / V converter 11 (b) outputs 1V to 5V.
It is converted into a voltage signal that rises linearly.

On the other hand, in the synchronizing circuit 9 on the main station 4 side, the synchronizing pulse S0 and the sampling pulses S1 and S2 are generated, and these pulses cause the two-wire type signal transmission line 13 to output the time as shown in FIG. 11 (c). Divided into slots.

That is, the two-wire signal transmission line 13 becomes the base level at the time of the synchronization slot “0” by the synchronization pulse S0 on the side of the main station 4, and the signal α1 is changed to the two-wire signal only in the section of the slot “1” by the sampling pulse S1. It is sent to the transmission line 13. On the side of the main station 4, the signal input to the multiplex signal receiving circuit 8 at the time of slot "2" is sampled by the sampling pulse S2. The slave station 3 side detects the base level of the two-wire signal transmission line 13, and based on this, the slave station 3 side synchronization pulse S0 ′ and sampling pulse S
Create 1 ', S2'. Therefore, the synchronization pulse S0 'and the sampling pulses S1', S2 'have the same timing as the synchronization pulse S0 and the sampling pulses S1, S2 on the main station 4 side, respectively. The multiple signal receiving circuit 10 of the slave station 3 samples and holds the current signal on the two-wire type signal transmission line 13 at the time of slot "1" by the sampling pulse S1 ', and the multiple signal transmitting circuit 11 of the slave station 3 performs sampling. By the pulse S2 ′, the signal α2 of the transmitter 2 is transmitted to the two-wire signal transmission line 13 only in the section of slot “2”.

FIG. 11 (d) is a current signal waveform on the two-wire signal transmission line 13 at this time, FIG. 11 (e) is a waveform after sample hold in the multiple signal receiving circuit 10 of the slave station 3, and FIG. Main station 4
3A and 3B show waveforms after sample and hold in the multiple signal receiving circuit 8 of FIG. From these figures, two kinds of data and the synchronizing signal are multiplexed on the two-wire type signal transmission line 13, and the signals from the other side are clearly separated from the signal transmitted by the master station 4 and the slave station 3 respectively. It turns out that it can be extracted neatly.

In the present embodiment, an example in which two types of data are bidirectionally transmitted has been shown, but the present invention can be applied to multiplexing of three or more types of data, and two or more types of data can be transmitted. It can also be applied to unidirectional transmission.

〔The invention's effect〕

As described above, according to the two-wire data transmission method of the present invention, the zero current that is not included in the data is assigned as the synchronization signal, so that three pieces of information, data information, clock information, and synchronization information are provided. Can be multiplexed into a set of two-wire transmission lines.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS.
FIG. 6 is a block diagram showing a concrete example of each element in the embodiment of FIG. 1, and FIG. 7 is a signal waveform diagram in the synchronizing circuit 9,
8 and 9 are block diagrams showing a concrete example of one element in the embodiment of FIG. 1, FIG. 10 is a signal waveform diagram in the synchronizing circuit 12, and FIG. 11 is a description of the operation of this embodiment. Timing chart for doing. 1 ... Actuator, 2 ... Transmitter, 3 ...
Slave station, 4 ... Main station, 5 ... PID controller, 6 ... Multiple transmission means, 7,11 ... Multiple signal transmitting circuit, 8,10 ... Multiple signal receiving circuit, 9,12 ... Synchronizing circuit.

Claims (1)

[Claims] 1. A master station on the controller side and a slave station for supplying a drive current to an actuator and for inputting a detection signal from a transmitter are connected by a two-wire signal transmission line, and a two-wire signal is transmitted from the master station to the slave station. A drive control signal that varies between 4 and 20 mA is transmitted via the transmission line, and a detection control signal that varies between 4 and 20 mA is also transmitted from the slave station to the master station through the 2-wire signal transmission line. A 2-wire type data transmission method, wherein the 2-wire type signal transmission path is divided into a state in which first, second and third time slots are sequentially repeated to form a multiplex, and a 2-wire type is used in the first time slot. The signal transmission line is set to the base level and is used as a synchronization signal, the 2-wire type signal transmission line is set to the level of the drive control signal in the second time slot, and the 2-wire type signal transmission line is set in the third time slot. The detection system Two-wire data transmission system, characterized in that the level of the signal.