JPH0779353A - Image compression / decompression device - Google Patents

Abstract

(57) [Summary] [Object] To provide an image compression / decompression device capable of image compression / decompression between main memories and compression / decompression between main memories and frame memories. [Structure] When decompressing data, it is selected which of the image data FIFO 50 and the frame memory controller 70 the still image data decompressed by the image compression / decompression device 30 is transferred, and at the time of data compression, the image data FIFO 5 and the frame memory An image compression / decompression device having a transfer switching device 40 for selecting which of the controllers 70 inputs still image data to the image compression / decompression device 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression / expansion device.

[0002]

2. Description of the Related Art A conventional image compression / decompression device will be described with reference to FIGS.

FIG. 2 is a diagram showing the structure of an image compression / expansion device for compressing and expanding image data between a compressed image data area 21 and a still image data area 22 in the main memory 20.

The compressed image in the compressed image data area 21 is decompressed by the image compression / decompression device 30 to be extracted as the still image data area 22.
The decompression function stored in will be described.

The MPU 10 sends the start address of the still image data area 22 to the address register 62 of the DMA controller 60, the byte register 61 to the size of the image resulting from the expansion of the compressed image in the compressed image data area 21, and the status register. The image transfer directions are set to 63.

Then, a DMA transfer start instruction is written in the status register 63. Next, the MPU 10 writes the compressed image data in the compressed image data area 21 from the beginning into the codec register 31 of the image compression / decompression device 30. In this case,
Writing is performed after checking the state of the image compression / decompression device 30 in the status register 32 to confirm that the image can be written.

The compressed image data written in the codec register 31 is expanded by the image compression / expansion device 30 and written in the expansion data register 33.

The decompressed data written in the decompressed data register 33 is written in the image data FIFO 50 under the control of hardware.

If the image data FIFO 50 has decompressed data
The DMA controller 60 transfers the top data in the image data FIFO 50 to the area written in the address register 62,
The address register 62 is increased by 1 and the byte register 61 is decreased by 1.

In this way, the MPU 10 writes all the compressed image data in the compressed image data area 21 into the codec register 31, and the decompressed image is completed by the DMA controller 60 writing in the still image data area 22. .

Next, a compression function of compressing still image data in the still image data area 22 by the image compression / expansion device 30 and storing it in the compressed image data area 21 will be described.

The MPU 10 sets the size of the still image in the still image data area 22 in the byte register 61 of the DMA controller 60 and sets the image transfer direction in the status register 63. The address register 62 is not used.

Next, a DMA transfer start instruction is written in the status register 63. The DMA controller 60 transfers the still image in the still image data area 22 to the image data FIFO 50. In this transfer, the DMA controller 60 controls the transfer so that the image data FIFO 50 does not overflow.

The image data written in the image data FIFO 50 is written in the decompression data register 33.

The image data written in the expanded image data register 33 is compressed by the image compression / expansion device 30 and written in the codec register 31.

The MPU 10 looks at the status register 32 and confirms that the codec register 31 has a compressed image, and writes the contents of the codec register 31 in the compressed image data area 21.

In this way, the still image in the still image data area 22 is compressed by the image compression / expansion unit 30 and stored in the compressed image data area 21.

FIG. 3 is a view showing the arrangement of an image compression / decompression device which compresses and decompresses image data between the frame memory 90 and the compressed image data area 21.

The decompression function of decompressing the compressed image in the compressed image data area 21 by the image compression / decompression device 30 and writing it in the frame memory 90 will be described.

The MPU 10 is the frame memory controller 7
To 0, the image compression / expansion device 30 sends an instruction to write in the frame memory 90 the data of the expansion data register 33 for writing the expansion data.

Next, the MPU 10 writes the compressed image data in the compressed image data area 21 into the codec register 31 of the image compression / decompression device 30 from the beginning.

When the MPU 10 writes the compressed image data in the codec register 31, the status register 32 is used.
Then, the state of the image compression / decompression device 30 is checked to confirm that the image can be written, and then the image is written.

The compressed image data written in the codec register 31 is expanded by the image compression / expansion device 30 and written in the expansion data register 33.

The decompressed data written in the decompressed data register 33 is read out by the frame memory controller 70 under the control of hardware and written in the frame memory area 90 designated by the MPU 10.

In this way, the MPU 10 writes all the compressed image data in the compressed image data area 21 into the codec register 31, and the decompressed image is written into the designated area of the frame memory 90 through the frame memory controller 70.

Next, the compression function of compressing the image data in the frame memory 90 by the image compression / expansion device 30 and storing it in the compressed image data area 21 will be described.

The MPU 10 is the frame memory controller 7
A command for deciding which area of the frame memory 90 to send to the image compression / decompression device 30 is sent to 0.

The frame memory controller 70 expands the designated area of the frame memory 90 to the decompression data register 3
Transfer to 3.

The image data written in the expanded image data register 33 is compressed by the image compression / expansion device 30 and written in the codec register 31.

The MPU 10 looks at the status register 31 and confirms that there is a compressed image in the codec register 31, and writes the contents of the codec register 31 in the compressed image data area 21.

In this way, the image data in the designated area of the frame memory 90 is compressed by the image compression / decompression device 30 and stored in the compressed image data area 21.

[0032]

However, the above-mentioned FIG.
With the configuration shown in (1), the image in the frame memory cannot be compressed and the compressed image in the memory cannot be expanded to the frame memory.

Further, the structure shown in FIG. 3 has a problem that the compressed data in the memory cannot be expanded and stored in the memory, and the image data in the memory cannot be compressed and stored in the memory.

The present invention solves the above-mentioned problems of the prior art by compressing / decompressing image data in a frame memory and compressing / decompressing image data in a memory in one system. An object is to provide a decompression device.

[0035]

In order to achieve this object, an image compression / expansion apparatus of the present invention comprises a compressed image data area for holding compressed image data, a still image data area for holding still image data, and An image compression / decompression device that compresses still image data and decompresses the compressed image data, a frame memory that holds output contents of a display device, a frame memory controller that controls reading and writing of data from the frame memory, and the still image. An image data FIFO that holds data, a DMA controller that transfers still image data between the still image data and the image data FIFO, still image data expanded by the image compression / expansion device, and the image data FIFO and the frame memory. Decide which of the controller to transfer to, the frame memory controller and the image data FIFO And a transfer switch for determining whether to enter the still image data to the image compression and expansion unit from Chira.

[0036]

According to the present invention, since the transfer switching device is provided,
A single image compression control device enables compression / expansion between memories and compression / expansion functions between memories and frame memories.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 10 is an MPU, 20 is a main memory, and 21.
Is a compressed image data area, 22 is a still image data area, 3
0 is an image compression / decompression device, 31 is a codec register, 32
Is a status register, 33 is a decompression data register, 4
0 is a transfer switcher, 50 is an image data FIFO, 60 is a DMA controller, 61 is a byte register, 62 is an address register, 63 is a status register, 70 is a frame memory controller, 80 is a clipping information storage device,
90 is a frame memory, 100 is a display device, and 110 is a bus.

First, the decompression function of decompressing the compressed image in the compressed image data area 21 by the image compression / decompression device 30 and storing it in the still image data area 22 will be described.

The MPU 10 sets the transfer switch 40 in the direction from the decompression data register 33 to the image data FIFO 50.

The MPU 10 sets the start address of the still image data area 22 to the address register 62 of the DMA controller 60, the byte address 61 to the size of the expanded image of the compressed image in the compressed image data area 21, and the status register 63 to the status register 63. Set the image transfer direction. Next, the DMA transfer start instruction is written in the status register 63.

Next, the MPU 10 writes the compressed image data in the compressed image data area 21 into the codec register 31 of the image compression / decompression device 30 from the beginning.

When the MPU 10 writes compressed image data in the codec register 31, the status register 32 is used.
Writing is performed after checking the state of the image compression / expansion unit 30 to confirm that writing is possible.

The compressed image data written in the codec register 31 is expanded by the image compression / expansion device 30 and written in the expansion data register 33.

The decompressed data written in the decompressed data register 33 is transferred by the transfer switch 40 to the decompressed data register 33.
Since it is set to the image data FIFO 50 side, the data is written in the image data FIFO 50.

If the image data FIFO 50 has decompressed data
The DMA controller 60 transfers the top data in the image data FIFO 50 to the area written in the address register 62,
The address register 62 is increased by 1 and the byte register 61 is decreased by 1.

In this way, the MPU 10 writes all the compressed image data in the compressed image data area 21 into the codec register 31, and the decompressed image is written into the still image data area 22 by the DMA controller 60, thus ending the decompression. To do.

Next, a compression function of compressing still image data in the still image data area 22 by the image compression / expansion device 30 and storing it in the compressed image data area 21 will be described.

The MPU 10 first sets the transfer switch 40 in the direction from the image data FIFO 50 to the decompression data register 33.

The MPU 10 sets the size of the still image in the still image data area 22 in the byte register 61 of the DMA controller 60 and sets the image transfer direction in the status register 63. The address register 62 is not used.

Next, a DMA transfer start instruction is written in the status register 63. The DMA controller 60 transfers the still image in the still image data area 22 to the image data FIFO 50. In this transfer, the DMA controller 60 controls the transfer so that the image data FIFO 50 does not overflow.

The image data written in the image data FIFO 50 is written in the expanded data register 33 because the transfer switch 40 is set in the expanded data register 33 from the image data FIFO 50.

The image data written in the expanded image data register 33 is compressed by the image compression / expansion device 30 and written in the codec register 31.

The MPU 10 looks at the status register 32 and confirms that there is a compressed image in the codec register 31, and writes the contents of the codec register 31 in the compressed image data area 21.

In this way, the still image in the still image data area 22 is compressed by the image compression / expansion device 30 and stored in the compressed image data area 21.

Next, the compressed image in the compressed image data area 21 is decompressed by the image compression / decompression device 30 to be expanded in the frame memory 9
The decompression function for writing 0 will be described.

The MPU 10 first sets the transfer switch 40 in the direction from the decompression data register 33 to the frame memory controller 70.

The MPU 10 is the frame memory controller 7
When the image compression / decompression device 30 writes decompression data to 0,
Send an instruction specifying where to write.

Next, the MPU 10 writes the compressed image data in the compressed image data area 21 into the codec register 31 of the image compression / decompression device 30 from the beginning.

When the MPU 10 writes the compressed image data in the codec register 31, the status register 32
Writing is performed after checking the state of the image compression / expansion unit 30 to confirm that writing is possible.

The compressed image data written in the codec register 31 is expanded by the image compression / expansion device 30 and written in the expansion data register 33.

The decompressed data written in the decompressed data register 33 is transferred to the transfer switching unit 40 by the decompressed data register 33.
Since it is set in the direction from the frame memory controller 70 to the frame memory controller 70, the frame memory controller 70 reads out and writes in the area designated by the MPU 10.

In this way, the MPU 10 writes all the compressed image data in the compressed image data area 21 into the codec register 31, and the decompressed image is written into the designated area of the frame memory 90 through the frame memory controller 70.

Next, the compression function of compressing the image data in the frame memory 90 by the image compression / expansion device 30 and storing it in the compressed image data area 21 will be described.

The MPU 10 first sets the transfer switch 40 in the direction from the frame memory controller 70 to the decompression data register 33.

The MPU 10 is the frame memory controller 7
A command for determining which area of the frame memory 90 is to be sent to the image compression / decompression device 30 is sent to 0.

Since the transfer switch 40 is set in the direction from the frame memory 70 to the decompression data register 33,
The frame memory controller 70 is a frame memory 90.
And transfers the designated area in the decompression data register 33.

The image data written in the decompression data register 33 is compressed by the image compression / decompression device 30 and written in the codec register 31.

The MPU 10 looks at the status register 32 and confirms that there is a compressed image in the codec register 31, and writes the contents of the codec register 31 in the compressed image data area 21.

In this way, the image data of the designated area in the frame memory 90 is compressed by the image compression / decompression device 30 and stored in the compressed image data area 21.

[0071]

As described above, the present invention has the function of realizing the compression / expansion between the memories and the compression / expansion between the memory and the frame memory with one image compression / expansion device by having the transfer switch. The effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a first configuration example of a conventional image compression / decompression device.

FIG. 3 is a diagram showing a second configuration example of a conventional image compression / decompression device.

[Explanation of symbols]

 10 MPU 20 Main memory 21 Compressed image data area 22 Still image data area 30 Image compression / decompression device 31 Codec register 32 Status register 33 Decompression data register 40 Transfer switcher 50 Image data FIFO 60 DMA controller 61 Byte register 62 Address register 63 Status register 70 frame memory controller 80 clipping information storage device 90 frame memory 100 display device 110 bus

Claims (1)

[Claims] 1. A compressed image data area for holding compressed image data, a still image data area for holding still image data, an image compression / expansion device for compressing still image data and expanding the compressed image data, and a display device. Between a frame memory that holds the output content of the frame memory, a frame memory controller that controls the reading and writing of data to the frame memory, an image data FIFO that holds the still image data, and the still image data area and the image data FIFO. A DMA controller that transfers still image data, and determines which of the image data FIFO and the frame memory controller to transfer the still image data expanded by the image compression / expansion device, the frame memory controller and the image data
An image compression / decompression device, comprising: a transfer switching device that determines from which of the FIFO the still image data is input to the image compression / decompression device.