JPH077945B2 - Line switching method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a line switching system, and more particularly to a line switching system in a digital wireless communication system that performs FEC.

[Conventional technology]

A large-capacity wireless communication system is usually provided with a protection line in addition to the working line in preparation for deterioration of line quality due to fading or the like, equipment failure, and line maintenance.

In a digital wireless communication line, in order to prevent the occurrence of a code error at the time of line switching due to the synchronization difference between the output signals of both lines due to the difference in propagation delay between the working and protection lines that are switched, A line switching system is used in which line output signals are synchronized and then line switching is performed without code error.

In such a line switching system, each data signal to be transmitted is framed by the transmitting end radio terminal station and transmitted to each line. FEC (Forward Err by Block Code)
or correction), each data signal is also divided into blocks by encoding.

FIG. 2 is a block diagram showing a transmitting end wireless terminal station in a first conventional example of a line switching system for performing such FEC.

In FIG. 2, 1 is a test pattern generator (hereinafter TPG).
2a ・ 12a …… k2a is a timing generator (hereinafter TI
MG), 3a ・ 13a …… k3a is a transmission signal processing circuit (hereinafter
TXDPU), 4 is a transmission signal switching circuit (hereinafter referred to as TXSW), 5a, 15a ... k5a is an FEC coding circuit (hereinafter referred to as FECENC), and 9.19 ... k9 is a TIMG.

TXDPU13a ... k3a converts the data signals D11 ... Dk1 input from the sending end carrier terminal (not shown) at high speed to obtain TIMG
At the timing when 12a ... k2a occurs, empty time slots are provided to form a frame, and additional bits are inserted into these empty time slots and output as data signals D12a ... Dk2a. The additional bit is used for monitoring the wireless transmission section and the like, and includes the frame synchronization bit in it.

The TPG1 generates a data signal D1 which is a test pattern for quality monitoring of the protection line. TXDPU3a converts the data signal D1 into a data signal D2a in the same way as TXDPU13a ... k3a does.

When all the working lines are normal and the protection line is on standby, the data signals D2a, D12a ... Dk2a pass through TXSW4 as they are, and are input to FECENC5a, 15a ... k5a.

FECENC5a ・ 15a …… k5a is the data signal D2a ・ D12a …… Dk2
Redundant bits obtained by performing a speed conversion of a at a high speed, creating an empty time slot at the timing when TIMG9 ・ 19 …… k9 occurs, and blocking the data signal D2a ・ D12a …… Dk2a for block coding for error correction. Are inserted into empty time slots and output as data signals D4 / D13 ... Dk3. The data signal D4 is sent to the protection line, and the data signals D13 ... Dk3 are sent to the respective working lines.

At each intermediate relay station and the receiving end wireless terminal station (neither shown) following the transmitting end wireless terminal station shown in FIG. 2, the data signals D4, D13, ...
The respective FEC decoding circuits perform error correction decoding to restore the data signals D2a, D12a ... Dk2a, and these data signals D2a
D12a ... Dk2a are reconverted into data signals D1, D11 ... Dk1 by respective reception signal processing circuits. The data signals D11 ... Dk11 obtained at the receiving end wireless terminal station are output to the receiving end carrier terminal station,
The data signal D1 is detected by the test pattern detector and used to monitor the quality of the protection line.

When switching one of the working lines, for example, the working line transmitting the data signal D13 to the protection line, the TXSW4 also inputs the data signal D12a to the FEC ENC5a. As a result, the data signal
Both D4 and D13 are data signals D12a encoded. In other words, TXSW4 makes the sending end parallel with the working line and the protection line that are switched.

Due to this transmission end parallel, the data signal output from the FEC decoding circuit for the protection line of the CEC relay station or the receiving end radio terminal station is the data signal D
It becomes 12a. The data signal D12a and the data signal D12a output by the working line FEC decoding circuit are synchronized with each other by the synchronization switching circuit, and line switching is performed without code error. There is also a method in which the two data signals D12a are reconverted to the data signals D11 and then synchronously switched. Whichever method is used, it is necessary to establish frame synchronization for each of the two data signals D12a. The frame timing of the data signal output by the FEC decoding circuit for the protection line can be set by the timing of TIMG2a before sending end parallel, and after sending end parallel.
The timing of TIMG12a is set. Therefore, the frame timing of the data signal passing through the protection line changes when the transmission ends are in parallel, and the frame synchronization is temporarily lost. It takes some time for frame sync to be lost and then reestablished. At this time, the synchronization switching operation is interrupted, but the time for reestablishing frame synchronization is relatively short, which is not a problem in synchronization switching. On the other hand, the word timing of the data signal D4 input to the protection line FEC decoding circuit is set by TIMG9, and it does not change depending on the sending end parallel, so the word synchronization of the protection line FEC decoding circuit will not be lost at this time. .

The first conventional example described above has the advantage that the frame length for inserting additional bits and the block length (word length) for encoding can be set freely regardless of each other.
The hardware becomes complicated because the element conversion is performed twice at the transmitting end wireless terminal station.

FIG. 3 is a block diagram showing a transmitting end wireless terminal station in a second conventional example of a line switching system for performing FEC.

The transmitting end wireless terminal shown in FIG. 3 removes TIMG9, 19 ... k9 from the transmitting end wireless terminal shown in FIG.
To TIMG2 ・ 12 …… k2, TXDPU3a ・ 13a …… k3a to TXDPU3 ・
13 …… k3, FECENC5a ・ 15a …… k5a to FECENC5 ・ 15 …… k
It is replaced with 5.

TXDPU3 · 13 ··· k3 converts the data signals D1 / D11 ··· Dk1 at high speed, and provides two types of empty time slots at the timing when TIMG2 · 12 ··· k2 occurs to form a frame.
An additional bit is inserted into one of these empty time slots and the other empty space is output as data signals D2, D12 ... Dk2. FECENC5 ・ 15 …… k5 is the data signal D2 ・ D12 …… Dk
Redundant bits obtained by error-correcting block coding operation of 2 are inserted into the other empty time slot above and the data signal
D4 / D13 …… Output as Dk3. The other operations are the same as those of the transmitting end wireless terminal station shown in FIG.

In this second conventional example, the speed can be converted only once at the transmitting end wireless terminal station, so the hardware is simple, but the word timing of the data signal D4 changes from the timing of TIMG2 to the timing of TIMG12 when the transmitting end is parallel, Word synchronization of the FEC recovery circuit for the protection line of the intermediate relay station or the receiving end wireless terminal station is lost. The FEC decoding circuit is normally word-synchronized by self-synchronization. That is, the FEC decoding circuit detects and corrects an erroneous bit for each word of the error correction block code.
The FEC decoding circuit monitors the occurrence probability of the detected erroneous bit, and when this occurrence probability exceeds a certain threshold value, it is determined that the word synchronization has been lost, and the word synchronization phase is shifted by one time slot. , Check whether the probability of erroneous bit generation falls below the threshold value described above.
In this way, the phase of word synchronization is shifted by trial and error, and if the probability of the occurrence of an erroneous bit falls below the threshold value, it is determined that word synchronization has been established, and the phase of word synchronization at this time is maintained. To do. There is a limit to the number of error-correctable bits per codeword in an error-correcting block code, and if a bit error occurs beyond this limit, error correction is impossible and the input data signal is output as is. When the word synchronization is lost, it appears to the FEC decoding circuit that many bit errors occur.
The C decoding circuit outputs the input signal as it is. Now,
It takes time until the word synchronization is reestablished after the sending end parallel and the data signal D4 via the protection line is error-corrected and decoded, and the synchronization switching operation is not completed during this time. FE for protection line
The time until the frame synchronization with the data signal D12 output from the C decoding circuit is established is the same as in the first conventional example.

Since the time required for establishing the word synchronization of the FEC decoding circuit is much longer than the time required for establishing the frame synchronization for the data signal D12, the line switching time in the second conventional example is much longer than that in the first conventional example. This is a big problem for the second conventional example.

[Problems to be solved by the invention]

As described above, in the conventional line switching method for performing FEC, the speed is doubled at the transmitting end wireless terminal station, so the hardware becomes complicated and expensive, or otherwise the line switching time becomes long. There is a drawback that.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a line switching system in which the speed conversion at the transmitting end wireless terminal station is performed only once and the line switching time is short.

[Means for solving problems]

The line switching system of the present invention has a working line and a protection line, converts the speed of a first data signal input from a sending end carrier terminal station, and provides first and second empty time slots to reduce the number of frames. Also, additional bits including a frame synchronization bit are inserted into the first empty time slot to be converted into a second data signal, and the second data signal is subjected to error correction block coding operation by a working coding circuit. The obtained first redundant bit is inserted into the second vacant time slot, encoded into a third data signal and transmitted to the working line, and the working line cannot be used for normal signal transmission, and the third line is transmitted to the protection line. A fourth data signal by inserting a second redundant bit obtained by performing an error correction block coding operation on the second data signal by a preliminary coding circuit when the line is switched to the second empty time slot. In the line switching method of encoding and transmitting to the protection line, the second data signal is restored by performing error correction decoding of the third data signal that has passed through the working line in word synchronization based on a first timing pulse. And outputs the third data signal as it is when the error correction decoding is not possible, and the fourth data signal passed through the protection line in word synchronization based on the second timing pulse. Error-correction-decoding to restore and output the second data signal, and when the error-correction decoding is impossible, a preliminary decoding circuit that outputs the fourth data signal as it is, and a signal output by the working decoding circuit or The first redundant bit is inserted in frame synchronization by detecting the frame synchronization bit from the third data signal that has passed through the working line. The current frame synchronization circuit for generating the first timing pulse representing the time position of the time slot, and the frame synchronization bit from the signal output by the preliminary decoding circuit or the fourth data signal via the preliminary line. And a spare frame synchronization circuit for generating the second timing pulse which indicates the time position of the time slot in which the second redundant bit is inserted in synchronization with the detection.

[Examples] The present invention will be described in detail below with reference to the drawings illustrating examples.

FIG. 1 is a diagram showing an embodiment of a line switching system of the present invention, (a) is a block diagram of a transmitting end wireless terminal station, and (b) is a block diagram of an intermediate relay station.

The transmitting end wireless terminal shown in FIG. 1A has the same structure and operation as the transmitting end wireless terminal shown in FIG. 3, that is, the terminal operating wireless terminal in the second conventional example.

The intermediate relay station shown in FIG. 1 (b) is provided with data signals D4, D13 ... Dk3 and timing pulses P2 output by the respective receivers (not shown) of the protection line and the working line.
・ P11 …… Pk1 input and data signal D2 ・ D12 …… Dk2 output FEC decoding circuit (hereinafter referred to as FECDEC) 6 ・ 16 …… k6
And a frame synchronization circuit that inputs data signals D2 ・ D12 …… Dk2 and outputs timing pulses P2 ・ P11 …… Pk1 (hereinafter FS
YNC) 7 ・ 17 …… k7 and data signals D2 ・ D12 …… Dk
FEC ENC which inputs 2 and timing pulses P2, P11 ... Pk1 and outputs data signals D4, D13, ... Dk3 to respective transmitters (not shown) of the protection line and working line
8 ・ 18 …… k8

FECDEC6 ・ 16 …… k6 is the timing pulse P2 ・ P11 …… Pk
Data signal D4 / D13 ... with 1 as the word timing reference
... Dk3 is error-correction-decoded to restore the data signals D2, D12, ... Dk.

FSYNC7 ・ 17 …… k7 is the restored data signal D2 ・ D12…
… By detecting the frame synchronization bit from Dk2 and performing frame synchronization, the time position of the time slot in which the redundant bit of the error correction block code was inserted is known, and the timing pulse P2 · P11 …… Pk1 representing this time position To occur.

The FECENC8 · 18 ··· k8 encodes the data signals D2 · D12 ··· Dk2 that have passed through the FSYNC7 · 17 ··· k7 into block codes for error correction and outputs them as the data signals D4 / D13 ·· Dk3. Timing pulses P2, P11 ... Pk1 are used to determine the word timing of this encoding.

As already described in the description of the second conventional example, the word timing of the data signal D4 and the data signal D2 when the sending end is parallel.
The frame timing of (this data signal becomes the same as the data signal D12 after sending end parallel) changes, and the word synchronization of FECDEC6 and the frame synchronization of FSYNC7 are lost.

The FECDEC6 does not perform error correction decoding on the data signal D4 when the word synchronization is lost, and outputs it as it is as the data signal D2. As a result, even if the frame synchronization of FSYNC7 is lost at this time, ignoring that the frame synchronization bit in the data signal D2 is not error-corrected (since the line is switched to the protection line, the frame synchronization bit in the data signal D2 is It can be considered that the transmission code error probability is low), and the time required to reestablish the frame synchronization of FSYNC7 is not affected by the loss of word synchronization of FECDEC6. When the frame synchronization of FSYNC7 is reestablished, the correct timing pulse P2 is generated, the word synchronization of FECDEC6 is reestablished, and the error correction decoding is restarted.

Word synchronization of FECDEC for each line at the receiving end wireless terminal station,
FECDEC in the intermediate relay station shown in FIG.
6 ・ 16 …… Similar to k6 word synchronization.

In the embodiment shown in FIG. 1, FSYNC is arranged after FECDEC in the intermediate relay station or the receiving end wireless terminal station.
It may be placed before FECDEC. In this case, the frame sync bits detected by FSYNC are those that have not been error-corrected by FECDEC.

〔The invention's effect〕

As described in detail above, the synchronous switching system of the present invention does not perform self-synchronization with the data signal input to the FECDEC of the intermediate relay station or the receiving end wireless terminal station, but performs word synchronization based on the timing pulse generated by FSYNC. , Sending end wireless terminal station performs only one transmission rate conversion, so when sending end is parallel
Even if FECDEC word synchronization is lost, if FSYNC synchronization is reestablished relatively quickly, frame synchronization is established.Timing pulses are generated due to FEC, and the synchronization switching operation for a long time for self synchronization of FECDEC is not completed. This has the effect of shortening the line switching time.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a line switching system of the present invention, in which (a) is a block diagram of a transmitting end wireless terminal station, (b) is a block diagram of an intermediate relay station, and FIG. 2 and FIG. FIG. 1 is a block diagram showing each of the transmitting end wireless terminal stations in the first and second conventional examples of the line switching method. 2 ・ 12 ・ k2 …… Timing generator (TIMG), 3 ・ 13 ・ k3
...... Transmission signal processing circuit (TXDPU), 4 …… Transmission signal switching circuit (TXSW), 5 ・ 15 ・ k5 …… FEC coding circuit (FECEN)
C), 6 ・ 16 ・ k6 …… FEC decoding circuit (FECDEC), 7 ・ 17 ・
k7: Frame synchronization circuit (FSYNC).

Claims (1)

[Claims] 1. A first data signal having a working line and a protection line, input from a transmitting end carrier terminal, is subjected to speed conversion, and first and second vacant time slots are provided to form a frame, and at least frame synchronization is performed. An additional bit including a bit is inserted into the first empty time slot to be converted into a second data signal, and the second data signal is obtained by performing an error correction block coding operation on the current coding circuit. One redundant bit is inserted into the second empty time slot, encoded into a third data signal and transmitted to the working line, and the working line cannot be used for normal signal transmission and the line is switched to the protection line. At this time, the second redundant bit obtained by performing the error correction block coding operation on the second data signal by the preliminary coding circuit is inserted into the second empty time slot and coded into the fourth data signal. In a line switching system for sending to a protection line, error-correction decoding of the third data signal that has passed through the working line in word synchronization based on a first timing pulse is performed to restore and output the second data signal. When the error correction decoding is impossible, the current decoding circuit that outputs the third data signal as it is, and the fourth data signal that has passed through the protection line in word synchronization based on the second timing pulse is error-corrected. A preliminary decoding circuit that decodes and outputs the second data signal and outputs the fourth data signal as it is when error correction decoding is impossible; and a signal output by the working decoding circuit or the working line The time at which the first redundant bit is inserted in frame synchronization by detecting the frame synchronization bit from the third data signal via An active frame synchronization circuit that generates the first timing pulse that represents the time position of a lot, and detects the frame synchronization bit from the signal output by the backup decoding circuit or the fourth data signal that has passed through the backup line. And a spare frame synchronization circuit for generating the second timing pulse indicating the time position of the time slot in which the second redundant bit is inserted in frame synchronization.