JPH078101B2 - Digital protective relay - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a digital protective relay device, and more particularly to a digital protective relay device that processes a plurality of relay elements by the same microprocessor.

[Technical background of the invention and its problems]

A well-known digital protective relay device is a first relay element called a main detection relay element and a failure detection relay element (fail safe relay element), as disclosed in JP-A-55-41189. A digital processing unit that determines the operation of the second relay element, which is called, is separated and the trip output is output according to the AND condition of the judgment results of both elements, thereby reducing the possibility that the trip output is erroneously output. Is.

However, the above apparatus is expensive because it requires two digital processing units.

Therefore, the first relay element and the second relay element are arithmetically processed by the same arithmetic processing circuit in the same manner as the method generally executed by the computer, and the operation of the first relay element is performed. A method is considered in which an output circuit for outputting an output and an output circuit for outputting an operation output of the second relay element are separated to reduce the possibility that the digital protective relay device outputs an erroneous operation output. This will be described with reference to the circuit configuration diagram of the conventional digital protective relay device shown in FIG.

In Fig. 1, multiple system information obtained from the power system
v and i are input to the input conversion circuits 1-1, ..., 1-6 for converting into voltage and current values suitable for processing. The outputs of the input conversion circuits 1-1, ..., 1-6 are input to the sample hold circuits (S / H) 2-1, ..., 2-6 to sample all the inputs at the same time, and further the multiplexer circuit ( The data is input to the MPX) 3 and serially and serially converted by the analog / digital conversion circuit (A / D) 4.
Then, a plurality of pieces of information converted into analog / digital,
That is, the relay input is input to the digital processing unit 8 and sent to the digital arithmetic processing unit (CPU) 6 by the direct memory access control circuit (DMA) 5. This digital arithmetic processing unit (CPU) 6 is an arithmetic processing circuit (ALU) 6-1, data memory (MEM) 6-2, program memory (ROM) 6-3,
First output circuit (DO1) 9-1 and second output circuit (DO2) 9-2
And a bus BUS that connects these circuits. The first operation output OP1 output from the first output circuit 9-1 and the second output circuit 9-2 are output. Second operation output O
P2 is input to the trip circuit 10 and the trip signal TRIP is output from the trip circuit 10. The arithmetic processing circuit 6-1 stores not only voltage information and current information of the digital value fetched from the direct memory access control circuit 5 via the data memory 6-2, but also a settling value from the settling circuit (SET) 7. The operation of the first relay element and the second relay element is judged according to a predetermined program stored in the program memory 6-3. During operation, "0" is output via the bus BUS to the first output circuit for the first relay element.
9-1 and for the second relay element, to the second output circuit 9-2 . The first output circuit 9-1 and the second
The output circuit 9-2 outputs the first operation output OP1 and the second operation output OP2, respectively, when "1" is written by the arithmetic processing unit 6-1. The trip circuit 1
Reference numeral 0 is a well-known circuit composed of a contact circuit or a thyristor circuit, and outputs the trip output TRIP only when both the first operation output OP1 and the second operation output OP2 are output.

Here, in this conventional example, the output circuit for outputting the operation output of the first relay element and the second relay element is the first
Since the output circuit 9-1 and the second output circuit 9-2 are separated from each other, the operation outputs of both the first relay element and the second relay element are erroneously output due to a single failure of the output circuit. Since it is not performed, no malfunction output is output to the trip output.

However, the digital protective relay device having the configuration shown in FIG. 1 has the following problems.

That is, a bus BU that connects the arithmetic processing device 6-1 or the arithmetic processing device 6-1 with the first output circuit 9-1 and the second output circuit 9-2.
A failure occurs in S, and the processor 6-1 outputs the first output circuit.
When "1" is always written to the 9-1 and second output circuits 9-2 , both the first operation output OP1 and the second operation output OP2 are output, and the trip output TRI
The malfunction output is output to P. As such a failure, for example, a failure in which the data output from the arithmetic processing device 6-1 to the bus BUS is always fixed to "1" is considered.

Further, when the bus BUS has a failure and the first output circuit 9-1 is written to, the second output circuit 9-2 is simultaneously written, or the second output circuit 9-2 is written to the first output circuit 9-2 . In the case where the output circuit 9-1 is also written, both the first operation output OP1 and the second operation output OP2 can be obtained by operating only one of the first relay element and the second relay element. Is output, and the malfunction output is a trip output.
It will be output from TRIP.

As described above, in the conventional digital protective relay having the configuration shown in FIG. 1, a malfunction output can be eliminated when the output circuit has a single failure. It has the disadvantage that a malfunction may be output due to a single failure.

[Object of the Invention] The present invention has been made in order to solve the above problems, and an object thereof is a digital type in which the operation of the first relay element and the second relay element is determined by the same arithmetic processing circuit. It is an object of the present invention to provide a highly reliable and inexpensive digital protective relay device with extremely low possibility that a malfunction output will occur even if a hardware failure occurs in the protective relay device.

[Outline of Invention]

In order to achieve the above-mentioned object, the present invention provides a digital protective relay device that outputs a trip output under an AND condition of a first relay element and a second relay element, wherein the first relay element and the second relay element are provided. An arithmetic processing circuit for determining the operation of the relay element outputs a code written to the first output circuit when the first relay element operates and a code written to the second output circuit when the second relay element operates. It is different.

Example of Invention

 [Structure of Embodiment] An embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit diagram of the essential parts of an embodiment of a digital protective relay device according to the present invention. In this case, the first in FIG.
The output circuit 9-1 , the second output circuit 9-2, and the part corresponding to the AND circuit 10 are shown, and the other configurations are the same as those in FIG. Therefore, 9A-1 , 9A-2 , and 10 in Fig. 2 are 9-1 and 9A in Fig. 1, respectively.
It is equivalent to 9-2 , 10.

In this embodiment, the first output circuit 9A-1 is a well - known latch circuit 11.
-1, and the second output circuit 9A-2 is a well - known latch circuit 11
-2 and an inverting circuit 12 connected to the latter stage of this circuit.

As a result of the operation determination, the arithmetic processing circuit 6-1 outputs “1” when the first relay element is operating and “0” when the first relay element is not operating via the bus BUS to the first output circuit 9A. -Latch circuit in 1 11-
Write to 1. This latch circuit 11-1 has a written "0"
Alternatively, it retains "1" and outputs it as the first operation output OP1. In addition, as a result of the operation determination, the arithmetic processing circuit 6-1 outputs “0” when the second relay element is operating and “1” when it is not operating, through the bus BUS to the second output. Write to the latch circuit 11-2 in the circuit 9A-2 . The latch circuit 11-2 holds and outputs the written "1" or "0". The inversion circuit
The input 12 is the output to the latch circuit 11-2, and the input is "0".
When the input is “1”, when the input is “1”, the output is “0”
Output as OP2. The trip circuit 10 inputs the first operation output OP1 and the second operation output OP2, and outputs the trip output TRIP only when both of them are "1".

[Operation of Example]

Next, the operation of this embodiment will be described. Arithmetic processing circuit 6-
As a result of the operation determination in 1, the first relay element and the second relay element
When both relay elements are operating, "1" is written in the latch circuit 11-1 and "0" is written in the latch circuit 11-2 by the arithmetic processing circuit. Therefore, the first operation output becomes "1", the output "0" of the latch circuit 11-2 is inverted by the inversion circuit 12, and the second operation output also becomes "1". As a result, both inputs of trip circuit 10 become "1", so relay output
RY is output. Here, if at least one of the first relay element and the second relay element is inoperative, at least one of the first operation output OP1 and the second operation output OP2 becomes "0". Therefore, trip output TRIP is not output.

[Effect of Example]

Since the present embodiment is configured as described above, not only when either the first or second output circuit becomes defective, but also the bus or the arithmetic processing circuit becomes defective and the arithmetic processing circuit outputs Even if the writing of "1" or "0" to the second output circuit is not correctly performed, the first and second output circuits are both caused by the defect for the reason described below. Since the operation output is not output and the trip circuit does not output an incorrect trip output as a result, a highly reliable digital protection relay that does not immediately output an incorrect trip output due to one defect An electric device can be provided.

That is, for example, even if the first output circuit becomes defective and the first operation output “1” is output, if the second output circuit is normal, the second operation output “0” is changed to the second operation output “0”. Since the relay element is not output unless it operates, the wrong trip output is not immediately output. The same applies when the second output circuit becomes defective. Further, for example, the arithmetic processing circuit or the bus becomes defective, and "1" is always written when writing to the first and second output circuits regardless of the operation of the first and second relay elements. In this case, the first output circuit erroneously outputs the first operation output, but the second output circuit does not output the second operation output. Therefore, in this case also, the trip output is not output. . Further, even when "0" is always written in the first and second output circuits, the trip output is not output in the same manner. Furthermore, when the bus becomes defective and the operation processing circuit simultaneously writes "0" or "1" to the first or second output circuit, the first and second output circuits can be simultaneously written. Since the second operation output is never output together, the trip output is not output.

FIG. 3 shows a second embodiment of the present invention. In this case, the arithmetic processing circuit selects a combination of "1" and "0" from the known latch circuits 11-3 and 11-4 via the bus BUS. A code of two bits or more is written, the latch circuits 11-3 and 11-4 hold and output the code, and the well-known first and second comparison circuits 13-1 and 13-2 operate in the latch circuit 11-. The point that the first and second operation outputs are output only when the outputs of 3, 11-4 and the first and second code data different from each other are compared and they match each other is shown in FIG. Only the first and second output circuits and the trip circuit are shown in the same manner as in FIG. 2 except for the difference from the embodiment, and the other parts are exactly the same as in FIG. The same parts as those in the configuration are designated by the same reference numerals, and detailed description thereof will be omitted.

Next, the operation of the present embodiment will be described. When the first relay element is operating, the arithmetic processing circuit 6-1 writes the first code in the latch circuit 11-1 via the bus BUS. The first comparison circuit 13-1 compares the first code data held by the first latch circuit 11-1 and the preset first code data set by the first comparison circuit 13-1 with each other and matches the first code data. The first operation output OP1 is output. When the second relay element is in operation, the arithmetic processing circuit 6-1 writes the second code to the latch circuit 11-2 via the bus BUS, and the second code is the latch circuit 11-2.
The second operation output OP2 is output from the second comparison circuit by being held in the second comparison circuit and being input to the second comparison circuit to be compared with the preset second code data and coincide with each other. The first code data and the second code data are different. Operations other than these are the same as those shown in FIG.
Since it is exactly the same as the embodiment described above, detailed description will be omitted.

With the above configuration, even when the bus BUS and the arithmetic processing circuit become defective, the first code is written to the first output circuit even though the first and second relay elements are inoperative. Since writing the second code to the second output circuit cannot occur by a single hardware failure, as in the first embodiment of FIG. 2, an extremely highly reliable digital protection relay is used. A device can be provided.

Furthermore, one of the first and second output circuits 9B-1 and 9B-2 is used as the first or second output circuit in the embodiment of FIG.
It is clear that similar effects can be obtained for the following reasons even if they are replaced with 9A-1 and 9A-2 .

That is, in order for the first or second output circuit 9B-1 , 9B-2 to output the first or second operation output, the first or second code must be written from the arithmetic processing circuit 6-1. However, since the first or second code is a combination of a plurality of bits "0" and "1", the first or second code is caused by a single failure of the arithmetic processing circuit 6-1 and the bus BUS. This is because it is extremely rare that the code is erroneously written in the first or second output circuit.

FIG. 4 shows a third embodiment of the present invention. 2 and 3
In the first and second embodiments of the drawing, the bit position of the signal on the bus BUS used when the arithmetic processing circuit writes the code or the like to the first and second output circuits is not considered at all. In the present embodiment, when the first or second relay element operates, the arithmetic processing unit causes the first or second output circuit 9C-
1 , when writing "1" to 9C-2 , different bits in the bus BUS, that is, BUS _i and BUS _j are used in this embodiment. Except this point, it is exactly the same as the conventional example of FIG. 1, and only the first and second output circuits and the trip circuit are shown as in FIGS. 2 and 3, and other parts are completely different from those of FIG. The same parts are designated by the same reference numerals, and detailed description thereof will be omitted.

Next, regarding the operation of this embodiment, writing "1" from the arithmetic processing circuit 6-1 to the first and second output circuits 9C-1 and 9C-2 is performed via different signal lines in the bus BUS. The description is omitted because it is exactly the same as the conventional example of FIG. 1 except that it is performed.

With the above configuration, the signal line used for writing to the first output circuit and the signal line used for writing to the second output circuit are separated, so that both signal lines are defective due to a single defect of the bus BUS. Since it is rare that both the first and second output circuits output the first and second operation outputs, it is highly reliable that the trip output is unlikely to be erroneously output. It is possible to provide a proper digital type protective relay device.

In each of the above embodiments, the case where the input system information is 6 quantities has been described, but it goes without saying that it may be any quantity. Further, although a method by direct memory access is used as a method for inputting these system information, it is obvious that any method such as reading through a digital input circuit may be used without being limited to this.

Further, the first and second codes used in the second embodiment are 2 if the combination of "1" and "0" is different from each other.
It is also clear that any bit width may be used in addition to the bit width, and the first and second codes may have different bit widths.

Further, in the second embodiment, as in the third embodiment, the signal lines in the bus using the first and second codes are made different between the first code and the second code. By doing so, it is also clear that it is possible to further reduce the possibility of erroneous trip output.

Further, in each of the above embodiments, the trip output at the time of initializing the apparatus is not considered, but it is also possible to prevent unnecessary trip output at the time of initializing by the method described below. it is obvious. That is, for example, in the embodiment of FIG. 2, the latch circuit 11-1 clears and outputs "0" at the time of initialization, and the latch circuit 11-2 presets and outputs "1". During initialization, the latch circuits in the first and second output circuits are cleared or preset regardless of their inputs so that the first and second operation outputs are not output, or as shown in FIG. In addition, a well-known first AND circuit 14-1 and an initialization signal INIT which output the initialization signal INIT which becomes “0” at initialization and the first operation output OP1 and which output when both inputs are “1” A well-known second AN that outputs the second operation output OP2 when both inputs are "1".
D circuit 14-2 is provided, and the first and second AND circuits 14-1, 1 are provided.
By inputting the output of 4-2 to trip circuit 10, both inputs of trip circuit 10 are set to "0" at the time of initialization.
There is a method to turn off the trip output. Here, the reference numerals in FIG. 5 correspond to those in FIG. 2, and the same portions are designated by the same reference numerals.

Further, in the second embodiment of FIG. 3, at least one of the first and second comparison circuits 13-1 and 13-2 outputs “0” when the signs match, and is the same as that of FIG. In the same manner, it is of course possible to provide an inverting circuit that receives the output as an input and inverts the logic to output the output, and use the output of the inverting circuit as the first or second operation output.

〔The invention's effect〕

According to the present invention, it is possible to provide a highly reliable digital protective relay device in which a relay output is not erroneously output even if a single defect occurs in an output circuit, a bus, and an arithmetic processing circuit. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional digital protective relay device, and FIGS. 2 to 5 are block diagrams showing an embodiment of the present invention. 1-1 to 1-6 ... Input conversion circuit 2-1 to 2-6 ... Sample and hold circuit 3 ... Multiplexer circuit 4 ... Analog / digital conversion circuit 5 ... Direct memory access circuit 6 , 6C ... Digital arithmetic processing unit 6-1 , 6C-1 ... Arithmetic processing circuit 6-2 ... Data memory 6-3 ... Program memory 7 ... Settling circuit 8 , 8C ... Digital processing circuit 9-1 , 9-2 , 9A-1 , 9A-2 , 9B-1 , 9B-2 , 9C-2 ... Output circuit 10 ... AND circuit 11-1 to 11-4 ... Latch circuit 12 ... Inversion circuit 13-1, 13-2 ... Comparison circuit 14-1, 14-2 ... AND circuit

Claims (4)

[Claims] 1. An AN for a first relay element and a second relay element.
In a digital protective relay device that outputs a trip output under D condition, an arithmetic processing circuit that determines the operation of the first relay element and the second relay element, and the arithmetic processing circuit operates as a first relay element. The first determination result is written when the first operation circuit produces the first operation output, and the second determination result is written when the arithmetic processing circuit operates as the second relay element. A second output circuit for outputting the operation output of the above, and a plurality of signal lines for connecting the arithmetic processing circuit and the first and second output circuits and transmitting the first and second determination results. Bus
A trip circuit that receives the first operation output and the second operation output and outputs a trip output only when both the first operation output and the second operation output are output, The code for writing the first determination result in the first output circuit and the second determination result in the second
The digital protective relay is characterized in that the sign when writing to the output circuit is different. 2. The code when the arithmetic processing circuit writes the first judgment result to the first output circuit is "1", and the code when the second judgment result is written to the second output circuit is "1". The digital protective relay device according to claim 1, wherein the protective relay device is 0 ". 3. A code used when the arithmetic processing circuit writes the first determination result in the first output circuit, and a second determination result obtained in the second code.
At least one of the codes when writing to the output circuit of is a code of 2 bits or more which is a combination of "1" and "0",
The digital protective relay device according to claim (1) is characterized in that the same reference numerals are not used. 4. A signal line on a bus used when an arithmetic processing circuit writes a first determination result to a first output circuit, and a second signal line.
The digital protective relay device according to claim (1), wherein the signal lines on the bus used when writing the determination result of (1) to the second output circuit are different.