JPH0783054B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0783054B2
JPH0783054B2 JP5240153A JP24015393A JPH0783054B2 JP H0783054 B2 JPH0783054 B2 JP H0783054B2 JP 5240153 A JP5240153 A JP 5240153A JP 24015393 A JP24015393 A JP 24015393A JP H0783054 B2 JPH0783054 B2 JP H0783054B2
Authority
JP
Japan
Prior art keywords
wiring layer
connection hole
layer
wiring
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5240153A
Other languages
Japanese (ja)
Other versions
JPH06283608A (en
Inventor
幸広 牛久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP5240153A priority Critical patent/JPH0783054B2/en
Publication of JPH06283608A publication Critical patent/JPH06283608A/en
Publication of JPH0783054B2 publication Critical patent/JPH0783054B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.

【0002】[0002]

【従来の技術】近年の半導体製造技術の向上は目覚し
く、特に半導体装置上の配線においては、2層から3
層、更に4層以上の多層化が実現されるに至っている。
しかし、一方では配線層の増加に伴い半導体表面の段差
形状が益々複雑化しており、断線を含む配線特性の劣化
や信頼性の低下等の問題が表面化している。特に、所望
の配線層間を接続するための接続孔に関しては、従来出
来るだけ大きく開口するのが一般的であり、かつ有利で
あると考えられていたが、このような接続孔では以下に
述べるような不都合があった。
2. Description of the Related Art Recent improvements in semiconductor manufacturing technology are remarkable, especially in wiring on a semiconductor device from two layers to three layers.
The number of layers and the number of layers of four or more have been realized.
However, on the other hand, as the number of wiring layers increases, the stepped shape of the semiconductor surface becomes more and more complicated, and problems such as deterioration of wiring characteristics including disconnection and deterioration of reliability have come to the surface. In particular, with regard to connection holes for connecting desired wiring layers, it has been generally considered that it is common and advantageous to open the connection holes as large as possible in the past. There was an inconvenience.

【0003】図1は従来の半導体装置の要部の構造を示
す平面図で、図2は図1の矢視A−A断面を示す図であ
る。図中1は半導体基板で、この基板1の表面には拡散
層2が形成されている。半導体基板1上には第1の絶縁
層3が設けられ、この絶縁層3の拡散層2上には接続孔
4が開孔されている。絶縁層3上にはAl膜からなる第
1の配線層5が設けられており、この配線層5は接続孔
4を介して拡散層2と接続されている。
FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device, and FIG. 2 is a view showing a cross section taken along the line AA of FIG. In the figure, 1 is a semiconductor substrate, and a diffusion layer 2 is formed on the surface of the substrate 1. A first insulating layer 3 is provided on the semiconductor substrate 1, and a connection hole 4 is opened on the diffusion layer 2 of the insulating layer 3. A first wiring layer 5 made of an Al film is provided on the insulating layer 3, and the wiring layer 5 is connected to the diffusion layer 2 via a connection hole 4.

【0004】ここで、接続孔4は拡散層2と配線層5と
の間の接続を確実にするため拡散層2、配線層5の重な
る領域で比較的大きく、かつ、配線層5の長さ方向に長
く形成されている。
Here, the connection hole 4 is relatively large in the region where the diffusion layer 2 and the wiring layer 5 overlap in order to ensure the connection between the diffusion layer 2 and the wiring layer 5, and the length of the wiring layer 5 is large. It is formed long in the direction.

【0005】また、第1の絶縁層3及び第1の配線層5
上には、第2の絶縁層6を介してAl膜からなる第2の
配線層7が設けられている。なお、この第2の配線層7
は第1の配線層5と交差する関係に形成され、かつ前記
接続孔4上を通過している。
Further, the first insulating layer 3 and the first wiring layer 5
A second wiring layer 7 made of an Al film is provided on the upper side of the second insulating layer 6. The second wiring layer 7
Are formed so as to intersect with the first wiring layer 5 and pass over the connection hole 4.

【0006】[0006]

【発明が解決しようとする課題】このような構成では、
第2の配線層7は、第1の絶縁層3の表面形状に起因す
る第2の絶縁層6の段差により、絶縁層6への被覆性が
悪くなり、段差部においてその膜厚が極めて薄くなる。
このため、第2の配線層7の段切れや配線抵抗増大等の
配線特性の劣化を招き、またマイグレーション等による
信頼性低下を招くと言う問題があった。
SUMMARY OF THE INVENTION With such a configuration,
The second wiring layer 7 has poor step coverage of the second insulating layer 6 due to the surface shape of the first insulating layer 3 and thus has poor coverage with the insulating layer 6, resulting in a very thin film thickness at the step portion. Become.
For this reason, there is a problem that the wiring characteristics are deteriorated such as a step break of the second wiring layer 7 and the wiring resistance is increased, and the reliability is lowered due to migration and the like.

【0007】なお、上述した問題は第2の配線層7の幅
よりも接続孔4の長手方向の方が長く、配線層7が接続
孔4にて完全に横切られるために生じるものであり、こ
れを避けるためには接続孔4を配線層7の幅より短く形
成すればよい。しかしながら、この場合には接続孔4の
面積が狭くなり、拡散層2と第1の配線層5との接続が
不確実となるため、好ましくない。
The above-mentioned problem occurs because the connecting hole 4 is longer in the longitudinal direction than the width of the second wiring layer 7 and the wiring layer 7 is completely crossed by the connecting hole 4. In order to avoid this, the connection hole 4 may be formed shorter than the width of the wiring layer 7. However, in this case, the area of the connection hole 4 becomes small, and the connection between the diffusion layer 2 and the first wiring layer 5 becomes uncertain, which is not preferable.

【0008】本発明の目的は、配線層が接続孔上の段差
を通過することに起因する該配線僧の段切れや抵抗増大
化等を未然に防止することができ、配線特性及び信頼性
の向上をはかり得る半導体装置を提供することにある。
An object of the present invention is to prevent the wiring layer from being stepped or having its resistance increased due to the wiring layer passing through a step on the connection hole, thereby improving the wiring characteristics and reliability. It is to provide a semiconductor device which can be improved.

【0009】[0009]

【課題を解決するための手段】上記の目的を達成するた
めに本発明の半導体装置は、表面に拡散層を有する半導
体基板上に絶縁層と配線層が交互に積層された多層配線
構造を有し、前記拡散層と第1の配線層とが前記絶縁層
に設けられた接続孔を通して相互接続され、この接続孔
上を第2の配線層が通過するものであって、この第2の
配線層より幅広の前記接続孔が、前記第2の配線層が通
過する領域で、前記第2の配線層の幅方向に並ぶ複数の
接続孔と前記第2の配線層の通過領域外に設けられた接
続孔とに分割されてなることを特徴とする。
In order to achieve the above object, a semiconductor device of the present invention has a multilayer wiring structure in which insulating layers and wiring layers are alternately laminated on a semiconductor substrate having a diffusion layer on the surface. The diffusion layer and the first wiring layer are interconnected through a connection hole provided in the insulating layer, and the second wiring layer passes over the connection hole. The connection hole, which is wider than the layer, is provided in a region through which the second wiring layer passes, and is provided outside the passing region of the plurality of connection holes arranged in the width direction of the second wiring layer and the second wiring layer. It is characterized in that it is divided into two connecting holes.

【0010】[0010]

【作用】上述の構成においては、接続孔の上を通る第2
の配線層が通過する領域で接続孔を複数に分割したこと
により、接続孔上の段差を横切らせていた第2の配線層
の一部が、段差の無い領域(分割された接続孔と接続孔
との間の領域)を通過するようになる。これにより、第
2の配線層の段切れや、抵抗増大化等が防止される。
In the above structure, the second passage that passes over the connection hole is used.
Since the connection hole is divided into a plurality of parts in the region through which the wiring layer passes, a part of the second wiring layer that has crossed the step on the connection hole has a step-free region (connects with the divided connection hole). The area between the holes). As a result, the disconnection of the second wiring layer and the increase in resistance are prevented.

【0011】また、第2の配線層より幅広の接続孔を複
数に分割する際に、接続孔の上を通る第2の配線層が通
過する領域外にも分割された接続孔が設けられている。
このため、第2の配線層が通過する領域で接続孔を複数
に分割したことに起因する、拡散層と第1の配線層との
間のコンタクト抵抗の増大という不都合は生じない。即
ち、接続孔を介する配線層間の接続特性は、接続孔の面
積のみならず周囲長に依存する。本発明のように、第2
の配線層が通過する領域で第2の配線層の幅方向に並ぶ
複数の接続孔と第2の配線層の通過領域外に設けられた
接続孔とに分割すると、面積は狭くなるが、周囲長が増
大するので、接続孔を小分割することによる接続特性の
劣化は殆ど問題とならない。
Further, when the connecting hole wider than the second wiring layer is divided into a plurality of connecting holes, the connecting hole is also provided outside the region where the second wiring layer passing above the connecting hole passes. There is.
Therefore, there is no inconvenience that the contact resistance between the diffusion layer and the first wiring layer is increased due to the division of the connection hole into a plurality of areas in the region where the second wiring layer passes. That is, the connection characteristic between the wiring layers via the connection hole depends not only on the area of the connection hole but also on the peripheral length. Like the present invention, the second
If a plurality of connection holes arranged in the width direction of the second wiring layer in a region through which the wiring layer passes and a connection hole provided outside the passage region of the second wiring layer are divided, the area is reduced, but Since the length is increased, the deterioration of the connection characteristics due to the subdivision of the connection hole hardly poses a problem.

【0012】また、接続孔を分割することによるパター
ンの追加やパターン面積の増大等を招くことがなく、さ
らに接続孔パターンの分割には、プロセスの変更を伴わ
うこともない。従って、レイアウトやプロセス等の変更
なしに、配線特性および信頼性の向上が図られる。
Further, the addition of a pattern or the increase of the pattern area due to the division of the connection hole does not occur, and the division of the connection hole pattern does not involve a process change. Therefore, the wiring characteristics and reliability can be improved without changing the layout or the process.

【0013】[0013]

【実施例】図3は本発明の一実施例に係わる半導体装置
の要部の構造を示す平面図である。なお、図1と同一部
分には同一符号を付して、その詳しい説明は省略する。
この実施例が先に説明した従来例と異なる点は、前記接
続孔4の代わりに複数の接続孔を形成したことである。
即ち、第1の絶縁層3には、第1の配線層5の長さ方向
に沿って4個の接続小孔8a,8b,8c,8dが直線
状に配列形成されている。
FIG. 3 is a plan view showing the structure of the main part of a semiconductor device according to an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.
This embodiment is different from the above-mentioned conventional example in that a plurality of connection holes are formed instead of the connection holes 4.
That is, in the first insulating layer 3, four connection small holes 8a, 8b, 8c, 8d are linearly arranged along the length direction of the first wiring layer 5.

【0014】ここで、本実施例においては接続孔によっ
て接続される拡散層2と第1の配線層5より上層側にあ
る第2の配線層7が通過する領域で、この第2の配線層
7より幅広の接続孔が、第2の配線層7の幅方向に並ぶ
接続孔8b,8cと第2の配線層7の通過領域外に設け
られた接続孔8aあるいは接続孔8dとに分割されてい
ることが重要である。
Here, in the present embodiment, in the region where the diffusion layer 2 connected by the connection hole and the second wiring layer 7 above the first wiring layer 5 pass, this second wiring layer is passed. The connection hole wider than 7 is divided into the connection holes 8b and 8c arranged in the width direction of the second wiring layer 7 and the connection hole 8a or the connection hole 8d provided outside the passage area of the second wiring layer 7. Is important.

【0015】このような構成であれば、第2の配線層7
の一部を段差のない領域を通過させることができる。即
ち、図3の孔8cを通る矢視B−B断面では、図2に示
す如く第2の配線層7は段差を横切るが、図3の孔8b
と8cとの間を通る矢視C−C断面では、図4に示す如
く段差のない領域を横切ることになる。従って、段差部
での段切れや膜厚減少等に起因する第2の配線層7の断
線や抵抗増大化を防止でき、配線特性及び信頼性の向上
を図ることができる。
With such a configuration, the second wiring layer 7
Can pass through a stepless region. That is, in the BB cross section taken through the hole 8c in FIG. 3, the second wiring layer 7 crosses the step as shown in FIG. 2, but the hole 8b in FIG.
In the cross-section taken along the line C-C as seen from the arrow passing through between No. 8c and No. 8c, as shown in FIG. Therefore, it is possible to prevent disconnection of the second wiring layer 7 and increase in resistance due to step disconnection at the step portion, reduction in film thickness, and the like, and it is possible to improve wiring characteristics and reliability.

【0016】なお、本発明は上述した実施例に限定され
るものではなく、その要旨を逸脱しない範囲で、種々変
形して実施することができる。例えば、前記接続孔の分
割数は4個に限るものではなく、適宜増減できる。
The present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention. For example, the number of divisions of the connection hole is not limited to four and can be increased or decreased as appropriate.

【0017】[0017]

【発明の効果】本発明によれば、拡散層と第1の配線層
とを接続するための接続孔を、この接続孔の上を通る第
2の配線層が通過する領域で複数に分割したことによ
り、接続孔上の段差を横切る第2の配線層の一部を段差
の無い領域を通過させることが可能となるので、第2の
配線層の段切れや抵抗増大化等を防止することができ
る。また、第2の配線層より幅広の接続孔を複数に分割
する際に、接続孔の上を通る第2の配線層が通過する領
域外にも分割された接続孔が設けられている。このた
め、第2の配線層が通過する領域で接続孔を複数に分割
したことに起因する、拡散層と第1の配線層との間のコ
ンタクト抵抗の増大という不都合は生じない。すなわ
ち、拡散層と第1の配線層間の接続特性は、接続孔の面
積のみならず周囲長に依存し、本発明のように、第2の
配線層が通過する領域で第2の配線層の幅方向に並ぶ複
数の接続孔と第2の配線層の通過領域外に設けられた接
続孔とに分割すると、その面積は狭くなるが、周囲長が
増大するため、接続孔を小分割することによる接続特性
の劣化は殆ど問題とならない。
According to the present invention, the connection hole for connecting the diffusion layer and the first wiring layer is divided into a plurality of areas in the region where the second wiring layer passing above the connection hole passes. As a result, it is possible to pass a part of the second wiring layer that crosses the step on the connection hole through a region having no step, so that it is possible to prevent disconnection of the second wiring layer and increase in resistance. You can Further, when the connection hole wider than the second wiring layer is divided into a plurality of portions, the connection hole is also provided outside the region where the second wiring layer passing above the connection hole passes. Therefore, there is no inconvenience that the contact resistance between the diffusion layer and the first wiring layer increases due to the connection hole being divided into a plurality of portions in the region where the second wiring layer passes. That is, the connection characteristics between the diffusion layer and the first wiring layer depend not only on the area of the connection hole but also on the peripheral length, and as in the present invention, the connection characteristics of the second wiring layer in the region through which the second wiring layer passes. If the connection hole is divided into a plurality of connection holes arranged in the width direction and the connection hole provided outside the passage area of the second wiring layer, the area becomes smaller, but the peripheral length increases, so the connection hole should be subdivided. The deterioration of the connection characteristics due to the above causes almost no problem.

【0018】また、接続孔を分割することによるパター
ンの追加やパターン面積の増大等を招くことがなく、さ
らに接続孔パターンの分割であるのでプロセスの変更も
伴わない。従って、レイアウトやプロセス等の変更なし
に、配線特性および信頼性の向上を図ることができる。
Further, there is no need to add a pattern or increase a pattern area by dividing the connection hole, and since the connection hole pattern is divided, the process is not changed. Therefore, it is possible to improve the wiring characteristics and the reliability without changing the layout and the process.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の半導体装置の要部の構造を示す平面図FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device.

【図2】図1の矢視A−A断面図FIG. 2 is a sectional view taken along the line AA of FIG.

【図3】本発明の一実施例に係わる半導体装置の要部の
構造を示す平面図
FIG. 3 is a plan view showing a structure of a main part of a semiconductor device according to an embodiment of the present invention.

【図4】図3の矢視C−C断面図FIG. 4 is a sectional view taken along the line C-C of FIG.

【符号の説明】[Explanation of symbols]

1…半導体基板 2…拡散層 3…第1の絶縁層 4…接続孔 5…第1の配線層 6…第2の絶縁層 7…第2の配線層 8a,8b,8c,8d…接続小孔 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Diffusion layer 3 ... 1st insulating layer 4 ... Connection hole 5 ... 1st wiring layer 6 ... 2nd insulating layer 7 ... 2nd wiring layer 8a, 8b, 8c, 8d ... Small connection Hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】表面に拡散層を有する半導体基板上に絶縁
層と配線層が交互に積層された多層配線構造を有し、前
記拡散層と第1の配線層とが前記絶縁層に設けられた接
続孔を通して相互接続され、この接続孔上を第2の配線
層が通過する半導体装置であって、この第2の配線層よ
り幅広の前記接続孔が、前記第2の配線層が通過する領
域で、前記第2の配線層の幅方向に並ぶ複数の接続孔と
前記第2の配線層の通過領域外に設けられた接続孔とに
分割されてなることを特徴とする半導体装置。
1. A multilayer wiring structure in which an insulating layer and a wiring layer are alternately laminated on a semiconductor substrate having a diffusion layer on the surface, and the diffusion layer and the first wiring layer are provided in the insulating layer. In the semiconductor device, the second wiring layer is interconnected through the connection hole, and the second wiring layer passes over the connection hole. The connection hole wider than the second wiring layer passes through the second wiring layer. A region is divided into a plurality of connection holes lined up in the width direction of the second wiring layer and a connection hole provided outside the passage region of the second wiring layer.
JP5240153A 1993-09-27 1993-09-27 Semiconductor device Expired - Lifetime JPH0783054B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5240153A JPH0783054B2 (en) 1993-09-27 1993-09-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5240153A JPH0783054B2 (en) 1993-09-27 1993-09-27 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1198338A Division JPH0624220B2 (en) 1989-07-31 1989-07-31 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP21762296A Division JP2693750B2 (en) 1996-08-19 1996-08-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06283608A JPH06283608A (en) 1994-10-07
JPH0783054B2 true JPH0783054B2 (en) 1995-09-06

Family

ID=17055289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5240153A Expired - Lifetime JPH0783054B2 (en) 1993-09-27 1993-09-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0783054B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5947474B2 (en) * 1975-10-31 1984-11-19 株式会社東芝 Hand tie souchi
JPS5556667A (en) * 1978-10-20 1980-04-25 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPH06283608A (en) 1994-10-07

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