JPH0783111B2 - Ultra high speed semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an ultra-high speed semiconductor device, and more particularly to an ultra-high speed semiconductor device based on a field effect transistor (FET) utilizing the resonant tunneling effect of a semiconductor ultrathin film structure. Get involved.

[Outline of Invention]

The present invention has a semiconductor ultrathin film structure in which a charge storage layer, a quantum well channel layer, and an intermediate potential barrier layer having a thickness capable of producing a resonance tunnel effect are disposed between these layers. The first and second electrodes are provided on the charge storage layer and the quantum well channel, and the gate portion is provided on the charge storage layer. The high speed FET operation is achieved by utilizing the resonance tunnel effect. is there.

[Conventional technology]

Recently, there is an increasing demand for the practical use of FETs that operate at higher speeds.

The operating speed of a general FET, such as a Schottky gate type FET or a junction gate type FET, is generally determined by the product of its gate capacitance, source resistance, or channel resistance. In other words, in this type of FET, the gate capacitance is changed by the change of the gate potential, and the charge / discharge operation of the carriers such as electrons corresponding to the change is performed through the source resistance or the channel resistance. And the channel resistance. Therefore, its operating speed depends on the channel length. This channel length is usually around 0.5 μm due to the manufacturing technology, that is, the restrictions on the gate processing accuracy, so the carrier transit time is shortened, that is, high-speed operation is actually restricted, and sufficient high-speed performance is achieved. Can't get

[Problems to be solved by the invention]

The present invention solves the problem of the restriction on the carrier travel distance due to the above-described gate processing accuracy.

[Means for solving problems]

In the present invention, a semiconductor ultra-thin film structure is adopted, and a carrier travel time is set substantially only by the time required for carriers to resonantly tunnel the potential barrier layer.

That is, in the present invention, as shown in FIG. 1, the charge storage layer (1), the quantum well channel layer (2), and the charge storage layer (1) and the quantum well channel layer (2).
It has a semiconductor ultra-thin film structure having an intermediate potential barrier layer (3) interposed therebetween.

The charge storage layer (1) is ohmic-deposited with a first electrode (4) or source electrode, and the quantum well channel layer (2) is ohmic-deposited with a second electrode (5) or drain electrode. It

Further, the charge storage layer (1) is provided with a gate portion (6), for example, a Schottky gate, and first and second electrodes (4) and (5).
It is formed on the part corresponding to the space.

The thickness L _B of the intermediate potential barrier layer (3) is equal to the first electrode (4),
The selection of the voltage applied to the second electrode (5) and the gate portion (6) causes a resonance tunnel between the charge storage layer (1) and the quantum well channel layer (2) due to the overlapping of the wave functions of the respective electrons. Thickness that can generate an electric current Specifically, L _B
300 Å, for example 25 Å ~ 50 Å. In the figure, S, D
Symbols G and G indicate source, drain and gate terminals.

[Action]

In the configuration of the present invention, by applying the required voltage V _DS between the source and drain S and D and the required voltage to the gate G, the charge from the charge storage layer (1) is transferred to the electron well channel layer (2). ) Is moved by a resonant tunneling action penetrating the thickness L _B of the intermediate potential barrier layer (3) under the gate part (6). By doing so, the transit time of the charge is This is a very short time required to substantially tunnel the thin intermediate potential barrier layer (3).

〔Example〕

Further, an embodiment of the present invention will be described with reference to FIG. In this example, the signal carrier is an electron, and
As shown in the band model diagram of the bottom of the conduction band in C, 2
This is the case where the structure has _two quantum wells W ₁ and W ₂ .
That is, one quantum well W ₁ is due to the quantum well channel layer (2), and the other quantum well W ₂ is due to the charge storage layer (1).

In this case, for example, a semi-insulating GaAs single crystal substrate (11) is provided, and a molecular beam epitaxy method called MB
E (Molecular Beam Epitaxy) method, or metal organic chemical vapor deposition (MOCVD) method
or Deposition) method, the lower potential barrier layer (7), the quantum well channel layer (2), the intermediate potential barrier layer (3) in which resonance tunneling can occur, the charge storage layer (1), and the upper layer The potential barrier layer (8) is epitaxially grown.

The quantum well channel layer (2) and the charge storage layer (1) are made of, for example, n-type GaAs, and the potential barrier layers (7), (3) and (8) are made of undoped Al GaAs. That is, the potential barrier layers (7), (3) and (8) are made of a semiconductor layer having a larger band gap and a higher level of the bottom of the conduction band than the charge storage layer (1) and the quantum well channel layer (2). Constitute.

The thicknesses of the charge storage layer (1), the quantum well channel layer (2), and the intermediate potential barrier layer (3) between them enable electron confinement in each quantum well, and further provide a required voltage to each part. Each thickness that can cause resonant tunneling when applied from the outside, for example, 30 in the intermediate potential barrier layer (3)
The thickness of each layer (1) to (3) is 25Å to 50Å
Can be selected.

The impurity concentration of the charge storage layer (1) is, for example, 10 ¹⁸ cm ^-3.
You can select it for your order.

On the upper potential barrier layer (8), a Schottky metal such as Al or Au that forms a Schottky junction thereto is formed.
A gate portion (6) is formed by depositing a gate electrode (9) made of And on the one side across this gate part,
A first electrode alloyed to a depth reaching the charge storage layer (1),
That is, the source electrode (4) is provided, and on the other side, the potential barrier layer (8) and the charge storage layer (1) are partially removed by etching to remove the second electrode, that is, the drain, in the quantum well channel layer (2). An electrode (5) is provided.

According to such a configuration, by applying a required voltage to the gate G in a state where the required voltage V _DS is applied between the source S and the drain D, the charge storage layer (1) is moved to the intermediate potential barrier. A channel portion (13) can be generated by resonance tunneling across the layer (3) and can be directed to the quantum well channel layer (2), and an ON operation between the source S and the drain D can be performed. become. This will be described with reference to the band model diagrams of FIGS. In this figure, E _G and E ₁ , E _2, ... Are the ground level of electrons in each quantum well W ₁ and W ₂ by the quantum well channel layer (2) and the charge storage layer (1), and n = 1,2
Each energy level of ... is shown. FIG. 2A shows each terminal S,
It shows a state where no electric potential is applied to D and G from the outside. At this time, no resonance tunnel occurs between the quantum wells, that is, the intermediate potential barrier (3), and electrons (carriers) are localized in each well. Has been done. In this structure, when a positive voltage is applied to the drain D with respect to the source S, a potential gradient is generated in the intermediate potential barrier layer (3), but the voltage V _DS between the source S and the drain D is applied to the gate G, for example. In the off-voltage state in which no external voltage is applied, as shown in the band model diagram of FIG. 2B, the potential barrier (3) is still selected so that resonance tunneling does not occur. And with this voltage V _DS selected,
By applying a required negative on-voltage to the gate G, as shown in the band model diagram of FIG. 2C, the ground level E _G in the quantum well W ₂ of the charge storage layer (1) only under the gate electrode. There overlap, for example, E ₁ of the quantum level of the quantum well W ₁ in the quantum well channel layer (2), coupling and resonance level of the antibonding state shown by broken lines in FIG C occurs, both quantum well W ₂ and W _As shown by an arrow a, a movement of electrons penetrating the potential barrier layer (3), that is, a resonance tunnel current is generated between 1 and the source S and the drain D are turned on. Since the tunnel current is generated in a spike shape, its on / off operation is extremely fast and can reach f _T = 1000 GHz.

Further, the tunnel charge at this time may be on the order of 10 ¹⁷ cm ^-3 if the impurity concentration of the charge storage layer (1) is on the order of 10 ¹⁸ cm ^-3 .

As described above, according to the device of the present invention, by selecting the voltage V _DS between the source S and the drain D at a required voltage, it is possible to perform the on / off operation at a very high speed with a minute voltage applied to the gate G.

In the above example, the configuration has two quantum wells W ₁ and W ₂ , but the quantum well channel layer (2) has only the well W ₁ and the charge storage layer (1) is It is also possible to use a layer having a relatively high impurity concentration capable of supplying electric charges and providing a gate portion (6) of, for example, a Schottky gate, on this layer.

Further, although the above-described example has been described with respect to the case where the mobile carrier is an electron, it can be applied to the case where a hole is used as the mobile carrier, and in this case, the conductivity type of each part may be selected in the opposite manner to the above.

In the above example, the ultrathin semiconductor structure may be a combination structure of GaAs and Al GaAs, but it may be a combination structure of InAs and AlGaSb.

Further, not limited to the example described above, various modified structures can be adopted such as a structure in which a plurality of quantum well channel layers (2) are arranged.

〔The invention's effect〕

As described above, in the device of the present invention, the movement of carriers is a gate portion utilizing resonance tunnel development in the ultra-thin film semiconductor structure, that is, a FET structure having a control electrode, so that it is significantly higher than the conventional FETs. This enables high-speed operation.

[Brief description of drawings]

FIG. 1 is an enlarged schematic cross-sectional view of an example of an ultrahigh-speed semiconductor device according to the present invention, and FIGS. 2A to 2C are band model diagrams used for explaining the operation of the device of the present invention. (1) is a charge storage layer, (2) is a quantum well channel layer,
(3) is a potential barrier layer, (4) and (5) are first and second
, And (6) is a gate part.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 29/812

Claims (1)

[Claims] 1. A semiconductor comprising: (a) a charge storage layer; (b) a quantum well channel layer; (c) an intermediate potential barrier layer interposed between the charge storage layer and the quantum well channel layer. An ultra-thin film structure, (d) a first electrode is provided on the charge storage layer, (e) a second electrode is provided on the quantum well channel layer, (f) the charge storage layer, The first electrode and the second
A gate portion is provided at a position corresponding to the gate electrode, and (g) the thickness of the intermediate potential barrier layer depends on the selection of the voltage applied to the first electrode, the second electrode, and the gate portion. An ultrahigh-speed semiconductor device, characterized in that the charge storage layer and the quantum well channel layer are selected to have a thickness that can generate a resonant tunneling current due to overlapping of wave functions.