JPH0783124B2 - Method for manufacturing self-aligned semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION An effective method of manufacturing a semiconductor device has been developed in a semiconductor layer.
Including one or more successive dopings to set one conductivity type region in a second region of opposite conductivity type that is itself in a layer of one conductivity type. well known. It is desirable to match the various regions to the desired relationship so that the manufactured device has the correct function. In practice, it is difficult to precisely match the two regions using available semiconductor technology, and thus the manufactured device may not work as intended. One example of such a device is an insulated gate transistor in which a first region of opposite conductivity type is disposed within a second region of one conductivity type, the second region being a layer of opposite conductivity type. It is located inside. Insulated gate electrode in the layer,
The layer and the first portion are arranged at the same position as a part of the second region.
The carriers of one conductivity type are conducted between the regions.

However, these insulated gate transistors may cause parasitic bipolar transistors in the device to turn on undesirably if, for example, a short circuit between the source and the base is inadequate or if the sheet resistance of the base is too low. There is a fear of operating in an unfavorable mode. Parasitic
A second deep P + diffusion in the NPN structure is used to improve the sheet resistance of the base of the device and reduce the sheet resistance of the P-type base layer, while at the same time source and lightly doped P.
Good contact between the shaped base regions has been proposed. This deep P + type diffusion, combined with the lightly doped shallow base diffusion, determines the channel characteristics of the device.

Due to the need to carefully align the source region with the base region in order to advantageously use a deep P + base in the device and to provide a device with a commercially acceptable current density. The difficulty in making this deep P + diffusion was a limitation of conventional insulated gate transistors. Conventionally, one mask was used to limit only two separate regions, so that it was not possible to precisely align the two separate regions.
A misalignment had to occur and the device had to be shaped to accommodate this integer deviation. Specifically, misalignment of the source and base regions in the insulated gate transistor results in a longer current path along the junction between the source and base regions, and thus a voltage along the junction. The drop increases and contributes to the voltage drop across the junction. When breakdown occurs at this junction, the parasitic transistor turns on,
You cannot control the gate of the device. Therefore, it is desirable to minimize undesired junction lengths as well as the dimensions of regions of the device and to precisely align each region of the device to avoid undesired voltage breakdown.

OBJECT OF THE INVENTION The main object of the present invention is to provide a new and improved method of manufacturing a semiconductor device.

Another object of the invention is to provide a method of manufacturing a semiconductor device in which two or more regions of the device are set in a precisely aligned relationship with each other.

Further, the present invention sets up an insulated gate device in which two or more device regions are self-aligned.

Another object of the present invention is to provide an improved method of manufacturing an insulated gate semiconductor device having improved resistance to unwanted latch-up.

Another object of this invention is to treat the photolithographic masks differently so that the protective layers of the device are precisely aligned with each other and set up three precisely aligned regions. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be divided into three separate regions. Thus, the present invention eliminates the need to establish a precise alignment between photolithographic masks applied one after the other to the surface of the substrate of the device.

Another object of the present invention is to open a window in the first portion of the first protective layer to expose the first portion of the semiconductor substrate and
A method of manufacturing an improved insulated gate semiconductor device is provided that defines a second central portion of the protective layer and an unexposed portion of the underlying semiconductor substrate. The third, non-exposed portion of the first protective layer is also limited to surround the first and second portions.

SUMMARY OF THE INVENTION The above and other objects and features of a preferred embodiment of a method of manufacturing a self-aligned insulated gate semiconductor device according to the present invention include providing a semiconductor substrate and setting a first protective layer on the substrate. To be achieved. A first window is opened in the first portion of the first protective layer to expose the first portion of the surface of the substrate. The first window has a second portion of the first protective layer and an unexposed second portion of the underlying substrate.
Is limited to the circumferential direction. A third portion of the first protective layer surrounds the first and second portions of the first protective layer. One or more regions can be formed in the first portion of the substrate through the first window with precise alignment. A third portion of the first protective layer is coated with a corrosion resistant material and a second window is opened in the second portion of the first protective layer. One or more regions can be set in the second part of the substrate in precise alignment with each other and with the regions set via the first window.

In a preferred method of manufacturing a self-aligned semiconductor device, such as an insulated gate semiconductor device, another object and feature of this invention is to provide a semiconductor device, such as a silicon substrate, having a resistivity of about 5 ohm / cm. To be achieved. The substrate is covered with a first protective layer. This protective layer can be deposited, for example, on the oxide layer. In another preferred embodiment, the step of setting a first protective layer sets a first insulating layer, such as a native oxide, upon which a layer of gate electrode material such as a polysilicon layer is deposited. And confine the gate layer in a second insulating layer, such as a second oxide layer, and then deposit a nitride layer on the second insulating layer. A first protective layer is formed on the first protective layer using, for example, a reactive ion etch.
Window to expose the first portion of the substrate. A first window circumferentially defines a second central portion of the substrate beneath it. A first doping is performed on the substrate through the first window, for example by diffusion or implant doping to set the first region. A second protective layer is formed in the first window over the exposed portion of the substrate, for example by growing a native oxide in the first window. It is important that the first protective layer can be removed by an etching method that does not remove the second protective layer. Generally, because of this condition,
The first and second protective layers are required to be different materials, such as nitride and oxide materials. A second window is opened in the second part of the first protective layer by photolithography, thus for example for the material in the second part of the first protective layer which overlaps the second part of the substrate. But the second
The unexposed second central portion of the substrate is exposed by etching using an etch that is ineffective against the protective material forming the protective layer. A second doping is performed on the substrate through the second window, for example by implanting or diffusion doping, to define the second region. Therefore, the first and second regions are set with a predetermined relationship or matching relationship, and in the preferred embodiment, this relationship is symmetrical.

As will be described in more detail below, a first photolithographic mask is used to set boundaries for the windows of FIGS. 1 and 2 and thus separate the first protective layer and the substrate into three separate areas, namely a second window. An inner area of the window, a central area of the first window, and an outer area that lies outside and surrounds the first window. By setting a first window in the first part of the protective layer, which confines the unexposed second part of the substrate in the circumferential direction, the first region is made to be the first protective layer. The same or underlying conductivity type in the substrate by masking with a second protective material that is resistant to the cut or etch used to remove the protective material overlying the second portion. The first and second areas can be set.

This method, for example, forms a third protective layer in the second window, removes the second protective layer, and performs a third doping on the substrate to set a matched third region. By doing so, it can be expanded further. Alternatively, the second protective layer can be removed and a third doping can be performed on the first and second regions. In a preferred embodiment, the first region can be set up by diffusing a high concentration of slow-diffusing opposite conductivity type material into the opposite conductivity type substrate, and the second doping is performed with one conductivity type. The third doping can be set by a material having a fast diffusion type and the third doping can be set by a light doping using a material of one conductivity type having a fast diffusion. A metallization layer may be applied to the surface of the substrate that overlaps a portion of the first and second regions so as to make ohmic contact with the first and second regions to establish an electrical short between them.
In the preferred embodiment, the third window is co-located with the first window, and in another preferred embodiment, the third window is the first and second windows.
It is in the same location as both windows.

In another preferred embodiment, approximately 5 ohms are used to fabricate a self-aligned semiconductor device such as an insulated gate semiconductor device.
Prepare a substrate such as a silicon substrate with a specific resistance of / cm,
The substrate is covered with a first protective layer. The protective layer may be composed of an oxide layer, the gate electrode being disposed on the first oxide layer and the second oxide layer gate electrode. The second oxide layer in combination with the first oxide layer,
Enclose the gate electrode. A second passivation layer, such as a nitride layer
Can be placed on top of the insulating layer. Opening a first window in the first portion of the first protective layer to expose the surface of the first portion of the substrate and inscribe the second portion of the first protective layer,
Limit the unexposed portion of the underlying substrate. The first window defines the area of interest, for example using a photolithographic mask system, and then an appropriate etch is applied to the nitride, metal and oxide materials that make up the first protective layer. Remove (if it exists). Then, before doping the first region, a second protective layer, such as an oxide, is placed in the first window, which can consist of silicon dioxide, for example. The material of the first protective layer, which is outside the first window, can be coated with a corrosion resistant material such as photoresist and a specific etch to the material can be used to remove the second protective layer. Instead, the circumferentially confined second portion of the first protective layer is removed, thus exposing a previously unexposed second portion of the substrate. First through the second window
Doping is performed, and the first region is set by, for example, a diffusion or implantation method using a high-concentration material of one conductivity type that has a fast diffusion. A third protective coating, such as a nitride material, is placed in the second window and then a third window is drilled in the area of the first window to expose the third portion of the substrate. The third window can be set by using a specific etch for the material of the second protective layer. A second doping is performed through the third window, for example in combination with a diffusion or implantation scheme, to set the second region by using a lightly doped material of one conductivity type with a faster diffusion.
After this, a third doping is performed through the third window,
The third region is set, for example, by using a slow-diffusing, high-concentration material of the opposite conductivity type, in combination with a conventional diffusion or implantation scheme. After this, a fourth protective layer, such as an oxide layer, is set in the third window and, for example, the previously set third protective layer is etched to form the first, second and third protective layers. The fourth window can be set within the area of the second window by exposing a portion of the area. A metallization layer can be applied to the first, second and third regions through the fourth window to establish a short circuit between the first, second and third regions. Preferably, the area of the fourth window is co-located with the area of the second window and the area of the third window is co-located with the area of the second window.

Another preferred embodiment of the self-aligned semiconductor device of the present invention, such as an insulated gate semiconductor device, is, for example, 5 ohm / c.
It can be manufactured by preparing a semiconductor substrate made of a silicon material having a specific resistance of m. A first protective layer is arranged on it. The first protective layer is a first protective layer such as an oxide layer.
An insulating layer, a gate electrode disposed on the first insulating layer, and a second insulating layer, such as an oxide layer, surrounding the gate electrode and engaging the first insulating layer. Is preferred. A nitride passivation layer can be disposed on the second insulating layer. Then, a first window is opened in the first portion of the first protective layer by a normal photolithography mask and etching method to expose the first portion of the substrate and
The second portion of the protective layer and the underlying, unexposed second central portion of the substrate are circumferentially limited. The first window is preferably opened by sequentially using different etches to remove previously deposited material such as oxide, nitride and polysilicon. First
The first doping is performed through the window of the first, and the first doping is performed by using the lightly doped material of one conductivity type having slow diffusion.
Regions can be set up to create a lightly doped first region with one conductivity type. Then, a second protective layer is placed in the first window, which can consist of, for example, a native oxide. The material of the first protective layer outside the first window can be coated with a corrosion resistant material such as photoresist. First, apply undeveloped photoresist to the entire top surface. The entire second portion of the first protective layer and a portion of the second protective layer are covered with a loosely fitted mask. The photoresist is exposed and the photoresist is developed so that the masked portions are removed, leaving the unmasked portions with some of the first portions.

A second window is opened in the second portion of the first protective layer to expose the unexposed central portion of the substrate, and a high-concentration material of one conductivity type having a fast diffusion is used to form a second window. A second doping of the substrate is performed through the window to set a second region having one conductivity type. Then a third, like a natural oxide
A protective layer can be placed in the second window. The previously deposited photoresist layer can be removed and a third window can be opened in the second protective layer by, for example, a photolithographic mask and etching scheme to expose a portion of the first region. After that, the first region is sequentially doped with a high-concentration material having a slow diffusion and an opposite conductivity type,
A third region of opposite conductivity type can be set. Third
It is preferred that the window of is co-located with the first window.

In yet another preferred embodiment, the self-aligned insulated gate semiconductor device of the present invention can be manufactured by preparing a semiconductor substrate of silicon material having a specific resistance of, for example, 5 ohm / cm. The first protective layer includes a first insulating layer, such as a natural oxide, a gate electrode disposed on the insulating layer, and encapsulating the gate electrode to engage the first insulating layer. It is preferably composed of a second insulating layer such as a natural oxide. A nitride passivation layer can be disposed on the second insulating layer. Then, a first window is opened in the first portion of the first protective layer to expose the first portion of the substrate and the second portion of the first protective layer is formed by a conventional photolithography mask and etching method. And the underlying unexposed second central portion of the substrate is circumferentially limited. The first window is to use an etch, such as a reactive ion etch, one after the other to remove the already deposited material of the first protective layer consisting of, for example, oxides, nitrides and polysilicon. Open by The first doping is performed through the first window, the first region is set using a lightly-concentrated material of one conductivity type having a fast diffusion, and one conductivity type is set in the first region. Create a lightly doped first region to hold. After this, second doping is performed through the first window to set a second region of opposite conductivity type. In the preferred embodiment, the second region can be established by using a high concentration material of slow diffusion, opposite conductivity type in combination with conventional implantation and diffusion doping schemes. Then, a second protective layer that is different from the exposed material of the first protective layer is placed in the first window. It can consist, for example, of an oxide layer. A portion of the first protective layer, which is outside the first portion of the first protective layer, can be coated with a corrosion resistant material such as photoresist. For this reason, a loosely fitted mask is used that overlaps the second protective layer but does not overlap the second portion of the first protective layer. A second window is opened in the second portion of the first protective layer to expose the unexposed second central portion of the substrate.
A high concentration material of one conductivity type with a fast diffusion is used to perform a third doping of the substrate through the second window to set a second base region having one conductivity type.

The present invention thus provides an improved method of manufacturing a self-aligned semiconductor device. In particular, the improved method of manufacturing the semiconductor device of the present invention can be used to manufacture various insulated gate semiconductor devices such as insulated gate transistors, MOST controlled thyristors and MOSFETs. This improved manufacturing method allows the regions of the various devices to be precisely aligned, which requires the setting of zones for tolerances within the regions of the device, as well as the tolerances for misalignment between successive masks. The device can be manufactured without the need to create larger sized areas as would be required for The invention allows the device to be manufactured with tight tolerance limits. Further, the method of manufacturing the insulated gate semiconductor of the present invention allows all available semiconductor locations to be utilized, thus maximizing the performance of the device configured on various chips. To do.

While the features of the invention believed to be novel are set forth with particularity in the appended claims, the construction and operation of the invention itself, as well as other aspects of the improved method of fabricating a self-aligned insulated gate semiconductor device, are described. The features, objects and advantages will be best understood from the following detailed description of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1a to 1f are sectional views showing successive steps of the method of the first preferred embodiment of manufacturing a self-aligned insulated gate semiconductor device according to the present invention, and FIGS. 2a to 2g are the same. Sectional views showing successive steps of a method of a second preferred embodiment for manufacturing a self-aligned insulated gate semiconductor device according to the invention, FIGS. 3a to 3e show a third method for manufacturing a self-aligned insulated gate semiconductor device according to the present invention. FIGS. 4a to 4c are sectional views showing successive steps of the method of the preferred embodiment, and FIGS. 4a to 4c are sectional views showing successive steps of the method of yet another preferred embodiment of manufacturing a self-aligned insulated gate semiconductor device according to the present invention. .

Detailed Description of the Preferred Embodiments The improved method of manufacturing the self-aligned insulated gate semiconductor device of the present invention can be used in a wide range of semiconductor devices that can be made with a variety of semiconductor devices. In the following description, the silicon device or the device manufactured in the silicon substrate constitutes the self-aligned semiconductor device of the present invention configured on the silicon substrate in order to constitute the overwhelming majority of semiconductor devices currently available. Some preferred embodiments of the improved method of For this reason, the most common use of the invention is a silicon substrate. However, it is recognized that the invention described herein can be used with other semiconductor materials such as germanium or gallium arsenide, and that the method of the invention is equally applicable to these other semiconductor technologies. I want to be done. Therefore, the application of the present invention is not limited to a device manufactured on a silicon substrate, and the method described here is applicable to any of a large number of semiconductor materials and devices manufactured by any similar method. It also extends.

Further, although this specification describes the case of an insulated gate semiconductor device having three regions, this disclosure is a preferred embodiment of the present invention and does not limit the scope of use of the present invention. I want you to understand. Furthermore, the example shown here illustrates an improved method of manufacturing a self-aligned insulated gate semiconductor device in combination with an insulated gate transistor (IGT), although the invention is not limited thereto. Metal oxide semiconductor field effect transistor (MO
It should be appreciated that it can also be used in other insulated gate semiconductor devices, including SFETs) and MOS controlled thyristors (MCTs). Further, while the present invention precisely aligns various regions of the device, such as to increase the latch threshold of a particular device, the method of the present invention reduces cell size and cell repeat distance. It should be appreciated that it provides other advantages associated with precise bonding of device areas, including the ability to shrink, resulting in improved cell and current densities.

It is believed that the description of the invention will be easier to understand once the correspondence of the devices shown in FIGS. 1 through 4 is known, and therefore corresponding regions, layers and parts will be designated by the same reference numerals.
However, various parts of the semiconductor device are not drawn to scale. Certain dimensions have been exaggerated relative to other dimensions in order to more clearly illustrate and understand the present invention. By way of example, a preferred embodiment of the improved method of manufacturing a self-aligned insulated gate semiconductor device in accordance with the present invention is shown, with each particular embodiment including specific P and N type regions, Those skilled in the art will appreciate that what is described herein may be similarly applied to insulated gate semiconductor devices with opposite conductivity types in various regions, such as to make the same device. Ah Furthermore, although the illustrated embodiment is shown in a two-dimensional vertical cross-section, these regions only represent a portion of one cell of the device, and the device was actually arranged in a three-dimensional structure. Note that it is composed of multiple cells. Therefore, these regions, when manufactured in an actual device, form a plurality of regions having three dimensions, each of which has a length, a width, and a depth, and these regions have the two dimensions shown in the figure. The device is obtained by rotating the device about a vertical axis passing through the centerline of the second portion 30 of the first protective layer 14 to be described.

Referring now to FIG. 1, successive steps of a preferred embodiment of the method of manufacturing a self-aligned semiconductor device according to the present invention are shown in FIGS. 1a-1g. First, a first silicon wafer having a thickness of about 20 mils, a resistivity of about 5 ohms / cm, and doped with carriers of opposite conductivity type to a concentration of about 10 ¹⁵ carriers / cc. A semiconductor layer or substrate 10 is prepared. This carrier is shown in the drawings as a carrier having an N-type conductivity. Alternatively, the substrate 10 may be a semi-finished semiconductor wafer composed of a plurality of layers having one or the opposite conductivity type. As shown in FIG. 1a, the substrate 10
A first protective layer 14 is provided on top of. In one embodiment, the first protective layer 14 comprises a first protective layer 14 that may be composed of, for example, a natural oxide.
A first insulating layer 16, a gate electrode layer 18 and a gate electrode layer 18 such as polysilicon disposed on the first insulating layer 16.
The second insulating layer 20 may be included together with the insulating layer 16 of FIG. The second insulating layer 20 may be a native oxide of polysilicon gate material. It is also possible to provide the nitride layer 22 on the second insulating layer 20. The first window 25 of the first protective layer 14 may be a first window 25, which may be annular or ring-shaped, for example.
Put in the part of. By removing this, the first portion 27 of the surface of the substrate 10 is exposed and the second portion of the first protective layer 14 is removed.
The central portion 30 and the underlying unexposed portion 31 of the surface of the substrate 10 are circumferentially limited. The first window 25 is outside the first window 25 and the third portion 32 of the first protective layer 14 is located.
And also the underlying third portion 32a of the surface of the substrate 10. Thus, the first window 25 divides the first protective layer 14 and the underlying substrate 10 into three separate areas or surface portions.

Using photolithography in combination with an imaging material such as an external mask, the mask is defined by photolithography on the top surface 15 of the first protective layer 14, which is then developed into a first mask. Window 25
The portion of the first layer 14 for opening can be limited. After this, an etch such as a reactive ion etch is used to etch each of the nitride, metal and oxide layers 22, 20, 18 and 16 that make up the first protective layer 14, resulting in
The structure is shown in Figure 1a.

Once the first window 25 is opened and the first portion 27 of the substrate 10 is exposed, the substrate 10 is first doped through the first window 25 to form a first region 35. You can When manufacturing MOSFET devices, a heavily doped material of slow diffusion, opposite conductivity type, such as arsenic, is used in combination with conventional implantation or diffusion schemes, shown as a region with N-type conductivity. It is preferable to set one opposite conductivity type region 35.

Thereafter, as shown in FIG. 1b, the first window 35 is formed on the first region 35 on the exposed first surface portion 27 of the semiconductor substrate 10.
A second protective layer 36 is set within 25. The second protective layer 36 is
For example, in the case of a silicon substrate, it can be a natural oxide such as silicon dioxide. It is particularly preferred that the material of the second protective layer 36 is different from the material of the first protective layer 14, or at least the material constituting its exposed surface. In the illustrated example, the upper surface 15 is composed of the nitride layer 22. This criterion must be satisfied in order to remove one material of the first or second protective layers 14 and 36 and not to remove the other material. Therefore, the first protective layer 14 can be differentially etched with respect to the second protective layer 16. Or vice versa.

Next, referring to FIG. 1c, of the first protective layer 14,
In order to open the second window without removing the third portion 32 outside the first window 25, a photoresist layer 33 is deposited on the surface of the device to remove the first and second protective layers. Can be covered.
After this, a second loosely fitted mask (not shown) is used to remove the second central portion 30 of the first protective layer 14 and the second protective layer 36 of the photoresist layer 33. It is possible to remove a portion that overlaps a part.

Referring to FIG. 1d, after this, a second window 37 is opened in the second portion 30 of the first protective layer 14 to react with, for example, the material of the first protective layer 14 to remove it. , The second protective layer
A selective etch that does not remove all 36 material is used to expose the previously unexposed second portion 31 of the substrate 10. In the illustrated example, the second protective layer 36 is composed of silicon dioxide and the first protective layer 14 is composed of a silicon nitride layer 22 overlying the oxide layer 20, which is a polysilicon layer. Overlying the gate layer 18, which is overlying the silicon oxide layer 16. After this, a reactive ion type etch is used to remove the second portion 30 of the first insulating layer 14 and only the second portion 30 of the first protective layer 14, You can open the second window 37.

After this, the second portion of the surface of the substrate 10 through the second window 37
A second doping is performed on 31 to set a second region 38 having one conductivity type, shown as a P + type region. In the preferred embodiment, the second doping is done by using a high-concentration material of one conductivity type, such as boron, in combination with a conventional implantation or diffusion scheme.

Thereafter, as shown in FIG. 1e, the photoresist layer 33 is peeled off, and the second protective layer 36 is removed by, for example, a buffered hydrofluoric acid etching method to remove the first and second layers on the surface of the substrate 10, respectively. It is possible to expose the portions 27 and 31 of the above and to expose the first and second regions 35 and 38 respectively set therein. After that, a third dopant 40 having one conductivity type can be set by performing a third doping using a lightly doped dopant having one conductivity type having a high diffusion rate such as boron. First
The contact electrode 60 as shown in FIG. 1f is provided in the first and second regions of the device.
It can be deposited in the usual manner in ohmic contact with 35,38 to short the junction between the regions of FIGS. 2 and 1 and inhibit the junction from being forward biased.

In the insulated gate embodiment of the invention shown in Figure 1f,
The lightly doped third region 40 is a portion of the third region 40.
41 is set to extend under the first protective layer 14. Third
The portion 41 of the region extending under the first protective layer 14 can be referred to as a channel region 41. This is because the gate electrode 18 sets up a channel in the channel region 41 of the third region 40 in response to an appropriately applied bias voltage and is opposite between the first region 35 and the substrate 10. This is because it facilitates the flow of conductive carriers. The channel area 41 is
The substrate 10 diffuses laterally under the first protective layer 14 and
It can be formed underneath the first protective layer 14 by doping the second region 38 with a material that diffuses vertically downward into. The first protective layer 14 preferably overlaps the channel region 41 and is in contact therewith. Furthermore, it is preferable that the first protective layer 14 overlap the entire circumference of the channel region 41.

The first window 25 and the areas of the first, second and third devices are
The horizontal cross section is preferably circular.

By the self-aligning method of manufacturing the insulated gate semiconductor device according to the present invention, the first source region 35 is precisely defined with respect to the second and third regions 38 and 40, which are hereinafter referred to as the base region 38 and the base attachment region 40, respectively. Note that they are arranged in a limited relationship. First region 35 is substrate 10
In combination with the third region 40 below the first protective layer 14.
The channel region 41 is limited to the inside. Layer 14 is formed as an insulated gate electrode. The distance between the first region 35 and the substrate 10 or the width of the third region 40 close to the surface of the substrate defines the channel length. Therefore, precise alignment between the first, second and third regions 35, 38, 40 is desirable.

In addition, a heavily doped second region 38 is provided to minimize the voltage drop along the PN junction between the first region 35 and the second and third regions 38, 40 to allow one conductivity The flow of mold carriers through the second and third regions 38, 40 to the short circuit electrode 60 reduces the likelihood of a voltage drop of greater than 0.7 volts along the junction. When a voltage drop of more than about 0.7 volts occurs along this junction, the inherent parasitic NPN formed by the first region 35, the second / third regions 38/40 and the substrate 10.
The transistor is activated. By setting the various areas of the device in close relationship to each other, the undesirable consequences of this parasitic transistor being activated are reduced.
This precise alignment is possible due to the use of a single annular or donut-shaped mask set on the first protective layer 14 by photolithography.
However, the relative dimensions, depths and relationships of the first, second and third regions 35, 38, 40 are not limited to the shape of the mask but also to the appropriate doping material and process conditions for applying this doping material. It is also related to how to choose. Many manufacturing parameters vary with the type and conductivity of the device being set. The effects of different process parameters on setting different areas of equipment have been discussed in many publications, including John Wiley and
AS Grove author "The Physics and Technology of Semiconductor Devices" published by Sands, Inc. and Beadle et al. It's Circid Technology ". However, in the preferred embodiment of the present invention, process parameters generally as described below can be used. Device area parameters First oxide layer 16 (thickness) 1,000Å Gate electrode 18 (thickness) 1 micron Second insulator 20 4,000Å Nitride layer 1,000Å First area 10 ¹⁷ atoms / cm ³ Dopant Second region 10 ¹⁷ atoms / cm ³ dopant Third region 10 ¹⁵ atoms / cm ³ dopant Second protective layer 4,000Å FIGS. 2a to 2f show an insulated gate semiconductor device according to the present invention. Another preferred embodiment self-aligning method of manufacture is shown. In this embodiment, first the first window 25 is opened in the first portion of the first protective layer 14 to form the protective layer 14
The second portion 30 and the unexposed central portion 31 of the surface of the underlying substrate 10 are circumferentially limited. The first window also defines a third portion of the first protective layer that is outside the first window 25. First, the second protective layer 36 is set in the first window 25. Removing the second portion 30 of the protective layer 14,
A deep P + type base region 38 can be set, a P- type base attachment region 40 is also set after this, and finally a first N + type source region 35 is set. Therefore, the method of manufacturing the insulated semiconductor device according to this embodiment in a self-aligned manner is such that the step of setting the base and source regions of the device is rearranged from the steps described above with reference to FIGS. 1a to 1f. is there.

Specifically, another preferred method of manufacturing a semiconductor device in a self-aligned manner is to prepare a semiconductor substrate 10 and cover the surface of the substrate with a first protective layer 14 as shown in FIG. 2a. . A first window 25 is opened in the first protective layer 14 to expose a first portion 27 of the surface of the substrate 10 and the first protective layer 14
The second portion 30 of the is restricted circumferentially. A third portion 32 of the first protective layer 14 where the first window 25 is outside the first window 32.
Is also limited. After this, as shown in FIG. 2b, a second protective layer 36 made of a material that can be differentially etched with respect to the material of the first protective layer 14, such as a natural oxide, is formed on the first window.
Provide in 25. A photoresist layer 33 can then be deposited over the third portion 32 of the first protective layer 14 and over a portion of the second protective layer 36 by using a loose fit mask. Then, as shown in Figure 2c, the first
A second window 37 is opened using a differential etch throughout the second portion 30 of the protective layer 14 to expose the second portion 31 of the surface of the substrate 10. The substrate 10 is first doped with one conductivity type carrier to set a base region 38, shown as a deep P + type region. After this, as shown in FIG. 2d, a third protective layer 45 is set in the second window 37 by growing a natural nitride such as silicon nitride Si ₃ N ₄ .

The third window shown in FIG. 2e is then formed in the region of the first window 25 by removing the previously provided second protective layer 36, for example using a suitable differential etch. Opening exposes a first portion 27 of the surface of the substrate 10, including a surface portion of the base region 38 and a surface portion of the undoped substrate 10. Then a second doping is performed through the third window to form a lightly doped P-type base extension,
Set up a lightly doped base attachment region 40 with one conductivity type shown in Figure 2e. After that, the source region 35 is set by performing the third doping using the material of the opposite conductivity type through the same third window. This source region is shown as a region having a strongly doped N + type conductivity type.

The fourth protective layer 50, shown in FIG. 2f, is advantageously composed of a natural oxide such as silicon dioxide, which can be grown in the third window.

This is followed by a third protective layer, for example using a differential etch.
By removing 45, a fourth window 44 is opened in the third protective layer 45 located in the second window 37, as shown in Figure 2g, the base region, the base attachment region and the source region. 38,40,
Can expose part of 35. In the preferred embodiment, a metallization layer (not shown) in the fourth window 55.
To short the source region 35 to the base region 38/40 of the device, thus turning on the parasitic transistor,
Reduce the likelihood that the device will operate in a manner other than the preferred one.

In another preferred embodiment of the method shown in FIG. 2, base diffusion is performed as shown in FIG. 2c to provide a P + type base region.
Set 38, ending with a particularly strong surface concentration. The third protective layer 45 in Figure 2d is not provided. Instead, the second protective layer 36 is removed to expose the first and second portions 27, 31 of the surface of the substrate 10. A first doping is performed to set the base attachment region 40 using a lightly-concentrated material having one conductivity type such as boron, which has a high diffusion rate. Perform another doping using a high concentration material with slow diffusion opposite conductivity type,
Set the N + type source region 35. Doping of the N + type source region is preferably performed by implantation to reduce the surface concentration of the opposite conductivity type and avoid significantly reducing the ohmic contact capability of the central P + type region 38. Fourth
It is not necessary to provide the protective layer 50 of
The structure shown is obtained.

As previously explained, the various doping concentration and temperature level parameters associated with the processing of the device are closely related to the type of device ultimately sought to be achieved, thus constituting a preferred embodiment of the present invention. It is difficult to identify one type of embodiment or range of devices to do. However, when manufacturing such a device, a satisfactory insulated gate semiconductor device can be manufactured by using the following parameters. Equipment parameters First oxide layer 16 1,000Å Gate electrode 18 1 micron Second insulator 20 4,000Å Nitride layer 22 1,000Å First region 10 ¹⁷ atoms / cc Dopant second region 10 ¹⁵ atoms / cc dopant third region 10 ¹⁷ atoms / cc dopant second protective layer 4,000 Å third protective layer 1,000 Å FIG. 3 shows another preferred embodiment of the present invention, the first protective layer 14 A first window 25 where there was a first portion of the protective layer 14 to expose the first portion 27 of the surface of the semiconductor substrate 10 and the second portion 30 of the protective layer 14 and below it. It is shown to include another method of circumferentially confining the unexposed portion 31 of the surface of the substrate 10. First, a lightly doped base attachment region 40 is set, then a heavily doped deep base region 38 is set, and finally a heavily doped source region 35 is set.

In another preferred method of manufacturing an insulated gate semiconductor device according to this invention, a semiconductor substrate 10 having a resistivity of about 5 ohm.cm is provided. First protective layer, such as a nitride layer
14 is set on the substrate 10 and a first window 25 is opened in the first portion of the first protective layer 14 to expose the first portion 27 of the surface of the substrate 10 and The second portion 30 of the layer 14 and the unexposed second central portion 31 of the surface of the substrate 10 are circumferentially limited. The first window 25 also defines a third portion 32 of the first protective layer 14, which is outside the first window 25. A lightly doped material with one conductivity type, such as boron, having a fast diffusion is used to perform a first doping through the first window 25 to set the base attachment region 40 with one conductivity type. To do. A base attachment region 40 preferably extends underneath the first protective layer 14 to set the channel region of the device.
After this, a second protective layer 36, such as a differentially etchable native oxide layer, is set in the first window 25. This can be grown, for example, when the base region 40 is driven inward.

Thereafter, as shown in FIG. 3b, the photoresist mask layer 33 previously described is set on the third portion 32 of the first protective layer 14 and a portion of the second protective layer 36 to form Part 32 of 3
The second portion 30 of the first protective layer 14 can be removed without removing the above. Then, a second window 37 is formed in the entire second portion 30 of the first protective layer 14 using a differential etching method to expose the substrate 10 in a circumferential direction limited to the circumferential direction. The second central portion 31, which was not present, is exposed.
A second doping is performed through the second window 37 to form a base region by a conventional implantation or diffusion method using a high-concentration material of one conductivity type such as boron.
Set to 38. The photoresist layer can be removed if not removed by then.

After that, as shown in FIG.
The protective layer 45 of is arranged. This is advantageously a nitride layer that can be differentially etched.

Then, referring to FIG. 3d, a second protective layer may be formed using a suitable etch, such as a buffered hydrofluoric acid etch.
By removing 36, in the area of the first window 25 a third window
Open 48 to re-expose a portion of the first portion 27 of the surface of the substrate 10. The third window 48 limits the third protective layer 45 circumferentially. Thereafter, as shown in FIG. 3d, a high concentration dopant of opposite conductivity type such as phosphorus is introduced through the third window 48 to set the source region 35 as a heavily doped opposite conductivity type region. . This source region is shown in the drawings as an N + region located within the lightly doped P-type base attachment region 40 and the heavily doped P-type base region 38 with self-alignment accuracy. After that, the third protective layer 45 is removed using an appropriate etchant, leaving the structure shown in FIG. 3e.

It has been found that a satisfactory insulated gate semiconductor device manufactured according to the self-aligned manufacturing method of the present invention can be achieved by using the process parameters outlined below. Installation parameters First oxide layer 16 1,000Å Gate electrode 18 1 micron Insulator 20 4,000Å Nitride layer 22 1,000Å First region 10 ¹⁵ atoms / cc Dopant second region 10 ¹⁷ atoms / cc Dopant of the third region 10 ¹⁷ atoms / cc of dopant Second protective layer 4,000Å Third protective layer 1,000Å Still another preferred embodiment of the method of manufacturing a self-aligned semiconductor device according to the present invention is the successive steps. It is shown in Figures 4a to 4c. First, as shown in FIG. 4a, the semiconductor substrate 10 is prepared. The substrate is 20 mils thick, has a resistivity of about 5 ohms / cm, and can consist of a silicon wafer doped with carriers of opposite conductivity type to a concentration of approximately 10 ¹⁵ carriers / cc, The carrier is shown in the drawings as a carrier having an N-type conductivity. A first protective layer 14, such as a nitride layer, is provided on the substrate 10. In the insulated gate semiconductor device of the preferred embodiment of the present invention, the first protective layer 14 may be, for example, a natural oxide.
Of the insulating layer 16, a gate electrode 18 such as polysilicon disposed on the first insulating layer 16, and a second insulating layer 20 on the gate electrode 18. The second insulating layer may be a native oxide of polysilicon gate material. A passivation layer, such as nitride layer 22, is disposed over the second insulating layer 20.

A first window 15 is opened in a first portion of the first protective layer 14 and this portion is removed to expose a first surface portion 27 of the substrate 10 and a second portion of the first protective layer 14 is exposed. The central portion 30 and the underlying unexposed surface portion 31 of the substrate 10 are circumferentially limited. As shown, the unexposed surface portion 31 of the substrate 10 is covered by the second portion 30 of the first protective layer 14.

Once the first window 25 has been opened, the first portion of the substrate 10 is exposed and the substrate 10 can be first doped through the first window 25 to form the base attachment region 40. .
In the preferred form of manufacturing the MOSFET device, a lightly-concentrated material having one of the faster-diffusing conductivity types, such as boron, was used in combination with a conventional implantation or diffusion scheme to show as a region having a P-type conductivity type. , A first region 40 having one conductivity type that is lightly doped can be set. A base attachment region 40 preferably extends underneath the first protective layer 14 and sets the channel region of the device. Then the same first window 15
A second doping is carried out on the first surface portion 27 of the substrate 10 via a slow-diffusing opposite conductivity type dopant such as arsenic through the opposite conductivity type shown in the drawing as an N-type region. Set up a heavily doped source region 35 with a mold.

Next, referring to FIG. 4b, the first window 25 is formed above the first region 35 on the exposed surface of the first portion 27 of the semiconductor substrate 10.
The second protective layer 36 is set in the inside. In the preferred embodiment, the second protective layer 16 is differentially etchable and can be composed of natural and oxides such as silicon dioxide in the case of a silicon substrate, for example.

After this, referring to FIG. 4c, by using a loose fitting mask, the third portion 32 of the first protective layer 14 is
And a photoresist layer 33 is set on a part of the second protective layer 36. Then, by using a differential etch, for example, reacting with the material of the first protective layer 14 but not the second
The second window 37 is opened in the entire second portion 30 of the first protective layer 14 by using a selective etch that does not react with the material of the protective layer 36 of The second portion 31 that was not exposed is exposed. By using a reactive ion etch, the second portion 30 of the first insulating layer 14 can be removed and the second window 37 can be opened.

After this, the second surface portion 31 of the substrate 10 is exposed through the second window 37.
A third doping is performed on P + in the substrate 10
A base region 38 having one conductivity type shown in the drawing as a shaped region is set. The second doping is preferably done by using a high concentration material with one of the faster-diffusing conductivity types, such as boron, in combination with conventional implantation or diffusion schemes. Thereafter, conventional metallization and patterning steps can be performed to complete the device.

Although the preferred embodiment of the present invention has been described for the case of a self-aligned method of manufacturing an insulated gate semiconductor device such as an insulated gate transistor, any of a large number of semiconductor devices can be set using the self-aligned method of the present invention. Please understand that you can do it. Furthermore, the self-aligned manufacturing method of the present invention creates precisely aligned regions, which requires less tolerances between regions, thus maximizing the utilization of available chip substrate area. It will be appreciated that by improving the cell density and reducing the cell size and cell repeat distance, a significant contribution can be made to the improvement of semiconductor devices.

While the preferred embodiment of the present invention has been shown and described in the drawings,
Obviously, the invention is not limited to this embodiment. Those skilled in the art will appreciate various modifications within the scope of this invention. Therefore, it should be appreciated that the invention is limited by the claims.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Chan, Mike Fu Singh, United States, 27511, North Carolina, Karii, Queensferry, 1006 (72) Inventor Pfeiffer, George Charles United States, 13212 No. 6767, Buckley Road, Syracuse, New York (56) References JP 57-139965 (JP, A) JP 59-3973 (JP, A) JP 62-73778 (JP, A) )

Claims (53)

[Claims] 1. A semiconductor substrate having a main surface is prepared, a first protective layer is provided on the surface of the substrate, a first portion of the protective layer has an inner periphery and an outer periphery, and a second portion of the protective layer is provided. A first window surrounding a portion of the first window and introducing a first dopant into the substrate from the first window to create a first doped region self-aligned to the first window, Forming a second protective layer on the substrate of the first window;
Removing the second portion of the protective layer to open a second window,
Introducing a second dopant from the second window into the substrate to create a second doped region self-aligned to the inner perimeter of the first window, exposing the first doped region. A third window from the third window to the first region to create a third doped region self-aligned to the outer perimeter of the first window for forming a third window in the second protective layer. Introducing a third dopant, the second and third regions are of one conductivity type, and the substrate and the first region
Is a reverse conductivity type, and the first and second protective layers are substantially impermeable to the transmission of the diffusion dopant. 2. The method of claim 1, wherein the third region extends underneath the first protective layer. 3. The method of claim 1 including the step of providing a metallization layer in ohmic contact with portions of said first and second regions. 4. The method of claim 1, wherein the first protective layer comprises an insulated gate electrode. 5. The first protective layer is disposed on the substrate, a first insulating layer, a gate electrode disposed on the first insulating layer, and a gate electrode disposed on the gate electrode. The method of claim 1 comprising a second insulating layer. 6. The method according to claim 5, wherein the first insulating layer is made of a natural oxide, the second insulating layer is made of a natural nitride, and the gate electrode is made of polysilicon. Method. 7. The step of opening the second window comprises providing a photoresistor layer outside the first window, on a portion of the first protective layer, and on the second protective layer. The method of claim 1 including removing a second portion of the protective layer using a reactive ion etch. 8. The method of claim 1, wherein the step of opening the first window comprises removing a first portion of the protective layer using a reactive ion etch. 9. The method of claim 1, wherein the step of opening the first window comprises removing the first portion of the protective layer using a buffered hydrofluoric acid etch. 10. The method of claim 1 wherein the step of opening the second window comprises removing a second unexposed portion of the first protective layer using a reactive ion etch. Method. 11. The first window sets a mask by photolithography under the surface of the first protective layer to form the first window.
2. The method of claim 1, wherein the masking is performed by masking a portion of the first protective layer or a portion outside the first window, and then using an etchant to remove the unmasked areas of the first protective layer. . 12. A method of manufacturing a self-aligned semiconductor device, wherein (a) a semiconductor substrate is prepared, (b) a first protective layer is provided on the substrate, and (c) the first protective layer. The first of the layers
To expose the first portion of the substrate and to expose the second portion of the first protective layer as well as the unexposed second portion of the underlying substrate. Limiting to the circumferential direction, (d) providing a second protective layer on the first window,
(E) A second window is opened in the second portion of the first protective layer to expose the second portion of the substrate, and (f) A first window is formed in the substrate through the second window. Introduce the dopant of the first
And (g) forming a third protective layer on the second window, and (h) opening a third window on the second protective layer.
(I) introducing a second dopant through the third window to set a second region, and (j) third through the third window.
The step of introducing the dopant of step 1 to set the third region. 13. Further, a fourth protective layer is set on the third window, a fourth window is opened on the third protective layer, and a part of the first and third doped regions is formed. 13. The method of claim 12, including the step of applying a metallization layer that is exposed and in contact with the first and third regions to short the first and third regions. 14. The method of claim 13, wherein the first window is co-located with the third window and the fourth window is co-located with the second window. 15. The step of providing a first protective layer on the substrate comprises growing a first insulating layer on an exposed surface of the substrate and depositing a polysilicon layer on the first insulating layer. And growing a nitride layer on the polysilicon layer.
12 Method described. 16. The step of opening the first window comprises the step of opening the first window.
13. The method of claim 12, which is formed by photolithographically masking the protective layer of 1. and then etching the unmasked portion of the first protective layer. 17. The first protective layer is composed of a first insulating layer, a gate layer and a second insulating layer, and the step of opening the first window comprises nitriding using reactive ion etching. 17. The method of claim 16 including drilling a first window in the object layer, the gate layer and the first insulating layer. 18. The method of claim 17, wherein the first insulating layer comprises a native oxide. 19. The method of claim 17, wherein the second insulating layer comprises silicon nitride. 20. The first protective layer comprises a first insulating layer, a gate electrode layer and a second insulating layer, and the step of opening the second window etches the second insulating layer. And opening a window therein, performing a second etch to open the window in the gate electrode layer, and performing a third etch in the first insulating layer. 12 Method described. 21. The method of claim 12, wherein the step of introducing the first dopant is performed by diffusion. 22. The method of claim 12, wherein the step of introducing the first dopant is performed by implantation. 23. The method of claim 12, wherein the substrate and the third region are of opposite conductivity type and the first and second regions are of one conductivity type. 24. The second window is on the portion of the first protective layer outside the first mask, and the second window.
13. The method of claim 12, wherein the method is opened by providing a photoresist layer over the protective layer of, and performing a reactive ion etch to remove the second portion of the first protective layer. 25. The method of claim 12, wherein the first and second protective layers are differentially etchable. 26. The method of claim 12, wherein the first region is deeply diffused, the second region is less deeply diffused, and the third region is shallowly diffused. 27. In a self-aligning method for manufacturing a semiconductor device, (a) preparing a semiconductor substrate of opposite conductivity type,
(B) providing a first protective layer on the substrate, and (c) the first protective layer.
A first window in the protective layer to expose a first portion of the substrate, the first window including a second portion of the first protective layer and a second portion of the underlying substrate. Are limited to the circumferential direction, (d) a dopant of one conductivity type is introduced through the first window to set a base attachment region, and (e) a second region is formed in the first window. A protective layer is provided, (f) a second window is opened in the second portion of the first protective layer to expose the second portion of the substrate, and (g) one of the two is provided through the second window. Introduce a conductivity type dopant to set the central base region,
(H) providing a third protective layer on the second window, (i) opening a third window on the second protective layer, and (j) introducing a dopant through the third window. A self-aligning method including a step of setting a source region. 28. The step of providing the first protective layer comprises:
An insulating layer, a polysilicon layer is provided on the first insulating layer, and a second insulating layer is provided on the polysilicon layer.
28. The self-aligning method according to claim 27, further comprising the step of providing a nitride layer on the second insulating layer. 29. The first window is set by masking the first protective layer by photolithography and etching the first protective layer to remove unmasked portions. The self-aligning method according to Item 27. 30. A portion of the first protective layer outside the first window of the second window is masked by photolithography, and a portion of the second protective layer is also formed by photolithography. 28. The self-aligning method according to claim 27, wherein the self-alignment method is performed by masking and etching an unmasked portion of the first protective layer. 31. The self-aligning method according to claim 27, wherein the step of introducing the first dopant is performed by a diffusion method. 32. The self-aligning method according to claim 27, wherein the step of introducing the first dopant is performed by implantation. 33. The self-aligning method according to claim 27, wherein the second protective layer is composed of a natural oxide. 34. The self-aligning method according to claim 27, wherein the second protective layer is composed of silicon dioxide. 35. The third window is set by masking the first and second protective layers by photolithography and etching the unmasked portions of the third protective layer. Self-alignment method described. 36. The self-aligning method according to claim 27, further comprising the step of providing a fourth protective layer on the third window, removing the photolithographic mask, and opening a window on the second protective layer. 37. The self-aligned method of claim 27, wherein the third protective layer is resistant to oxide etch. 38. The self-aligned method of claim 27, wherein the substrate and the third region are of opposite conductivity type, and the base attachment region and the central base region are of opposite conductivity type. 39. The method of claim 27, wherein the central base region is doped to a greater depth than the base attachment region. 40. The method of claim 27, wherein the source region is shallow and heavily doped. 41. A semiconductor substrate having a main surface is prepared, a first protective layer is provided on the substrate surface, and the first protective layer is formed.
A first window having an inner circumference and an outer circumference in the portion of and surrounding the second portion of the protective layer to form a first doped region self-aligned with the first window. Closing the first window by introducing a first dopant into the substrate from a first window and providing a second protective layer in the first window, and the second portion of the first protective layer. Removing a second window to introduce a third dopant into the substrate from the second window to create a third doped region that is self-aligned to the inner perimeter of the first window. The first and third regions are of one conductivity type, the substrate is of opposite conductivity type, and the step of opening the second window extends beyond the outer periphery of the second protective layer. A photoresist layer on a part of the first protective layer, and the photoresist layer Method of manufacturing an insulated gate semiconductor device in which self-alignment comprises the step of etching the portions of said first protective layer not protected. 42. The method of claim 41, wherein the protective layer is substantially impermeable to dopant penetration by implantation. 43. The method of claim 41, wherein the first region extends underneath the first protective layer. 44. The method of claim 41, including the step of providing a metallization layer in ohmic contact with portions of the first and second substrate regions. 45. The method of claim 41, wherein the first protective layer comprises an insulated gate electrode. 46. The first protective layer is disposed on the substrate, the first insulating layer is disposed on the substrate, the gate electrode is disposed on the first insulating layer, and the gate electrode is disposed on the gate electrode. The second done
42. The method of claim 41, wherein the method comprises an insulating layer of. 47. The method according to claim 46, wherein the first insulating layer is made of a natural oxide, the second insulating layer is made of a natural nitride, and the gate electrode is made of polysilicon. Method. 48. The method of claim 41, wherein the first window is opened using an oxide specific etch. 49. The method of claim 41, wherein the step of forming the first window is performed using a KOH etch. 50. The method of claim 41, wherein the step of forming the second window is performed using a reactive ion etch. 51. The step of opening a first window comprises setting a mask on the surface of the first protective layer by photolithography and then etching away the unmasked regions of the first protective layer. 42. The method of claim 41, including. 52. In a method of manufacturing a self-aligned semiconductor device, (a) a semiconductor substrate is prepared, (b) a first protective layer is provided on the substrate, and (c) the first protective layer. The first of the layers
To expose a first portion of the substrate at a first portion of the first protective layer, the first window exposing a second portion of the first protective layer and an unexposed first portion of the underlying substrate. 2 is limited to the circumferential direction, (d) the first region is formed in a predetermined matching relationship with the first portion of the substrate, and (e) the second surface portion of the substrate. Forming a second substrate region in a predetermined alignment relationship with the first substrate region, wherein the first region extends under the first protective layer. 53. In a method of manufacturing a self-aligned semiconductor device, (a) a semiconductor substrate is prepared, (b) a first protective layer is provided on the substrate, and (c) the first protective layer. The first of the layers
Expose a first portion of the substrate by opening a first window in
The first window circumferentially defines a second portion of the first protective layer and an unexposed second portion of the underlying substrate, (d) the first portion of the substrate. First and second doped regions are formed in a surface portion of the substrate with a predetermined matching relationship, and (e) a predetermined portion with the first and second doped regions is formed in the second portion of the substrate. Forming the doped region of FIG. 3 in a matching relationship of ## EQU1 ## wherein the first window causes the substrate to be in three separate regions, namely a first region below the first window, A second region below a second portion of the first protective layer and a third region below a portion of the first protective layer outside the first window. how to.