JPH0783263B2 - Digital signal generator - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal generator, and more particularly to improvement of a frequency synthesizer using a phase locked loop (PLL).

(Prior Art) One type of frequency synthesizer uses a phase locked loop.

FIG. 3 is a block diagram showing an example of such a conventional device. In FIG. 3, reference numeral 1 denotes a phase locked loop which outputs a signal of frequency f ₁ , a reference oscillator 2 which outputs a reference signal of frequency f ₀ , a phase of the reference signal output from the reference oscillator 2 and a frequency dividing circuit. Phase comparator 5 for comparing the phases of the output signals of the voltage controlled oscillator (VCO) 4 having the frequency f ₁ applied via the voltage controlled oscillator 4 with the low frequency component of the output signal of the phase comparator 5 as the frequency control signal. And a low pass filter (LPF) 6 added to the. Reference numeral 7 is a fixed oscillator that outputs a signal of frequency f ₂ . 8 is a mixer for mixing the output frequency f ₂ of the output frequency f ₁ and the fixed oscillator 7 of the phase-locked loop 1. 9 is the low frequency component of the output signal of the mixer 8.
It is a low-pass filter for outputting f ₂ −f ₁ .

In such a configuration, for example, 10 kHz in 1 Hz steps
To obtain an output frequency of 100MHz, set f ₀ to 10KHz
Is set, the oscillation frequency region of the voltage controlled oscillator 4 is set so that f ₁ is 500 MHz to 599.99 MHz, the division ratio of the frequency dividing circuit 3 is set, and f ₂ is set to 600 MHz. Then, the output frequency can be adjusted by changing the frequency division ratio of the frequency dividing circuit 3.

(Problems to be Solved by the Invention) However, according to such a conventional configuration, since a frequency that is several times the required output frequency band is handled, a shield is provided in order to reduce interference and spurious between signals. Should be strict.

Further, in order to set the output frequency with 1 Hz resolution, it is necessary to devise so that a fractional value can be set as the frequency division ratio of the frequency divider circuit 3, which complicates the circuit configuration.

Furthermore, the output signal of the reference oscillator 2 of the voltage controlled oscillator 1 and the output signal of the fixed oscillator 7 must be phase-synchronized.

The present invention focuses on such a point, and an object thereof is to provide an apparatus capable of obtaining a high frequency signal with high frequency accuracy and high frequency setting resolution with a relatively simple configuration. .

(Means for Solving Problems) A digital signal generator of the present invention which achieves such an object reads sine wave waveform data from a waveform memory in accordance with address data arbitrarily set according to a desired frequency. A waveform synthesizer that converts and outputs the analog signal waveform, and the output signal of this waveform synthesizer is added as a reference signal to the phase comparator, and the output signal of the voltage controlled oscillator is fed back to the phase comparator through the frequency divider. A phase-locked loop, a frequency divider that sequentially divides the output signal of this phase-locked loop by 1/2, and the input and output of the frequency dividers that configure these frequency dividers. Consists of a multiplexer that selectively outputs signals according to the desired frequency, and a control unit that controls the address addition to the waveform synthesizer and the selection operation of the multiplexer according to the desired frequency. It is characterized by being done.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, reference numeral 10 is a waveform synthesizer. The waveform synthesizer 10 includes a clock generator 11 for generating a clock signal having a constant cycle, an adder 12 for externally setting unit address data related to a unit phase amount according to a desired frequency, and a clock for the clock generator 11. Latch 13 that latches the address data output from the adder 12 in synchronization with the signal and adds the latched address data to the other input terminal of the adder 12 and also to the memory (ROM) 14 in the next stage, this latch 13 The memory 14 that outputs predetermined waveform data according to the address data that is output from the D / A converter 15 that converts the waveform data output from the memory 14 into an analog signal in synchronization with the clock signal of the clock generator 11, The low pass filter 16 outputs the low frequency component of the analog signal converted and output from the D / A converter 15. From the waveform synthesizing unit 10 configured in this way, an analog signal waveform of frequency f having a frequency resolution of 1 / r according to the unit address data preset according to the desired frequency is converted and output. . Here, the memory 14 stores sine wave data as waveform data in order to guarantee a single frequency spectrum of the output waveform. Therefore, the output waveform of the waveform synthesizer 10 becomes a sine wave. Reference numeral 17 is a phase locked loop using the output signal of the waveform synthesizer 10 as a reference signal. The phase locked loop 17 includes a phase comparator 21 and a phase comparator 21 for comparing the phase of the output signal of the waveform synthesizer 10 and the phase of the output signal of the voltage controlled oscillator (VCO) 19 applied via the frequency divider 20. And a low-pass filter (LPF) 18 that applies the low-frequency component of the output signal of 1 to the voltage-controlled oscillator 19 as a frequency control signal. When the frequency division ratio of the frequency divider 20 is N, the phase-locked loop 17 thus configured outputs a signal of frequency N · f with a frequency resolution of N / r. Reference numeral 22 is a frequency dividing unit composed of a plurality of frequency dividers d _{1 to} d _{n for} sequentially dividing the output signal of the phase locked loop 17 by 1/2. Reference numeral 23 is a multiplexer for selectively outputting the output signal of the frequency divider 22 according to a control signal applied from the outside according to a desired frequency. A control unit 24 outputs a control signal for controlling the waveform synthesizing unit 10 and the multiplexer 23.

The operation of the apparatus thus configured will be described.

For example, assume that a signal of 1 Hz to 134 MHz is obtained with a frequency resolution of 1 Hz.

In this case, the memory 14 stores the sine wave amplitude data for one cycle as the waveform data. In the waveform synthesizer 10,
The adder 12 and the latch 13 add unit address data given from the outside for each clock output from the clock generator 11. The result of this addition is given to the memory 14 as phase information. Here, by changing the unit address data given to the adder 12 from the outside, the reading interval of the sine wave amplitude data stored in the memory 14 can be changed and the output frequency can be changed. The setting resolution (= 1 / r) of this output frequency is determined by the number of bits of the adder 12 and the latch 13 and the clock frequency. For example, set the output frequency of the clock generator 11 to 2 ²³ H
z, the number of bits of the adder 12 and the latch 13 is 29, and the unit address data (binary data) externally given to the adder 12 is ΔΦ, the output frequency f of the waveform synthesizing unit 10 is
It is expressed by the following equation.

f = Thus ΔΦ × 2 ^{23/2 29,} frequency 2 ²⁶ H as a unit address data .DELTA..PHI
by providing data corresponding to z~2 ²⁷ Hz, as the output frequency f of the waveform synthesizer 10 can be obtained in 2 ²⁰ Hz to 2 ²¹ Hz setting resolution 1 / r = 1 / 64Hz. This waveform synthesizer 1
The output frequency f of 0 corresponds to the phase comparator 21 of the phase locked loop 17.
As a reference signal. On the other hand, the phase-locked loop 17
The frequency division ratio N of the frequency divider 20 is set to N = 64. As a result,
The output frequency N of the voltage controlled oscillator 19 of the phase locked loop 17
f is from 2 ²⁶ Hz (67.108864MHz) in 1Hz step resolution
It will change between 2 ²⁷ Hz (134.217728 MHz). The output frequency N · f of the voltage controlled oscillator 19 of the phase-locked loop 17 is added to the frequency divider 22 composed of a plurality of frequency dividers d _{1 to} d _n and sequentially divided by 1/2. Thus, the frequency of the input signal s ₁ of the frequency divider d ₁ becomes 2 ²⁷ Hz since by dividing the frequency of the input signal s ₂ of divider d ₂ is 2 ²⁶ Hz, and so on to, the divider d _n The input signal s _{n has} a frequency of 2 ^{27-n + 1} Hz, and the frequency divider d
the frequency of the output signal s _{n + 1} of the _n becomes 2 ^27-n Hz. The input / output signals s _{1 to} s _{n + 1} of the frequency divider 22 are applied to the multiplexer 23. Then, the multiplexer 23 is provided with a frequency division unit according to a control signal applied from the control unit 24 according to a desired frequency.
Selectively outputs any of 22 input / output signals s _{1 to} s _{n + 1}
Output to 25.

Therefore, by configuring the frequency divider 22 in the 27 1/2 frequency divider, the frequency of the signal from the 2 ⁰ Hz (1Hz) to 2 ²⁷ Hz (134.217728MHz) can be set at 1Hz resolution . The waveform of the signal output from the multiplexer 23 to the output terminal 25 is a square wave pulse train suitable for digital processing.

With this configuration, the frequency to be handled becomes equal to the desired frequency, and when compared with the same output frequency, the shield condition can be relaxed and cost can be reduced as compared with the conventional case.

Further, a complicated frequency dividing circuit as in the prior art is unnecessary, and the circuit configuration can be simplified.

Further, most of the circuits can be integrated into a circuit, which can be significantly downsized, and mass production effects can be expected.

In the above embodiment, the frequency divider 20 of the phase-locked loop 17 and the frequency dividers d _{1 to} d _n forming the frequency divider 22 are individually provided. The frequency divider 20 and the frequency dividers d _{1 to} d _n forming the frequency divider 22 may be shared as shown in FIG.

In the above embodiment, although the frequency of the signal from the 2 ⁰ Hz up to 2 ²⁷ Hz has been described an example of a signal generating apparatus which can output at 1Hz resolution frequency range and setting resolution are those that can be appropriately changed, Example It is not limited to.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a digital signal generator that can obtain a high-frequency signal with high frequency accuracy and a high frequency setting resolution with a relatively simple configuration, and is practically used. The above effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an essential part of another embodiment of the present invention, and FIG. 3 is a block diagram showing an example of a conventional device. 10 ... Waveform synthesis block, 17 ... Phase locked loop, 22 ... Frequency division block, 23 ... Multiplexer, 24 ... Control block.

Claims (1)

[Claims] 1. A waveform synthesizer for reading sine wave waveform data from a waveform memory in accordance with address data arbitrarily set according to a desired frequency, converting the waveform data into an analog signal waveform and outputting the waveform, and an output signal of the waveform synthesizer. A phase-locked loop that is applied as a reference signal to the phase-comparison section and that the output signal of the voltage-controlled oscillator is fed back to the phase-comparison section via a frequency divider, and the output signal of this phase-locked loop is divided by 1/2 in sequence. Frequency division unit composed of a plurality of frequency dividers, a multiplexer that selectively outputs the input / output signals of the plurality of frequency dividers that compose these frequency division units according to the desired frequency, and waveform synthesis according to the desired frequency. A digital signal generator comprising: a control unit for controlling an address applied to the unit and a selecting operation of a multiplexer.