JPH0832350A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce the spuriousness of a PLL frequency synthesizer using a direct digital synthesizer at an optional frequency. CONSTITUTION:Frequency setting signals 25 prepared beforehand for reducing the generation of the spuriousness are inputted to the direct digital synthesizer 23 and the frequency division ratio of an universal frequency divider 43 is set so as to output the signals of the frequency for which the optional frequency to be outputted from the direct digital synthesizer 23 is divided by the ratio. The output of the universal frequency divider 43 is inputted as the reference clock signal 21 of the direct digital synthesizer. Since the ratio with less spuriousness is set to the direct digital synthesizer 23 and the frequency of the reference clock signal 21 is changed corresponding to the frequency to be outputted from a PLL circuit 11, the signals with less spuriousness are outputted at any frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer capable of outputting a signal of any frequency, and more particularly to a frequency synthesizer using a direct digital synthesizer (DDS).

[0002]

2. Description of the Related Art PLL (Phase Locked L)
There are various types of frequency synthesizers such as a prescaler system and a mixing system as a frequency synthesizer using a loop circuit, but in recent years, one using a direct digital synthesizer has been proposed. A PLL frequency synthesizer using a direct digital synthesizer is disclosed in USP-4965533. Direct digital synthesizers are attracting attention because they can set the output frequency in very fine steps. Direct digital
The synthesizer is also called a Numerical Controlled Oscillator (NCO).

FIG. 2 shows an outline of a circuit configuration of a PLL frequency synthesizer using a direct digital synthesizer. This frequency synthesizer includes a PLL circuit unit 11 that locks a phase,
The PLL circuit unit 11 includes a phase comparison reference signal generation unit 13 that outputs a phase comparison reference signal 12 for performing phase comparison. The PLL circuit unit 11 includes a phase comparator 14
, Loop filter 15, voltage controlled oscillator (VCO)
16 and a frequency divider 17. The voltage controlled oscillator 16 oscillates a signal having a frequency according to the voltage of the input control signal. Voltage controlled oscillator 16
The output of is divided by a frequency divider 17 at a predetermined frequency division ratio and input to the phase comparator 14. The phase comparator 14 detects the phase difference between the phase comparison reference signal 12 and the signal output from the frequency divider 17. The loop filter 15 extracts a low frequency component from the output signal of the phase comparator 14. By inputting the output of the phase comparator 14 into the voltage controlled oscillator 16 via the loop filter 15, the voltage controlled oscillator 16 outputs a signal having a frequency obtained by multiplying the frequency of the phase comparison reference signal 12 by a frequency division ratio. Has become.

The phase comparison reference signal generator 13 comprises a reference signal generator 22 for generating a reference clock signal 21, a direct digital synthesizer 23, and a low pass filter 24 for extracting low frequency signal components. ing. A reference clock signal 21 and a frequency setting signal 25 for setting the frequency of the signal output by the direct digital synthesizer 23 are input to the direct digital synthesizer 23. The frequency of the signal output by the direct digital synthesizer 23 is determined by both the frequency of the reference clock signal 21 and the frequency setting signal 25. Normally, the frequency of the reference clock signal 21 is fixed, and the frequency of the phase comparison reference signal 12 input to the PLL circuit unit 11 is changed by changing the value of the frequency setting signal 25. . By changing the frequency of the signal output from the direct digital synthesizer 23 by the frequency setting signal 25, the frequency of the output signal of the PLL frequency synthesizer is changed.

FIG. 3 shows an outline of a typical circuit configuration of a direct digital synthesizer.
The direct digital synthesizer 23 includes a phase accumulator 31, a sine look-up table 32, and a digital / analog converter 33. Of these, the phase accumulator 31
Is one cycle of the reference clock signal 21 divided by 2 to the power of 32.
The phase at each time divided into is retained. The frequency setting signal 25 input to the phase accumulator 31 sets the ratio of the frequency of the output signal to the reference clock signal 21. Here, the frequency setting signal 25 is a digital signal representing the numerator value when the denominator is 2 32, and the ratio of the frequency of the output signal to the frequency of the reference clock signal 21 is represented by the ratio represented by this fraction. Is set. For example, if the frequency of the output signal is the reference clock signal 2
When the frequency is set to 1/10 of the frequency of 1, the numerical data representing the value of 1/10 of 2 32 is input as the frequency setting signal 25. The phase accumulator 31 is adapted to perform a phase conversion operation for each phase divided into 1/32 of 2 by a set ratio.

The signature look-up table 32 is
The amplitude value corresponding to the phase is stored for each phase, and is a part that converts the phase information into amplitude information. The sine look-up table 32 outputs a digital signal representing the amplitude of the sine wave as a numerical value when the phase advance of the input phase information is constant. A ROM (Read Only Memory) is normally used for the signature lookup table 32. The phase information input from the phase accumulator 31 is a sine
It is converted into amplitude information by the look-up table 32 and input to the digital-analog converter 33. Here, the digital signal representing the amplitude information is converted into an analog electric signal. In this way, the direct digital synthesizer 23 converts the frequency of the reference clock signal 21 into an analog signal having a frequency of the ratio set by the frequency setting signal 25 and outputs it.

[0007]

By the way, when the frequency of the output signal of the direct digital synthesizer is changed variously by the frequency setting signal, spurious noise may occur in the vicinity of the center frequency. Spurious often occurs in a frequency region separated by about 0.01% of the center frequency. Further, spurious noise does not occur only when the direct digital synthesizer oscillates a specific frequency, and also occurs in many other channels. For example, when a frequency of 1000 channels is oscillated in a frequency step of 10 kilohertz, it has been confirmed that spurious is generated in several hundred channels. If the number of channels is small, it is also possible to remove spurs individually with a filter. However, when the number of channels that can be output exceeds several thousand, the number of channels that must be provided with a filter becomes huge, which complicates the device and makes it difficult to reduce the size. There was a problem. Further, since spurious is generated in the vicinity of the center frequency, a filter with high frequency accuracy is required, which causes a cost increase. As a result, it has been almost impossible to put a high-quality PLL frequency synthesizer with a large number of channels using a direct digital synthesizer into practical use.

Therefore, a first object of the present invention is to provide a frequency synthesizer which can easily remove spurious generated by a direct digital synthesizer.

A second object of the present invention is to provide a frequency synthesizer which does not generate spurious in a large number of channels.

[0010]

According to a first aspect of the present invention, there is provided an oscillator having a variable oscillation frequency, and a direct signal outputting a signal obtained by converting a frequency of a signal output from the oscillator into a frequency having a set ratio. The digital synthesizer and the ratio setting means for setting a preset ratio for this direct digital synthesizer that reduces the spurious contained in the signal output by this direct digital synthesizer, and the oscillation frequency of the oscillator by the direct digital synthesizer. The frequency synthesizer is provided with oscillation frequency setting means for setting a frequency obtained as a result of dividing the frequency of the signal to be output from the synthesizer by the ratio set by the ratio setting means.

That is, according to the first aspect of the invention, the oscillation frequency of the oscillator is changed in accordance with the frequency of the signal to be output, in the state where a small ratio of spurious prepared in advance is set. This allows the direct digital synthesizer to output a signal having an arbitrary frequency with less spurious.

According to a second aspect of the present invention, an oscillator having a variable oscillation frequency, a direct digital synthesizer for outputting a signal obtained by converting the frequency of the signal output by the oscillator into a frequency having a set ratio, The direct digital synthesizer outputs the oscillation frequency of the oscillator from a ratio setting means for setting a preset ratio in the direct digital synthesizer that reduces the spurious contained in the signal output from the direct digital synthesizer. Oscillation frequency setting means for setting a frequency obtained by dividing the frequency of the power signal by the ratio set by the ratio setting means, and a phase locked loop for inputting the output of the direct digital synthesizer as a signal for phase comparison. And are used as frequency synthesizers. It is made to.

That is, according to the second aspect of the invention, the oscillation frequency of the oscillator is changed in accordance with the frequency of the signal to be output in a state in which a small ratio of spurious prepared in advance is set. This allows the direct digital synthesizer to output a signal having an arbitrary frequency with less spurious. In addition, as a signal for phase comparison of the phase locked loop,
By using the output of the digital synthesizer,
A phase locked loop signal with few spurious signals with a locked phase is obtained from the output of the phase locked loop. If a frequency divider is provided in the phase-locked loop, a signal with a frequency obtained by multiplying the frequency output by the direct digital synthesizer by a frequency division ratio can be output from the phase-locked loop, and a high-frequency signal can be obtained. be able to.

Further, in the invention according to claim 3, the ratio set in the direct digital synthesizer is 1 / N of 2 (N is an integer of 1 or more). Ratio 2
It has been found as a result of various measurements that the spurious signal contained in the signal output from the direct digital synthesizer is reduced by setting it to the Nth power of N.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows an outline of a circuit configuration of a frequency synthesizer according to an embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted as appropriate. In the phase comparison reference signal generator 13 of FIG. 1, the frequency of the reference clock signal 21 input to the direct digital synthesizer 23 can be arbitrarily set. The clock signal generator 41 outputs the clock signal 42 having a fixed frequency. Here, a crystal oscillator is used to output a clock signal 42 of 10 MHz. Universal frequency divider 43
Is for dividing the 10 MHz clock signal 42 input from the clock signal generator 41 by a set arbitrary division ratio. The universal frequency divider 43 can output the reference clock signal 21 having an arbitrary frequency by setting the frequency division ratio.

The ratio setting unit 44 has a universal frequency divider 4 according to the frequency of the signal output from the PLL circuit unit 11.
3 is a part for setting the frequency of the reference clock signal 21 output by the signal No. 3. The ratio setting unit 44 uses the reference frequency calculation circuit 4
5 and ratio register 46. The reference frequency calculation circuit 45 is a part that calculates the frequency of the reference clock signal 21 to be output by the universal frequency divider 43 in accordance with the frequency output from the PLL circuit unit 11. The reference frequency calculation circuit 45 is supplied with a frequency designation signal 47 for designating the frequency of the signal output from the PLL circuit. The universal frequency divider 43 receives a frequency division ratio designating signal 48 for designating a frequency division ratio from the reference frequency calculation circuit 45. The ratio register 46 is a part in which the value of the frequency setting signal 25 input to the direct digital synthesizer 23 is stored in advance. Here, the ratio register 4
In “6”, “40000000” (hexadecimal notation) is stored. Since the frequency setting signal 25 represents the value of the numerator when the denominator is 2 32, the direct digital synthesizer 23 outputs the reference clock signal 21.
A signal having a frequency of a quarter of the frequency is output.

The frequency synthesizer of this embodiment is a PLL.
The output frequency of the circuit unit 11 is changed from 2.45 GHz to 2.
1000 in 10 kilohertz units up to 55 GHz
It can be changed by 0 steps.
The frequency division ratio of the PLL circuit unit 11 is “1000”. Therefore, the output of the direct digital synthesizer 23 may be changed by 10000 steps in units of 10 hertz. Since the direct digital synthesizer 23 outputs a signal having a frequency that is a quarter of the frequency of the reference clock signal 21, the reference clock signal 2
1 is changed in units of 40 hertz. The reference frequency calculation circuit 45 outputs the reference clock signal to be output by the universal frequency divider 43 based on the frequency of the signal output to the PLL circuit unit 11, the frequency division ratio in the PLL circuit unit 11, and the value of the ratio register 46. 21 frequencies are calculated. That is, the output frequency is 1/4000
The calculated value is calculated.

The low pass filter 24 removes high frequency components from the output signal of the direct digital synthesizer 23. Since the amplitude of the output of the direct digital synthesizer 23 changes stepwise, it contains many high frequency components. The low pass filter 24 is designed to remove this.

Then, the value of the frequency setting signal 25 set in the direct digital synthesizer 23 is set to "4".
It will be described that spurious can be reduced by setting "0000000".

The value of the frequency setting signal 25 is 32 from 1 to 2.
It can be set by changing the interval between rides by one. When the value of the frequency setting signal 25 is changed by 1 and measured, the value of the direct digital
There are cases where a large amount of spurious occurs in the output of the synthesizer 23 and cases where a small amount of spurious occurs. When the value of the frequency setting signal 25 is set to 2 N,
It turned out that at least spurious emission was low.
Occurrence of spurious was small even with values other than 2 to the Nth power, but the frequency with spurious was very high. From the above measurement results, the direct digital synthesizer 2 can be used for the frequency of the reference clock signal 21.
It has been found that when the frequency output from 3 is 1 / N of 2, the generation of spurious is at least small.

For example, when a signal having a frequency of 2.5 GHz is output from the PLL circuit section 11, if the frequency division ratio of the frequency divider is "1000", the phase comparison reference signal 12 of 2.5 MHz is obtained. Just enter it. In this case, the frequency of the reference clock signal 21 is divided by 2 to the power of 2, that is, 4 by the direct digital synthesizer 23.
It is set so that the signal of the divided frequency is output.
Then, if the 10 MHz reference clock signal 21 is input from the universal frequency divider 43, the 2.5 MHz phase comparison reference signal 12 can be obtained. When the 2.499990 GHz signal, which is 10 kHz lower than the 2.5 GHz, is output from the PLL circuit section 11, the phase comparison reference signal 12 of 2.499990 MHz must be output from the direct digital synthesizer 23. At this time, the reference clock signal 2
1 to 10 MHz, the frequency setting signal 25
2.4999 even if the value of is set to "3FFFEF39"
A 90 MHz phase comparison reference signal 12 can be obtained. However, in this case, a lot of spurious is generated. This is because the frequency of the signal output from the direct digital synthesizer 23 is not the frequency of the frequency of the reference clock signal 21 divided by 2 N.

Therefore, the value of the frequency setting signal 25 is set to "40".
The frequency of the reference clock signal 21 was set to 9.999960 MHz. At this time, the spurious emission was small.
By changing the frequency of the reference clock signal 21 while keeping the frequency of the signal output from the digital synthesizer 23 at one fourth of the reference clock signal 21, it is possible to obtain a signal of an arbitrary frequency with less spurious. The cause of the decrease in spurious is not clear, but as a result of various measurements, it has been found that the occurrence of spurious is not limited to 1/4 and 2 to the Nth power.

Direct digital used for measurement
The phase accumulator 31 of the synthesizer 23 divides one cycle of the reference clock signal 21 into phases by the power of 2 32, and the frequency setting signal 25 can set a value from 1 to the power of 2 2. There is. The ratio of the frequency of the output signal to the frequency of the reference clock signal is 2 32
Since the power is set as the denominator, the ratio can be set to 1 / integer only when 1 / N is 2. If the frequency setting method for the direct digital synthesizer 23 is different and an arbitrary ratio can be set, it is not limited to 1 / N of 2 and spurious is small when the ratio is 1 / integer. it is conceivable that.

In the embodiment described above, a fixed value is used as the value of the frequency setting signal set in the direct digital synthesizer, but the ratio is 2 to the Nth power.
This value may be changed as long as the value becomes. For example, when the frequency range of the reference signal cannot be changed to cover the entire frequency range of the signal output from the PLL circuit unit, the value of the frequency setting signal can be changed. Further, in the embodiment, the frequency of the reference clock signal is calculated by calculation.
The value of the frequency of the reference clock signal corresponding to the frequency output from the L circuit unit may be stored in a table format.

Further, in the embodiment, the universal frequency divider which generates the reference clock signal of the arbitrary frequency from the clock signal by changing the frequency division ratio is used, but it is possible to output the signal of the arbitrary frequency. , But not limited to this.

Further, although the direct digital synthesizer is provided outside the loop of the PLL circuit in the embodiment, it may be incorporated in the loop. For example, the output of the frequency divider in the loop is input as the reference clock signal of the direct digital synthesizer. The direct digital synthesizer is set so as to output a signal having a frequency of 1 / N of the output of the frequency divider. For example, this is set to a quarter frequency. The output of the direct digital synthesizer and the output of the universal frequency divider are input to the phase comparator of the PLL circuit section. The frequency of the signal to be output by the PLL circuit section is divided by the frequency division ratio of the frequency divider, and this is further divided by the direct digital
It is set so that the universal frequency divider outputs a signal having a quarter frequency according to the setting value of the synthesizer. Even in this case, it is possible to obtain the frequency synthesizer in which the generation of spurious is suppressed.

[0028]

According to the first aspect of the present invention, the oscillation frequency of the oscillator is adjusted in accordance with the frequency of the signal to be output in the state where a small ratio of spurious prepared in advance is set in the direct digital synthesizer. Have changed. This allows the direct digital synthesizer to output a signal having an arbitrary frequency with less spurious.

According to the second aspect of the invention, the oscillation frequency of the oscillator is changed according to the frequency of the signal to be output in a state where a small ratio of spurious prepared in advance is set in the direct digital synthesizer. are doing. This allows the direct digital synthesizer to output a signal having an arbitrary frequency with less spurious. Furthermore, by using the output of the direct digital synthesizer as the signal to be compared in the phase of the phase locked loop, it is possible to obtain a signal of an arbitrary frequency locked with a phase with less spurious from the output of the phase locked loop. Further, if a frequency divider is provided in the phase locked loop, a signal having a frequency obtained by multiplying the frequency output by the direct digital synthesizer by a frequency division ratio can be output from the phase locked loop, and a high frequency signal can be obtained. .

According to the third aspect of the invention, the ratio of 1 / N of 2 is set in the direct digital synthesizer. By setting a ratio of 1 to the Nth power of 2, it is possible to obtain an output signal with less spurious from the direct digital synthesizer.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a circuit configuration of a PLL frequency synthesizer which is an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a circuit configuration of a PLL frequency synthesizer using a direct digital synthesizer which has been conventionally used.

FIG. 3 is a block diagram showing an outline of a circuit configuration of a direct digital synthesizer.

[Explanation of symbols]

 11 PLL Circuit Section 13 Phase Comparison Reference Signal Generation Section 23 Direct Digital Synthesizer 43 Universal Divider 45 Reference Frequency Calculation Circuit 46 Ratio Register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Yoshida 8-1 Minamikurokawa, Aso-ku, Kawasaki City, Kanagawa Prefecture

Claims (3)

[Claims] 1. An oscillator having a variable oscillation frequency, a direct digital synthesizer which outputs a signal obtained by converting the frequency of a signal output from this oscillator into a frequency of a set ratio, and a direct digital synthesizer of the direct digital synthesizer. A ratio setting means for setting a pre-prepared ratio in the direct digital synthesizer to reduce spurious contained in the output signal, and the frequency of the signal to be output from the direct digital synthesizer as the oscillation frequency of the oscillator. A frequency synthesizer, comprising: an oscillation frequency setting means for setting a frequency obtained as a result of dividing by the ratio set by the ratio setting means. 2. An oscillator having a variable oscillation frequency, a direct digital synthesizer for outputting a signal obtained by converting a frequency of a signal output by the oscillator into a frequency having a set ratio, and a direct digital synthesizer of the direct digital synthesizer. A ratio setting means for setting a pre-prepared ratio in the direct digital synthesizer to reduce spurious contained in the output signal, and the frequency of the signal to be output from the direct digital synthesizer as the oscillation frequency of the oscillator. An oscillation frequency setting means for setting a frequency obtained as a result of dividing by the ratio set by the ratio setting means, and a phase locked loop for inputting the output of the direct digital synthesizer as a signal for phase comparison are provided. Frequency characterized by Synthesizer. 3. The frequency synthesizer according to claim 1, wherein the ratio set by the ratio setting means is 1 / N of 2 (N is an integer of 1 or more).