JPH0783452B2 - Digital TV video signal special effect device - Google Patents

Description

The present invention relates to a digital television video signal special effect device.

[Conventional technology]

In a conventional television video signal special effect device, an image in which a specific portion of the image is replaced with specific pixel data is "1" for a pixel to be replaced corresponding to each pixel, and other pixels. However, the key signal having a value of "0" is generated, and the original image is combined with the image in which all the one image has specific pixel data.

[Problems to be Solved by the Invention]

In the above-described conventional television video signal special effect device, an image in which all the one image has specific pixel data is combined with the original image. There was a problem that it was necessary to have another circuit.

[Means for Solving the Problems]

A digital television video signal special effect device of the present invention stores an A / D converter that encodes an analog video signal to obtain a coded video signal and an output video signal of this A / D converter for one image. An image memory, a write address generator for determining the location of the image memory to be written corresponding to the location of the input image, and a read address generator for reading each pixel data of the image from the image memory. And a digital television video signal special effect device comprising a D / A converter for decoding the coded video signal read out from the image storage device into an analog signal, any chroma level, brightness level, color A pixel data generator for generating pixel data having a phase and a control signal generated by the write address generator generate the input of the image memory by the pixel data generator. Input image switch for switching to either pixel data or pixel data from the A / D converter, and the same read address as the write address generated when the write address generator generated the control signal. A constant read address generator and a read address switcher for switching between the address generated by the constant read address generator and the address generated by the read address generator are provided.

[Work]

In the present invention, by adding a pixel data generator and further combining a read address switching device, two images are combined without having an image combining circuit.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, 1 is an input terminal to which an analog television signal is applied, and 2 is an analog-digital converter (hereinafter referred to as an A / D converter) that encodes an analog video signal from the input terminal 1 to obtain a coded video signal. (Abbreviated) 3 is a write address generator that determines the location of the image memory to be written corresponding to the location of the input image, 4 is a pixel that generates pixel data having an arbitrary chroma level, luminance level, and color phase The data generator 5 switches the input of the image memory to either the pixel data generated by the pixel data generator 4 or the pixel data from the A / D converter 2 according to the control signal generated by the write address generator 3. Input image switching device, 6 is an image storage device that stores the output video signal of the A / D converter 2 for one image, and 7 is a reading for reading each pixel data of the image from the image storage device 6. Address generator, 8 is a constant read address generator that generates the same read address as the write address generated when the write address generator 3 generates a control signal, and 9 is the address generated by this constant read address generator 8. And an address generated by the read address generator 7, a read address switch, 10 is a background adder, and 11 is a digital-analog converter that decodes the coded video signal read from the image memory 6 into an analog signal. (Less than,
(Abbreviated as D / A converter), 12 is a sync signal adder that receives the output of this D / A converter 11 and adds a sync signal supplied from an input terminal 15, and 13 of this sync signal adder 12. An output terminal for obtaining a regular television signal, which is an output, is a clock generator.

The operation of the embodiment shown in FIG. 1 will be described below.

First, the analog television video signal input from the input terminal 1 is encoded into an 8-bit binary code by the A / D converter 2, and the writing address generator 3 is processed by the A / D converter 2 or the pixel data. The X and Y coordinates on the image of the video signal output by the generator 4 are output. This writing address generator 3
Sends a control signal of logical value "1" to the input image switching device 5 when the address X = 0 and Y = 0 is generated, and the input image switching device 5 sends the pixel data generator 4 to the image storage device 6. Output the generated data. Further, the writing address generator 3 has a logical value "0" so that the output to the image memory 6 becomes the A / D converter 2 when the other addresses are generated.
To the input image switching device 5. And
The image memory 4 stores the X output from the writing address generator 3.
The video signal output from the A / D converter 2 or the pixel data generator 4 is written in an address uniquely determined by the coordinates and the Y coordinate, and is stored until the next field.

Next, the read-out address generator 5 calculates the stored x-coordinates and y-coordinates of the video signal to be read out from the X-coordinates and Y-coordinates of the image, and outputs them to the read-out address switching unit 9. Since the read address generator 7 has two kinds of address generating circuits inside, when one circuit outputs an address, a logical value "1" is output to the read address switching device 9 as a control signal and the other address generating circuit is output. When the circuit outputs an address, the logical value "0" is read as a control signal and the address switch 9
Output to. Then, the constant read address generator 8 has x = 0.
And an address of y = 0 is generated. This is the address where the pixel data generated by the pixel data generator 4 is written. The read address switch 9 receives a control signal from the read address generator 7, and the control signal is a logical value “1”.
Then, the address generated by the constant read address generator 8 is output to the image memory 6, and if the control signal is a logical value "0", the address generated by the read address generator 7 is output to the image memory 6.
The image storage device 6 outputs the write address generator 3 from the x-coordinate and the y-coordinate output from the read address switching device 9 for the video signal stored one field before in parallel with the writing of the video signal. The video signal of the address determined by the method of determining the address to be written is read from the X coordinate and the Y coordinate and output to the background adder 10. Then, the background is added by the background adder 10 by the in-range instruction signal AS output from the read address generator 7, and its output is output by the D / A converter 1.
It goes into 1 and is decoded, and this decoded output is the sync signal adder 12
Then, the synchronizing signal supplied from the input terminal 15 is added to form a regular television signal, which is output from the output signal 13.

Then, the clock generator 14 generates a clock indicating the main operation timing of each component, and this clock is A / D.
It is supplied to the converter 2, the write address generator 3, the image memory 6, the read address generator 7 and the D / A converter 11, respectively.

FIG. 2 is a block diagram showing an embodiment of the read address generator 7, constant read address generator 8 and read address switching device 9 in FIG.

In FIG. 2, 36 is an input terminal to which a clock signal is input, 16 and 17 are an X coordinate generator and a Y coordinate generator which operate in synchronization with the clock signal input from this input terminal 36, and 18 is a constant a. Generator, 19 is a constant b generator, 20 is a constant c generator, 21 is a coordinate x, y respectively output from the X coordinate generator 16 and the Y coordinate generator 17, a constant a generator 18 and a constant b
The distance from the generator 19 and the constant c generator 20 to the point represented by (X, Y) from a straight line γ expressed as a set of points satisfying ax + by + c = 0, where x and y coordinates are variables. On the other hand, for the two areas divided by γ, the amount given the code determined by the area to which the point (X, Y) belongs Is a distance calculator that calculates and outputs.

22 is a memory that generates a function f using a memory in which an appropriate value is written so that the value read out is a function f (u) of u when a read address is input u in advance for a readable / writable memory. , 23 is a function g (u) whose value is u when the read address is input in advance for a readable / writable memory like this memory 22.
Is a memory for generating a function g using a memory in which an appropriate value is written as Then, in the memories 22 and 23, AD indicates an address and DT indicates output data.

24 is a × f with a and X and f (d) as inputs
A coordinate calculator 25 calculates (d) + X and outputs it, and a coordinate calculator 25 calculates and outputs b × f (d) + Y with b and Y and f (d) as inputs. 26 is a constant X address generator for generating a constant x = 0, and 27 is a constant Y address generator for generating a constant y = 0, which constitute a read address generator. 28 is a coordinate calculator that inputs a and X and g (d) to calculate and outputs a × g (d) + X, and 29 is b × g that receives b and Y and g (d) as inputs.
(D) A coordinate calculator that calculates and outputs + Y.

30 is a switching signal generator that outputs a control signal to the X address switching device, 31 is an X address that switches the output from the constant X address generator 26 and the output from the coordinate calculator 28 with the control signal from the switching signal generator 30 Is a switching device,
When the switching signal generator 30 generates a logical value "1", the output of the constant X address generator 26 is output to the data selector, and when the switching signal generator 30 generates a logical value "0", the output of the coordinate calculator 28 is data. Output to the selector. 32 is a constant Y address generator
Y to switch the output from 27 and the output from the coordinate calculator 29
An address switcher, which outputs the output of the constant Y address generator 27 to the data selector when the switching signal generator 30 generates a logical value "1", and calculates the coordinates when a logical value "0" is generated. The output of the device 29 is output to the data selector.
The switching signal generator 30, the X address switching device 31, and the Y address switching device 32 constitute a read address switching device.

33 is a constant m equal to or less than the value output from the coordinate calculator 28 and equal to the maximum value of the X coordinate, and the coordinate calculator 29
A constant comparator that outputs a logical value "1" only when the output value is 0 or more and is a constant n or less equal to the maximum value of the Y coordinate, and outputs a logical value "0" otherwise. Is an output terminal when the output of this constant comparator 33 is a logical value "1"
The output value of the coordinate calculator 24 is output to 37, the output value of the coordinate calculator 25 is output to the output terminal 38, and when the output of the constant comparator 33 is the logical value "0", the coordinate value is calculated to the output terminal 37. A data selector configured to output the output value of the output device 28 and the output value of the coordinate calculator 29 to the output terminal 38, and 35 is a value output to the output terminal 37 of 0 or more and the maximum X coordinate. The logical value "1" is output only when the value output to the output terminal 38 is 0 or more and is equal to or less than the constant n that is equal to the maximum value of the Y coordinate when the value output to the output terminal 38 is 0 or more. It is a constant comparator that outputs a logical value "0" to the output terminal 39. Then, the read X coordinate, the read Y coordinate, and the designated output within the range are obtained at the output terminals 37, 38, and 39, respectively.

Here, it is assumed that the function f and the function g are defined as follows.

However, K is a constant equal to 1/2 of the pi, r is a constant, and ∞ is the maximum value of the X coordinate m even though the output value of the coordinate calculator 24,25,28,29 is less than 0. And the maximum value of Y coordinate n
Use a constant that is a sufficiently large value. Also, y = sin ^-1
(X) indicates that the range of x is − for the trigonometric function y = sin (x).
It is an inverse function in π / 2 ≦ x ≦ π / 2.

A graph of the function f, that is, the function y written in the memory 22 for generating the function f of FIG.
= F (x) is shown in a graph in FIG. 3, and the function g is shown in a graph, that is, the function y = g (x) written in the memory 23 for generating the function g in FIG. Fig. 4 shows a graph of the above.

Also here And constant a such that a <0 and b <0 and 0 <c <n,
Define constant b and constant c respectively.

The operation of the embodiment in this case will be described.

The image shown in FIG. 5 showing an example of the image inputted to the television video signal special effect device shown in FIG. 1 is inputted. The input image data is stored in the image storage unit 6 for one field time. Then, in the next field, a value d = aX + bY determined by the position of the pixel data displayed on each X coordinate and Y coordinate and the straight line γ: ax + by + c = 0.
+ C is calculated by the distance calculator 21 shown in FIG. 2, and af (d) + X and bf (d) + Y and ag (d) + X and bg (d) + Y are calculated by the read address generator 7 shown in FIG. To be done. When the switching signal generator 30 of FIG. 2 generates a logical value "1" and the output of the constant comparator 35 of FIG. 2 is a logical value "0", ag (d) + X, bg (d ) + Y is output to the image memory 6 of FIG. 1 as the X and Y coordinates for reading the video signal, the pixel generated by the pixel data generator 4 is read.

As a result, the output image is an explanatory diagram showing an example of the image input to the embodiment of FIG. 1. It is an explanatory diagram showing an output image obtained by using the image shown in FIG. 5 as an input.
As shown in the figure, the paper placed on the plane is transformed into a shape folded along a cylinder having a radius r, and the folded image is a uniform image generated by the pixel data generator 4. Become. In FIG. 6, S is represented by S = | K _r −r |.

〔The invention's effect〕

As described above, according to the present invention, by adding an image data generator and further combining a read address switching device, it is possible to create an effect of combining two images without having an image combining circuit. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an embodiment of a read address generator, a constant read address generator and a read address switching device in FIG. 1, and FIG. Explanatory drawing showing a graph of a function y = f (x) written in a memory for generating the function f of FIG.
FIG. 4 is a graph showing the function y = g (x) written in the memory for generating the function g of FIG. 2, and FIG. 5 is an example of the image input to the embodiment of FIG. Explanatory diagram showing
FIG. 6 is an explanatory diagram showing an output image obtained by inputting the image shown in FIG. 5 to the embodiment shown in FIG. 2 ... A / D converter, 3 ... Writing address generator, 4 ...
Pixel data generator, 5 ... Input image switcher, 6 ...
Image memory, 7 ... Read-out address generator, 8 ... Constant read-out address generator, 9 ... Read-out address switching device, 11 ... D /
A converter.

Claims (1)

[Claims] 1. An A / D converter that encodes an analog video signal to obtain a coded video signal, an image memory that stores one image of the output video signal of this A / D converter, and a location of an input image. A write address generator for determining the location of the image store to be written corresponding to, a read address generator for reading each pixel data of the image from the image store, and a read address generator for reading. A pixel for generating pixel data having an arbitrary chroma level, luminance level, and color phase in a digital television video signal special effect device equipped with a D / A converter for decoding the encoded video signal converted into an analog signal. A data generator and a control signal generated by the write address generator are used to input the image memory to the pixel data generated by the pixel data generator or the pixel data from the A / D converter. The input image switching device for switching to the small one, the constant read address generator for generating the same read address as the write address generated when the write address generator generates the control signal, and the constant read address generator. A digital television video signal special effect device comprising a read address switching device for switching the generated address and the address generated by the read address generator.