JPH0783507B2 - Scan detection interface circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] A current mirror having two output terminals each of which outputs the same output current as an input current, a current limiting circuit, and a voltage compensating circuit are suitable for miniaturization. A scan detection interface circuit capable of reducing power consumption is constructed.

[Industrial application field]

The present invention relates to improvements in scan detect interface circuits used in subscriber circuits of digital exchanges.

The subscriber circuit of the digital exchange monitors the call current supplied to the accommodated subscriber and notifies the control circuit, which performs call processing, of the monitoring result as a scan output. As a method of monitoring the call current, a monitor voltage proportional to the call current is compared with a predetermined threshold voltage, and a scan output is output when the monitor voltage is equal to or higher than the threshold voltage.

Since the call current supplied to the subscriber is normally supplied from the main power source of the exchange with the + pole grounded, the monitoring voltage also becomes a negative voltage with respect to the ground.

On the other hand, in order to miniaturize the subscriber circuit, it is desired that the comparison circuit of the monitoring voltage and the threshold voltage is also composed of a circuit which operates with a single +5 volt power source such as a CMOS comparator. For that purpose, the monitoring voltage also needs to be a positive voltage with respect to the ground. Therefore, it becomes necessary to reverse the polarity of the negative voltage proportional to the speech current and convert it into a positive voltage.

It is strongly demanded for the circuit used for such polarity reversal to be realized by a circuit having the smallest possible number of constituent parts and low power consumption for miniaturization and high-density mounting of the subscriber circuit.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional scan detection interface circuit in a subscriber circuit of a digital exchange.

In FIG. 3, the power supply monitoring circuit 1 supplies the calling current I _L to the subscriber 2 from the main power source of the switch of −48 V, and also supplies the monitoring voltage V ₀ (negative voltage) proportional to the calling current I _L. ,
Output to monitor the call current I _L.

The monitoring voltage V ₀ is an operational amplifier 3 is transferred to the configured scan detection interface circuit 6 from the resistor 4 and 5, the monitoring voltage V ₀ and equal absolute values, of different polarity output voltage V
_It is converted to ₁ (positive voltage) and transmitted to the comparator 7.

The comparator 7 compares the transmitted output voltage V ₁ with the threshold voltage V _th, and when the output voltage V ₁ is lower than the threshold voltage V _th , sets the scan output SCN to be output to a logical value 0, and outputs it. Scan output SCN to be output when voltage V ₁ is higher than threshold voltage V _th
Is set to a logical value of 1.

[Problems to be solved by the invention]

As is clear from the above description, the conventional scanning detection interface circuit 6 is mainly composed of the operational amplifier 3. The operational amplifier 3 is composed of a large number of transistors and consumes a little electric power even when the monitor voltage V ₀ is 0 V, which may impair the downsizing of the subscriber circuit.

[Means for solving problems]

 FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, the scan detection interface circuit 6'is
A current mirror 8 having a first output terminal 82 and a second output terminal 83 that output the same output current as the input current, and an input resistor 9 connected to the input terminal 81 of the current mirror 8.
A current limiting circuit 10 inserted between the input terminal 81 and the input resistor 9 for limiting an input current equal to or more than a predetermined value; an output resistor 11 connected to the first output terminal 82 of the current mirror 8; The potential at the connection point between the input resistor 9 and the current limiting circuit 10 is connected to the second output terminal 83 of the current mirror 8,
And a voltage compensating circuit 12 for compensating to a predetermined potential when the input current is below the predetermined value.

[Action]

That is, according to the present invention, a scan detection interface circuit having a smaller number of components such as transistors as compared with the conventional scan detection interface circuit is realized, and when the input voltage is 0 V, the internal power consumption becomes almost 0, and further, When the input current is less than or equal to a predetermined value, the absolute value of the input voltage and the output voltage is proportional to the high accuracy, but when the input current is greater than or equal to the predetermined value, the input current is limited and power consumption is reduced. A scan detection interface circuit is realized, and miniaturization and high-density packaging of the subscriber circuit are promoted.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a scan detection interface circuit according to an embodiment of the present invention.

In FIG. 2, the current mirror 8 is a transistor 84.
Through 87, and the current limiting circuit 10 includes transistors 101 and 102.

The input resistor 9 is divided into resistors 91 and 92, and the emitter of the transistor 92 is connected to the midpoint of the division.

The voltage compensation circuit 12 includes a transistor 121 and a resistor 12 having the same resistance value (for example, 20 to 40 kΩ).
Consists of 2 and 123.

The current mirror 8 outputs output currents I ₁ and I ₂ equal to the input current I ₀ flowing through the input terminal 81 from the output terminals 82 and 83, and the output current I ₁ is the scan detection interface circuit 6 '.
The output current I ₂ flows to the ground potential via the output resistance 11 of the output current I _{2 and} the voltage compensating circuit 12.

In the transistor 121 of the voltage compensation circuit 12, the emitter E ₁₂₁ is grounded and the collector C ₁₂₁ of the base B ₁₂₁ is connected to the resistor 123, so that the output current I _{2 of the} current mirror 8 is
There flows to the transistor 121, the base potential V _{B 121} of transistor 121, the collector potential V _{C 121} of the base-emitter voltage V _BE121 (≒ 0.7 volts) and [V _B121 = V _BE121] The transistors 121 of the transistor 121, the transistor The value obtained by adding the voltage drop V ₁₂₃ [= I _B121 × R ₁₂₃ ] across the resistor 123 due to the base current I _B121 of ₁₂₁ and the base-emitter voltage V _EB121 [V _C121 = V ₁₂₃ + V _BE121 = I
_B121 × R ₁₂₃ + V _B121 ].

The collector C _{121 of the} transistor 121 is the current limiting circuit 1
Since it is connected to the base B ₁₀₁ of the transistor 101 in 0 through the resistor 122, when the input current I ₀ of the current mirror 8 flows through the transistor 101, the base potential V _B101 of the transistor 101 changes to the base of the transistor 101. Current I _B101
Voltage drop across resistor 122 due to V ₁₂₂ [= I _B101 ×
R ₁₂₂ ] is a value obtained by subtracting the collector potential V _C121 of the transistor 121 from [V _B101 = V _C121 −V ₁₂₂ = V _C121 −I _B101 ×
R ₁₂₂ ], and the emitter potential V _E101 of the transistor 101 is
From the base potential V _{B101 of} transistor ₁₀₁ to transistor 10
Value obtained by subtracting the voltage V _BE101 (≈ 0.7 volt) between base mitters of 1 [V _E101 = V _B101 -V _BE101 = V _C121 -I _B101 × R ₁₂₂ -V
_BE101 ].

When the transistor 102 in the current limiting circuit 10 is in the cutoff state, the input current I ₀ and the output current I ₂ of the current mirror 8 are
And therefore equal currents will flow through transistors 101 and 121, resulting in both transistors
Base emitter voltage of 101 and 121 V _BE101 and V
_BE121, and the base current I _B101 and I _{B 121} are equal, respectively _{[V BE101 = V BE121, I B101} = I B121 ].

Since the resistance values R ₁₂₂ and R 123 of the resistors ₁₂₂ and ₁₂₃ are determined to be equal, the base potential V of the transistor 101 is
_B101 becomes equal to the base potential V _B121 of the transistor 121 [V _B101 = V _C121 −I _B101 × R ₁₂₂ = V _C121 −I _B121 × R ₁₂₃
= V _B121 ], and the emitter potential of transistor 101 V _E101
It is equal to the emitter potential V _E121 of transistor 121, a ground potential _{[V E101 = V B101 -V BE101 =} V B121 -V BE121 = V
_E121 = earth potential].

As described above, the voltage compensating circuit 12 includes the emitter potential V _E101 of the transistor 101 in the current control circuit 10, that is, the current limiting circuit.
It serves to maintain the connection point between 10 and the input resistor 9 at an accurate ground potential.

In such a case, when the monitor voltage V ₀ (negative voltage) is applied between the input terminals 13 of the scan detection interface circuit 6 ′,
The input current I ₀ of the current mirror 8 and the output voltage V ₁ output between the output terminals 14 of the scan detection interface circuit 6 '.
Are represented by equations (1) and (2), respectively.

I ₀ = -V ₀ / R ₉ (1) V ₁ = I ₁ · R ₁₁ = I ₀ · R ₁₁ … (2) (However, R ₉ and R ₁₁ are resistance values of resistors 9 and 11, and so on.) Now, the resistance values R ₉ and R _{11 of} the input resistor 9 and the output resistor ₁₁
Are set to be equal (for example, 10 kOhm), the output voltage V ₁ is expressed by the equation (3).

V ₁ = −V ₀ (3) That is, the output voltage V ₁ is a positive voltage whose absolute value is equal to that of the monitor voltage V ₀ .

Here, when the resistance values of the resistors 91 and 92 which form the input resistor 9 are set to R ₉₁ = 1.8 k ohm and R ₉₂ = 8.2 k ohm, respectively, when the monitoring voltage V ₀ is 0 V to −3 V, The voltage across resistor 91 is transistor 102
Since the base Etta voltage of V _{BE is} less than (0.7 volt),
The transistor 102 is turned off, and the equation (3) is established.

On the other hand, when the monitor voltage V1 becomes -4 V or lower, the voltage across the resistor 91 becomes higher than the base-emitter voltage V _{BE of} the transistor 102, so that the transistor 102 becomes conductive and the emitter potential of the transistor 101 is reduced to the ground potential or lower. Let
The input current I ₀ of the current mirror 8 is limited to the equation (4).

I ₀ = V _BE / R ₉₁ (4) As a result, the output voltage V ₁ is also limited to the value shown in the equation (5).

V ₁ = (V _BE / R ₉₁ ) · R ₁₁ (5) As is apparent from the above description, according to this embodiment, the current mirror 8 having a smaller number of transistors than the operational amplifier 3 (FIG. 3) is used. The scan detection interface circuit 6'is configured, and when the monitor voltage V ₀ is 0 volt, the power consumption becomes almost 0. Further, when the monitor voltage V ₀ is 0 to -3 volts, the monitor voltage V ₀ is Positive voltage output voltage with the same absolute value
When V ₁ is output and the monitor voltage V ₀ becomes -4 V or less, the scan detection interface circuit 6 ′ is realized in which the output voltage V ₁ is limited to the value shown in the equation (5).

Thus (5) the limit value of the output voltages V ₁ shown in formula, by setting a sufficiently large value than the threshold voltage V _th of the comparator 7 outputs voltages V ₁ is transmitted, the scanning output by the comparator 7 SCN
The power consumption of the scan detection interface circuit 6'can be reduced without lowering the detection accuracy.

It is to be noted that FIG. 1 is merely an embodiment of the present invention, and the resistance values of the resistors 91, 92, 11, 121 and 122 are not limited to the illustrated ones, and many other modifications are possible. Is considered, the descent of the invention does not change in either case.

〔The invention's effect〕

As described above, according to the present invention, a scan detection interface circuit having a smaller number of components such as transistors and a reduced power consumption as compared with a conventional scan detection interface circuit is realized, and the subscriber circuit is downsized and has a high density. Implementation is promoted.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a scan detection interface circuit according to an embodiment of the present invention, and FIG.
FIG. 1 is a diagram showing an example of a conventional scan detection interface circuit. In the figure, 1 is a power supply monitoring circuit, 2 is a subscriber, 3 is an operational amplifier, 4, 5, 91, 92, 122 and 123 are resistors, 6 and 6'are scan detection interface circuits, 7 is a comparator, and 8 is a comparator.
Is a current mirror, 9 is an input resistor, 10 is a current limiting circuit,
11 is the output resistance, 12 is the voltage compensation circuit, 13 is the input terminal, 14 is the output terminal, 81 is the input terminal of the current mirror, 82 and 83
Is an output terminal of the current mirror, 84 to 87, 101, 102 and 121 are transistors, I _L is a call current, I ₀ is an input current, I
₁ and I ₂ are the output current, SCN is the scan output, V ₀ is the monitor voltage,
V ₁ indicates the output voltage and V _th indicates the threshold voltage.

Claims (1)

[Claims] 1. A first output terminal (82) and a second output terminal (83) which respectively output the same output current as the input current.
A current mirror (8) having an input resistor, an input resistor (9) connected to an input terminal (81) of the current mirror (8), and inserted between the input terminal (81) and the input resistor (9). , A current limiting circuit (1
0), an output resistor (11) connected to the first output terminal (82) of the current mirror (8), and a second output terminal (83) of the current mirror (8), Input resistance (9) and the current limiting circuit (10)
And a voltage compensating circuit 12 for compensating the electric potential at the connection point with the electric current to a predetermined potential when the input current is equal to or less than the predetermined value.